1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any
6*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above
7*5113495bSYour Name * copyright notice and this permission notice appear in all copies.
8*5113495bSYour Name *
9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
16*5113495bSYour Name */
17*5113495bSYour Name #ifndef _HAL_6432_TX_H_
18*5113495bSYour Name #define _HAL_6432_TX_H_
19*5113495bSYour Name
20*5113495bSYour Name #include "tcl_data_cmd.h"
21*5113495bSYour Name #include "phyrx_rssi_legacy.h"
22*5113495bSYour Name #include "hal_internal.h"
23*5113495bSYour Name #include "qdf_trace.h"
24*5113495bSYour Name #include "hal_rx.h"
25*5113495bSYour Name #include "hal_tx.h"
26*5113495bSYour Name #include "hal_api_mon.h"
27*5113495bSYour Name #include <hal_be_tx.h>
28*5113495bSYour Name
29*5113495bSYour Name #define DSCP_TID_TABLE_SIZE 24
30*5113495bSYour Name #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
31*5113495bSYour Name #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
32*5113495bSYour Name #define HAL_PPE_VP_ENTRIES_MAX 32
33*5113495bSYour Name #define HAL_PPE_VP_SEARCH_IDX_REG_MAX 8
34*5113495bSYour Name
35*5113495bSYour Name /**
36*5113495bSYour Name * hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432() - get number of PPE VP
37*5113495bSYour Name * search index registers
38*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
39*5113495bSYour Name *
40*5113495bSYour Name * Return: Number of PPE VP search index registers
41*5113495bSYour Name */
42*5113495bSYour Name static uint32_t
hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432(hal_soc_handle_t hal_soc_hdl)43*5113495bSYour Name hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432(hal_soc_handle_t hal_soc_hdl)
44*5113495bSYour Name {
45*5113495bSYour Name return HAL_PPE_VP_SEARCH_IDX_REG_MAX;
46*5113495bSYour Name }
47*5113495bSYour Name
48*5113495bSYour Name /**
49*5113495bSYour Name * hal_tx_set_dscp_tid_map_6432() - Configure default DSCP to TID map table
50*5113495bSYour Name * @hal_soc: HAL SoC context
51*5113495bSYour Name * @map: DSCP-TID mapping table
52*5113495bSYour Name * @id: mapping table ID - 0-31
53*5113495bSYour Name *
54*5113495bSYour Name * DSCP are mapped to 8 TID values using TID values programmed
55*5113495bSYour Name * in any of the 32 DSCP_TID_MAPS (id = 0-31).
56*5113495bSYour Name *
57*5113495bSYour Name * Return: none
58*5113495bSYour Name */
hal_tx_set_dscp_tid_map_6432(struct hal_soc * hal_soc,uint8_t * map,uint8_t id)59*5113495bSYour Name static void hal_tx_set_dscp_tid_map_6432(struct hal_soc *hal_soc, uint8_t *map,
60*5113495bSYour Name uint8_t id)
61*5113495bSYour Name {
62*5113495bSYour Name int i;
63*5113495bSYour Name uint32_t addr, cmn_reg_addr;
64*5113495bSYour Name uint32_t value = 0, regval;
65*5113495bSYour Name uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
66*5113495bSYour Name
67*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
68*5113495bSYour Name
69*5113495bSYour Name if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS_6432)
70*5113495bSYour Name return;
71*5113495bSYour Name
72*5113495bSYour Name cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
73*5113495bSYour Name MAC_TCL_REG_REG_BASE);
74*5113495bSYour Name
75*5113495bSYour Name addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
76*5113495bSYour Name MAC_TCL_REG_REG_BASE,
77*5113495bSYour Name id * NUM_WORDS_PER_DSCP_TID_TABLE);
78*5113495bSYour Name
79*5113495bSYour Name /* Enable read/write access */
80*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
81*5113495bSYour Name regval |=
82*5113495bSYour Name (1 <<
83*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
84*5113495bSYour Name
85*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
86*5113495bSYour Name
87*5113495bSYour Name /* Write 8 (24 bits) DSCP-TID mappings in each iteration */
88*5113495bSYour Name for (i = 0; i < 64; i += 8) {
89*5113495bSYour Name value = (map[i] |
90*5113495bSYour Name (map[i + 1] << 0x3) |
91*5113495bSYour Name (map[i + 2] << 0x6) |
92*5113495bSYour Name (map[i + 3] << 0x9) |
93*5113495bSYour Name (map[i + 4] << 0xc) |
94*5113495bSYour Name (map[i + 5] << 0xf) |
95*5113495bSYour Name (map[i + 6] << 0x12) |
96*5113495bSYour Name (map[i + 7] << 0x15));
97*5113495bSYour Name
98*5113495bSYour Name qdf_mem_copy(&val[cnt], (void *)&value, 3);
99*5113495bSYour Name cnt += 3;
100*5113495bSYour Name }
101*5113495bSYour Name
102*5113495bSYour Name for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
103*5113495bSYour Name regval = *(uint32_t *)(val + i);
104*5113495bSYour Name HAL_REG_WRITE(soc, addr,
105*5113495bSYour Name (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
106*5113495bSYour Name addr += 4;
107*5113495bSYour Name }
108*5113495bSYour Name
109*5113495bSYour Name /* Disable read/write access */
110*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
111*5113495bSYour Name regval &=
112*5113495bSYour Name ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
113*5113495bSYour Name
114*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
115*5113495bSYour Name }
116*5113495bSYour Name
117*5113495bSYour Name /**
118*5113495bSYour Name * hal_tx_update_dscp_tid_6432() - Update the dscp tid map table as updated
119*5113495bSYour Name * by the user
120*5113495bSYour Name * @soc: HAL SoC context
121*5113495bSYour Name * @tid: DSCP-TID mapping table
122*5113495bSYour Name * @id : MAP ID
123*5113495bSYour Name * @dscp: DSCP_TID map index
124*5113495bSYour Name *
125*5113495bSYour Name * Return: void
126*5113495bSYour Name */
hal_tx_update_dscp_tid_6432(struct hal_soc * soc,uint8_t tid,uint8_t id,uint8_t dscp)127*5113495bSYour Name static void hal_tx_update_dscp_tid_6432(struct hal_soc *soc, uint8_t tid,
128*5113495bSYour Name uint8_t id, uint8_t dscp)
129*5113495bSYour Name {
130*5113495bSYour Name uint32_t addr, addr1, cmn_reg_addr;
131*5113495bSYour Name uint32_t start_value = 0, end_value = 0;
132*5113495bSYour Name uint32_t regval;
133*5113495bSYour Name uint8_t end_bits = 0;
134*5113495bSYour Name uint8_t start_bits = 0;
135*5113495bSYour Name uint32_t start_index, end_index;
136*5113495bSYour Name
137*5113495bSYour Name cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
138*5113495bSYour Name MAC_TCL_REG_REG_BASE);
139*5113495bSYour Name
140*5113495bSYour Name addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
141*5113495bSYour Name MAC_TCL_REG_REG_BASE,
142*5113495bSYour Name id * NUM_WORDS_PER_DSCP_TID_TABLE);
143*5113495bSYour Name
144*5113495bSYour Name start_index = dscp * HAL_TX_BITS_PER_TID;
145*5113495bSYour Name end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
146*5113495bSYour Name % HAL_TX_NUM_DSCP_REGISTER_SIZE;
147*5113495bSYour Name start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
148*5113495bSYour Name addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
149*5113495bSYour Name HAL_TX_NUM_DSCP_REGISTER_SIZE));
150*5113495bSYour Name
151*5113495bSYour Name if (end_index < start_index) {
152*5113495bSYour Name end_bits = end_index + 1;
153*5113495bSYour Name start_bits = HAL_TX_BITS_PER_TID - end_bits;
154*5113495bSYour Name start_value = tid << start_index;
155*5113495bSYour Name end_value = tid >> start_bits;
156*5113495bSYour Name addr1 = addr + 4;
157*5113495bSYour Name } else {
158*5113495bSYour Name start_bits = HAL_TX_BITS_PER_TID - end_bits;
159*5113495bSYour Name start_value = tid << start_index;
160*5113495bSYour Name addr1 = 0;
161*5113495bSYour Name }
162*5113495bSYour Name
163*5113495bSYour Name /* Enable read/write access */
164*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
165*5113495bSYour Name regval |=
166*5113495bSYour Name (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
167*5113495bSYour Name
168*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
169*5113495bSYour Name
170*5113495bSYour Name regval = HAL_REG_READ(soc, addr);
171*5113495bSYour Name
172*5113495bSYour Name if (end_index < start_index)
173*5113495bSYour Name regval &= (~0) >> start_bits;
174*5113495bSYour Name else
175*5113495bSYour Name regval &= ~(7 << start_index);
176*5113495bSYour Name
177*5113495bSYour Name regval |= start_value;
178*5113495bSYour Name
179*5113495bSYour Name HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
180*5113495bSYour Name
181*5113495bSYour Name if (addr1) {
182*5113495bSYour Name regval = HAL_REG_READ(soc, addr1);
183*5113495bSYour Name regval &= (~0) << end_bits;
184*5113495bSYour Name regval |= end_value;
185*5113495bSYour Name
186*5113495bSYour Name HAL_REG_WRITE(soc, addr1, (regval &
187*5113495bSYour Name HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
188*5113495bSYour Name }
189*5113495bSYour Name
190*5113495bSYour Name /* Disable read/write access */
191*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
192*5113495bSYour Name regval &=
193*5113495bSYour Name ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
194*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
195*5113495bSYour Name }
196*5113495bSYour Name
197*5113495bSYour Name #ifdef DP_TX_IMPLICIT_RBM_MAPPING
198*5113495bSYour Name
199*5113495bSYour Name #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
200*5113495bSYour Name #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
201*5113495bSYour Name
202*5113495bSYour Name #define RBM_TCL_CMD_CREDIT_OFFSET \
203*5113495bSYour Name (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
204*5113495bSYour Name
205*5113495bSYour Name /**
206*5113495bSYour Name * hal_tx_config_rbm_mapping_be_6432() - Update return buffer manager ring id
207*5113495bSYour Name * @hal_soc_hdl: HAL SoC context
208*5113495bSYour Name * @hal_ring_hdl: Source ring pointer
209*5113495bSYour Name * @rbm_id: return buffer manager ring id
210*5113495bSYour Name *
211*5113495bSYour Name * Return: void
212*5113495bSYour Name */
213*5113495bSYour Name static inline void
hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,uint8_t rbm_id)214*5113495bSYour Name hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,
215*5113495bSYour Name hal_ring_handle_t hal_ring_hdl,
216*5113495bSYour Name uint8_t rbm_id)
217*5113495bSYour Name {
218*5113495bSYour Name struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
219*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
220*5113495bSYour Name uint32_t reg_addr = 0;
221*5113495bSYour Name uint32_t reg_val = 0;
222*5113495bSYour Name uint32_t val = 0;
223*5113495bSYour Name uint8_t ring_num;
224*5113495bSYour Name enum hal_ring_type ring_type;
225*5113495bSYour Name
226*5113495bSYour Name ring_type = srng->ring_type;
227*5113495bSYour Name ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
228*5113495bSYour Name ring_num = srng->ring_id - ring_num;
229*5113495bSYour Name
230*5113495bSYour Name reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
231*5113495bSYour Name
232*5113495bSYour Name if (ring_type == PPE2TCL)
233*5113495bSYour Name ring_num = ring_num + RBM_PPE2TCL_OFFSET;
234*5113495bSYour Name else if (ring_type == TCL_CMD_CREDIT)
235*5113495bSYour Name ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
236*5113495bSYour Name
237*5113495bSYour Name /* get current value stored in register address */
238*5113495bSYour Name val = HAL_REG_READ(hal_soc, reg_addr);
239*5113495bSYour Name
240*5113495bSYour Name /* mask out other stored value */
241*5113495bSYour Name val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
242*5113495bSYour Name
243*5113495bSYour Name reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
244*5113495bSYour Name (RBM_MAPPING_SHFT * ring_num));
245*5113495bSYour Name
246*5113495bSYour Name /* write rbm mapped value to register address */
247*5113495bSYour Name HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
248*5113495bSYour Name }
249*5113495bSYour Name #else
250*5113495bSYour Name static inline void
hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,uint8_t rbm_id)251*5113495bSYour Name hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,
252*5113495bSYour Name hal_ring_handle_t hal_ring_hdl,
253*5113495bSYour Name uint8_t rbm_id)
254*5113495bSYour Name {
255*5113495bSYour Name }
256*5113495bSYour Name #endif
257*5113495bSYour Name
258*5113495bSYour Name /**
259*5113495bSYour Name * hal_tx_init_cmd_credit_ring_6432() - Initialize command/credit SRNG
260*5113495bSYour Name * @hal_soc_hdl: Handle to HAL SoC structure
261*5113495bSYour Name * @hal_ring_hdl: Handle to HAL SRNG structure
262*5113495bSYour Name *
263*5113495bSYour Name * Return: none
264*5113495bSYour Name */
265*5113495bSYour Name static inline void
hal_tx_init_cmd_credit_ring_6432(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)266*5113495bSYour Name hal_tx_init_cmd_credit_ring_6432(hal_soc_handle_t hal_soc_hdl,
267*5113495bSYour Name hal_ring_handle_t hal_ring_hdl)
268*5113495bSYour Name {
269*5113495bSYour Name }
270*5113495bSYour Name
271*5113495bSYour Name /* TX MONITOR */
272*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) && defined(TX_MONITOR_WORD_MASK)
273*5113495bSYour Name
274*5113495bSYour Name #define TX_FES_SETUP_MASK 0x3
275*5113495bSYour Name typedef struct tx_fes_setup_compact_6432 hal_tx_fes_setup_t;
276*5113495bSYour Name struct tx_fes_setup_compact_6432 {
277*5113495bSYour Name /* DWORD - 0 */
278*5113495bSYour Name uint32_t schedule_id;
279*5113495bSYour Name /* DWORD - 1 */
280*5113495bSYour Name uint32_t reserved_1a : 7, // [0: 6]
281*5113495bSYour Name transmit_start_reason : 3, // [7: 9]
282*5113495bSYour Name reserved_1b : 13, // [10: 22]
283*5113495bSYour Name number_of_users : 6, // [28: 23]
284*5113495bSYour Name mu_type : 1, // [29]
285*5113495bSYour Name reserved_1c : 2; // [30]
286*5113495bSYour Name /* DWORD - 2 */
287*5113495bSYour Name uint32_t reserved_2a : 4, // [0: 3]
288*5113495bSYour Name ndp_frame : 2, // [4: 5]
289*5113495bSYour Name txbf : 1, // [6]
290*5113495bSYour Name reserved_2b : 3, // [7: 9]
291*5113495bSYour Name static_bandwidth : 3, // [12: 10]
292*5113495bSYour Name reserved_2c : 1, // [13]
293*5113495bSYour Name transmission_contains_mu_rts : 1, // [14]
294*5113495bSYour Name reserved_2d : 17; // [15: 31]
295*5113495bSYour Name /* DWORD - 3 */
296*5113495bSYour Name uint32_t reserved_3a : 15, // [0: 14]
297*5113495bSYour Name mu_ndp : 1, // [15]
298*5113495bSYour Name reserved_3b : 11, // [16: 26]
299*5113495bSYour Name ndpa : 1, // [27]
300*5113495bSYour Name reserved_3c : 4; // [28: 31]
301*5113495bSYour Name };
302*5113495bSYour Name
303*5113495bSYour Name #define TX_PEER_ENTRY_MASK 0x103
304*5113495bSYour Name typedef struct tx_peer_entry_compact_6432 hal_tx_peer_entry_t;
305*5113495bSYour Name struct tx_peer_entry_compact_6432 {
306*5113495bSYour Name /* DWORD - 0 */
307*5113495bSYour Name uint32_t mac_addr_a_31_0 : 32;
308*5113495bSYour Name /* DWORD - 1 */
309*5113495bSYour Name uint32_t mac_addr_a_47_32 : 16,
310*5113495bSYour Name mac_addr_b_15_0 : 16;
311*5113495bSYour Name /* DWORD - 2 */
312*5113495bSYour Name uint32_t mac_addr_b_47_16 : 32;
313*5113495bSYour Name /* DWORD - 3 */
314*5113495bSYour Name uint32_t reserved_3 : 32;
315*5113495bSYour Name /* DWORD - 16 */
316*5113495bSYour Name uint32_t reserved_16 : 32;
317*5113495bSYour Name /* DWORD - 17 */
318*5113495bSYour Name uint32_t multi_link_addr_crypto_enable : 1,
319*5113495bSYour Name reserved_17_a : 15,
320*5113495bSYour Name sw_peer_id : 16;
321*5113495bSYour Name };
322*5113495bSYour Name
323*5113495bSYour Name #define TX_QUEUE_EXT_MASK 0x1
324*5113495bSYour Name typedef struct tx_queue_ext_compact_6432 hal_tx_queue_ext_t;
325*5113495bSYour Name struct tx_queue_ext_compact_6432 {
326*5113495bSYour Name /* DWORD - 0 */
327*5113495bSYour Name uint32_t frame_ctl : 16,
328*5113495bSYour Name qos_ctl : 16;
329*5113495bSYour Name /* DWORD - 1 */
330*5113495bSYour Name uint32_t ampdu_flag : 1,
331*5113495bSYour Name reserved_1 : 31;
332*5113495bSYour Name };
333*5113495bSYour Name
334*5113495bSYour Name #define TX_MSDU_START_MASK 0x1
335*5113495bSYour Name typedef struct tx_msdu_start_compact_6432 hal_tx_msdu_start_t;
336*5113495bSYour Name struct tx_msdu_start_compact_6432 {
337*5113495bSYour Name /* DWORD - 0 */
338*5113495bSYour Name uint32_t reserved_0 : 32;
339*5113495bSYour Name /* DWORD - 1 */
340*5113495bSYour Name uint32_t reserved_1 : 32;
341*5113495bSYour Name };
342*5113495bSYour Name
343*5113495bSYour Name #define TX_MPDU_START_MASK 0x3
344*5113495bSYour Name typedef struct tx_mpdu_start_compact_6432 hal_tx_mpdu_start_t;
345*5113495bSYour Name struct tx_mpdu_start_compact_6432 {
346*5113495bSYour Name /* DWORD - 0 */
347*5113495bSYour Name uint32_t mpdu_length : 14,
348*5113495bSYour Name frame_not_from_tqm : 1,
349*5113495bSYour Name vht_control_present : 1,
350*5113495bSYour Name mpdu_header_length : 8,
351*5113495bSYour Name retry_count : 7,
352*5113495bSYour Name wds : 1;
353*5113495bSYour Name /* DWORD - 1 */
354*5113495bSYour Name uint32_t pn_31_0 : 32;
355*5113495bSYour Name /* DWORD - 2 */
356*5113495bSYour Name uint32_t pn_47_32 : 16,
357*5113495bSYour Name mpdu_sequence_number : 12,
358*5113495bSYour Name raw_already_encrypted : 1,
359*5113495bSYour Name frame_type : 2,
360*5113495bSYour Name txdma_dropped_mpdu_warning : 1;
361*5113495bSYour Name /* DWORD - 3 */
362*5113495bSYour Name uint32_t reserved_3 : 32;
363*5113495bSYour Name };
364*5113495bSYour Name
365*5113495bSYour Name typedef struct rxpcu_user_setup_compact_6432 hal_rxpcu_user_setup_t;
366*5113495bSYour Name struct rxpcu_user_setup_compact_6432 {
367*5113495bSYour Name };
368*5113495bSYour Name
369*5113495bSYour Name #define TX_FES_STATUS_END_MASK 0x7
370*5113495bSYour Name typedef struct tx_fes_status_end_compact_6432 hal_tx_fes_status_end_t;
371*5113495bSYour Name struct tx_fes_status_end_compact_6432 {
372*5113495bSYour Name /* DWORD - 0 */
373*5113495bSYour Name uint32_t reserved_0 : 32;
374*5113495bSYour Name /* DWORD - 1 */
375*5113495bSYour Name struct {
376*5113495bSYour Name uint16_t phytx_abort_reason : 8,
377*5113495bSYour Name user_number : 6,
378*5113495bSYour Name reserved_1a : 2;
379*5113495bSYour Name } phytx_abort_request_info_details;
380*5113495bSYour Name uint16_t reserved_1b : 12,
381*5113495bSYour Name phytx_abort_request_info_valid : 1,
382*5113495bSYour Name reserved_1c : 3;
383*5113495bSYour Name /* DWORD - 2 */
384*5113495bSYour Name uint32_t start_of_frame_timestamp_15_0 : 16,
385*5113495bSYour Name start_of_frame_timestamp_31_16 : 16;
386*5113495bSYour Name /* DWORD - 3 */
387*5113495bSYour Name uint32_t end_of_frame_timestamp_15_0 : 16,
388*5113495bSYour Name end_of_frame_timestamp_31_16 : 16;
389*5113495bSYour Name /* DWORD - 4 */
390*5113495bSYour Name uint32_t terminate_ranging_sequence : 1,
391*5113495bSYour Name reserved_4a : 7,
392*5113495bSYour Name timing_status : 2,
393*5113495bSYour Name response_type : 5,
394*5113495bSYour Name r2r_end_status_to_follow : 1,
395*5113495bSYour Name transmit_delay : 16;
396*5113495bSYour Name /* DWORD - 5 */
397*5113495bSYour Name uint32_t reserved_5 : 32;
398*5113495bSYour Name };
399*5113495bSYour Name
400*5113495bSYour Name #define RESPONSE_END_STATUS_MASK 0xD
401*5113495bSYour Name typedef struct response_end_status_compact_6432 hal_response_end_status_t;
402*5113495bSYour Name struct response_end_status_compact_6432 {
403*5113495bSYour Name /* DWORD - 0 */
404*5113495bSYour Name uint32_t coex_bt_tx_while_wlan_tx : 1,
405*5113495bSYour Name coex_wan_tx_while_wlan_tx : 1,
406*5113495bSYour Name coex_wlan_tx_while_wlan_tx : 1,
407*5113495bSYour Name global_data_underflow_warning : 1,
408*5113495bSYour Name response_transmit_status : 4,
409*5113495bSYour Name phytx_pkt_end_info_valid : 1,
410*5113495bSYour Name phytx_abort_request_info_valid : 1,
411*5113495bSYour Name generated_response : 3,
412*5113495bSYour Name mba_user_count : 7,
413*5113495bSYour Name mba_fake_bitmap_count : 7,
414*5113495bSYour Name coex_based_tx_bw : 3,
415*5113495bSYour Name trig_response_related : 1,
416*5113495bSYour Name dpdtrain_done : 1;
417*5113495bSYour Name /* DWORD - 1 */
418*5113495bSYour Name uint32_t reserved_1 : 32;
419*5113495bSYour Name /* DWORD - 4 */
420*5113495bSYour Name uint32_t reserved_4 : 32;
421*5113495bSYour Name /* DWORD - 5 */
422*5113495bSYour Name uint32_t start_of_frame_timestamp_15_0 : 16,
423*5113495bSYour Name start_of_frame_timestamp_31_16 : 16;
424*5113495bSYour Name /* DWORD - 6 */
425*5113495bSYour Name uint32_t end_of_frame_timestamp_15_0 : 16,
426*5113495bSYour Name end_of_frame_timestamp_31_16 : 16;
427*5113495bSYour Name /* DWORD - 7 */
428*5113495bSYour Name uint32_t reserved_7 : 32;
429*5113495bSYour Name };
430*5113495bSYour Name
431*5113495bSYour Name #define TX_FES_STATUS_PROT_MASK 0x2
432*5113495bSYour Name typedef struct tx_fes_status_prot_compact_6432 hal_tx_fes_status_prot_t;
433*5113495bSYour Name struct tx_fes_status_prot_compact_6432 {
434*5113495bSYour Name /* DWORD - 2 */
435*5113495bSYour Name uint32_t start_of_frame_timestamp_15_0 : 16,
436*5113495bSYour Name start_of_frame_timestamp_31_16 : 16;
437*5113495bSYour Name /* DWROD - 3 */
438*5113495bSYour Name uint32_t end_of_frame_timestamp_15_0 : 16,
439*5113495bSYour Name end_of_frame_timestamp_31_16 : 16;
440*5113495bSYour Name };
441*5113495bSYour Name
442*5113495bSYour Name #define PCU_PPDU_SETUP_INIT_MASK 0x1E800000
443*5113495bSYour Name typedef struct pcu_ppdu_setup_init_compact_6432 hal_pcu_ppdu_setup_t;
444*5113495bSYour Name struct pcu_ppdu_setup_init_compact_6432 {
445*5113495bSYour Name /* DWORD - 46 */
446*5113495bSYour Name uint32_t reserved_46 : 32;
447*5113495bSYour Name /* DWORD - 47 */
448*5113495bSYour Name uint32_t r2r_group_id : 6,
449*5113495bSYour Name r2r_response_frame_type : 4,
450*5113495bSYour Name r2r_sta_partial_aid : 11,
451*5113495bSYour Name use_address_fields_for_protection : 1,
452*5113495bSYour Name r2r_set_required_response_time : 1,
453*5113495bSYour Name reserved_47 : 9;
454*5113495bSYour Name /* DWORD - 50 */
455*5113495bSYour Name uint32_t reserved_50 : 32;
456*5113495bSYour Name /* DWORD - 51 */
457*5113495bSYour Name uint32_t protection_frame_ad1_31_0 : 32;
458*5113495bSYour Name /* DWORD - 52 */
459*5113495bSYour Name uint32_t protection_frame_ad1_47_32 : 16,
460*5113495bSYour Name protection_frame_ad2_15_0 : 16;
461*5113495bSYour Name /* DWORD - 53 */
462*5113495bSYour Name uint32_t protection_frame_ad2_47_16 : 32;
463*5113495bSYour Name /* DWORD - 54 */
464*5113495bSYour Name uint32_t reserved_54 : 32;
465*5113495bSYour Name /* DWORD - 55 */
466*5113495bSYour Name uint32_t protection_frame_ad3_31_0 : 32;
467*5113495bSYour Name /* DWORD - 56 */
468*5113495bSYour Name uint32_t protection_frame_ad3_47_32 : 16,
469*5113495bSYour Name protection_frame_ad4_15_0 : 16;
470*5113495bSYour Name /* DWORD - 57 */
471*5113495bSYour Name uint32_t protection_frame_ad4_47_16 : 32;
472*5113495bSYour Name };
473*5113495bSYour Name
474*5113495bSYour Name /**
475*5113495bSYour Name * hal_txmon_get_word_mask_qcn6432() - api to get word mask for tx monitor
476*5113495bSYour Name * @wmask: pointer to hal_txmon_word_mask_config_t
477*5113495bSYour Name *
478*5113495bSYour Name * Return: void
479*5113495bSYour Name */
480*5113495bSYour Name static inline
hal_txmon_get_word_mask_qcn6432(void * wmask)481*5113495bSYour Name void hal_txmon_get_word_mask_qcn6432(void *wmask)
482*5113495bSYour Name {
483*5113495bSYour Name hal_txmon_word_mask_config_t *word_mask = NULL;
484*5113495bSYour Name
485*5113495bSYour Name word_mask = (hal_txmon_word_mask_config_t *)wmask;
486*5113495bSYour Name
487*5113495bSYour Name word_mask->compaction_enable = 1;
488*5113495bSYour Name word_mask->tx_fes_setup = TX_FES_SETUP_MASK;
489*5113495bSYour Name word_mask->tx_peer_entry = TX_PEER_ENTRY_MASK;
490*5113495bSYour Name word_mask->tx_queue_ext = TX_QUEUE_EXT_MASK;
491*5113495bSYour Name word_mask->tx_msdu_start = TX_MSDU_START_MASK;
492*5113495bSYour Name word_mask->pcu_ppdu_setup_init = PCU_PPDU_SETUP_INIT_MASK;
493*5113495bSYour Name word_mask->tx_mpdu_start = TX_MPDU_START_MASK;
494*5113495bSYour Name word_mask->rxpcu_user_setup = 0xFF;
495*5113495bSYour Name word_mask->tx_fes_status_end = TX_FES_STATUS_END_MASK;
496*5113495bSYour Name word_mask->response_end_status = RESPONSE_END_STATUS_MASK;
497*5113495bSYour Name word_mask->tx_fes_status_prot = TX_FES_STATUS_PROT_MASK;
498*5113495bSYour Name }
499*5113495bSYour Name #endif
500*5113495bSYour Name
501*5113495bSYour Name /**
502*5113495bSYour Name * hal_tx_set_ppe_cmn_config_6432() - Set the PPE common config register
503*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
504*5113495bSYour Name * @cmn_cfg: Common PPE config
505*5113495bSYour Name *
506*5113495bSYour Name * Based on the PPE2TCL descriptor below errors, if the below register
507*5113495bSYour Name * values are set then the packets are forward to Tx rule handler if 1'0b
508*5113495bSYour Name * or to TCL exit base if 1'1b.
509*5113495bSYour Name *
510*5113495bSYour Name * Return: void
511*5113495bSYour Name */
512*5113495bSYour Name static inline
hal_tx_set_ppe_cmn_config_6432(hal_soc_handle_t hal_soc_hdl,union hal_tx_cmn_config_ppe * cmn_cfg)513*5113495bSYour Name void hal_tx_set_ppe_cmn_config_6432(hal_soc_handle_t hal_soc_hdl,
514*5113495bSYour Name union hal_tx_cmn_config_ppe *cmn_cfg)
515*5113495bSYour Name {
516*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
517*5113495bSYour Name union hal_tx_cmn_config_ppe *cfg =
518*5113495bSYour Name (union hal_tx_cmn_config_ppe *)cmn_cfg;
519*5113495bSYour Name uint32_t reg_addr, reg_val = 0;
520*5113495bSYour Name
521*5113495bSYour Name reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE);
522*5113495bSYour Name
523*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
524*5113495bSYour Name
525*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;
526*5113495bSYour Name reg_val |=
527*5113495bSYour Name (cfg->drop_prec_err &
528*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) <<
529*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT;
530*5113495bSYour Name
531*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;
532*5113495bSYour Name reg_val |=
533*5113495bSYour Name (cfg->fake_mac_hdr &
534*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) <<
535*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT;
536*5113495bSYour Name
537*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;
538*5113495bSYour Name reg_val |=
539*5113495bSYour Name (cfg->cpu_code_inv &
540*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) <<
541*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT;
542*5113495bSYour Name
543*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;
544*5113495bSYour Name reg_val |=
545*5113495bSYour Name (cfg->l3_l4_err &
546*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) <<
547*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT;
548*5113495bSYour Name
549*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
550*5113495bSYour Name }
551*5113495bSYour Name
552*5113495bSYour Name /**
553*5113495bSYour Name * hal_tx_set_ppe_vp_entry_6432() - Set the PPE VP entry
554*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
555*5113495bSYour Name * @cfg: PPE VP config
556*5113495bSYour Name * @ppe_vp_idx: PPE VP index to the table
557*5113495bSYour Name *
558*5113495bSYour Name * Return: void
559*5113495bSYour Name */
560*5113495bSYour Name static inline
hal_tx_set_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl,union hal_tx_ppe_vp_config * cfg,int ppe_vp_idx)561*5113495bSYour Name void hal_tx_set_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl,
562*5113495bSYour Name union hal_tx_ppe_vp_config *cfg,
563*5113495bSYour Name int ppe_vp_idx)
564*5113495bSYour Name {
565*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
566*5113495bSYour Name uint32_t reg_addr;
567*5113495bSYour Name
568*5113495bSYour Name reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
569*5113495bSYour Name ppe_vp_idx);
570*5113495bSYour Name
571*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, cfg->val);
572*5113495bSYour Name }
573*5113495bSYour Name
574*5113495bSYour Name /**
575*5113495bSYour Name * hal_ppeds_cfg_ast_override_map_reg_6432() - Set the PPE index mapping table
576*5113495bSYour Name * @hal_soc_hdl: HAL SoC context
577*5113495bSYour Name * @idx: index into the table
578*5113495bSYour Name * @idx_map: HAL PPE INDESX MAPPING config
579*5113495bSYour Name *
580*5113495bSYour Name * Return: void
581*5113495bSYour Name */
582*5113495bSYour Name static inline void
hal_ppeds_cfg_ast_override_map_reg_6432(hal_soc_handle_t hal_soc_hdl,uint8_t idx,union hal_tx_ppe_idx_map_config * idx_map)583*5113495bSYour Name hal_ppeds_cfg_ast_override_map_reg_6432(hal_soc_handle_t hal_soc_hdl,
584*5113495bSYour Name uint8_t idx,
585*5113495bSYour Name union hal_tx_ppe_idx_map_config *idx_map)
586*5113495bSYour Name {
587*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
588*5113495bSYour Name uint32_t reg_addr;
589*5113495bSYour Name
590*5113495bSYour Name reg_addr =
591*5113495bSYour Name HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
592*5113495bSYour Name idx);
593*5113495bSYour Name
594*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, idx_map->val);
595*5113495bSYour Name }
596*5113495bSYour Name
597*5113495bSYour Name /**
598*5113495bSYour Name * hal_tx_set_ppe_pri2tid_map_6432()
599*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
600*5113495bSYour Name * @val : PRI to TID value
601*5113495bSYour Name * @map_no: Map number
602*5113495bSYour Name *
603*5113495bSYour Name * Return: void
604*5113495bSYour Name */
605*5113495bSYour Name static inline
hal_tx_set_ppe_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,uint32_t val,uint8_t map_no)606*5113495bSYour Name void hal_tx_set_ppe_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,
607*5113495bSYour Name uint32_t val, uint8_t map_no)
608*5113495bSYour Name {
609*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
610*5113495bSYour Name uint32_t reg_addr, reg_val = 0;
611*5113495bSYour Name
612*5113495bSYour Name if (map_no == 0)
613*5113495bSYour Name reg_addr =
614*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
615*5113495bSYour Name else
616*5113495bSYour Name reg_addr =
617*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
618*5113495bSYour Name
619*5113495bSYour Name reg_val |= val;
620*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
621*5113495bSYour Name }
622*5113495bSYour Name
623*5113495bSYour Name /**
624*5113495bSYour Name * hal_tx_enable_pri2tid_map_6432()
625*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
626*5113495bSYour Name * @val : PRI to TID value
627*5113495bSYour Name * @ppe_vp_idx: Map number
628*5113495bSYour Name *
629*5113495bSYour Name * Return: void
630*5113495bSYour Name */
631*5113495bSYour Name
632*5113495bSYour Name static inline
hal_tx_enable_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,bool val,uint8_t ppe_vp_idx)633*5113495bSYour Name void hal_tx_enable_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,
634*5113495bSYour Name bool val, uint8_t ppe_vp_idx)
635*5113495bSYour Name {
636*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
637*5113495bSYour Name uint32_t reg_addr, reg_val = 0;
638*5113495bSYour Name
639*5113495bSYour Name reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
640*5113495bSYour Name ppe_vp_idx);
641*5113495bSYour Name
642*5113495bSYour Name /*
643*5113495bSYour Name * Drop precedence is enabled by default.
644*5113495bSYour Name */
645*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
646*5113495bSYour Name
647*5113495bSYour Name reg_val &=
648*5113495bSYour Name ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
649*5113495bSYour Name
650*5113495bSYour Name reg_val |=
651*5113495bSYour Name (val &
652*5113495bSYour Name HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
653*5113495bSYour Name HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
654*5113495bSYour Name
655*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
656*5113495bSYour Name }
657*5113495bSYour Name
658*5113495bSYour Name /**
659*5113495bSYour Name * hal_tx_update_ppe_pri2tid_6432()
660*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
661*5113495bSYour Name * @pri: INT_PRI
662*5113495bSYour Name * @tid: Wi-Fi TID
663*5113495bSYour Name *
664*5113495bSYour Name * Return: void
665*5113495bSYour Name */
666*5113495bSYour Name
667*5113495bSYour Name static inline
hal_tx_update_ppe_pri2tid_6432(hal_soc_handle_t hal_soc_hdl,uint8_t pri,uint8_t tid)668*5113495bSYour Name void hal_tx_update_ppe_pri2tid_6432(hal_soc_handle_t hal_soc_hdl,
669*5113495bSYour Name uint8_t pri, uint8_t tid)
670*5113495bSYour Name {
671*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
672*5113495bSYour Name uint32_t reg_addr, reg_val = 0, mask, shift;
673*5113495bSYour Name
674*5113495bSYour Name /*
675*5113495bSYour Name * INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15
676*5113495bSYour Name * is in MAP1 register.
677*5113495bSYour Name */
678*5113495bSYour Name switch (pri) {
679*5113495bSYour Name case 0 ... 9:
680*5113495bSYour Name reg_addr =
681*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
682*5113495bSYour Name mask =
683*5113495bSYour Name (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri));
684*5113495bSYour Name shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3);
685*5113495bSYour Name break;
686*5113495bSYour Name case 10 ... 15:
687*5113495bSYour Name pri = pri - 10;
688*5113495bSYour Name reg_addr =
689*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
690*5113495bSYour Name mask =
691*5113495bSYour Name (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri));
692*5113495bSYour Name shift =
693*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3);
694*5113495bSYour Name break;
695*5113495bSYour Name default:
696*5113495bSYour Name return;
697*5113495bSYour Name }
698*5113495bSYour Name
699*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
700*5113495bSYour Name reg_val &= ~mask;
701*5113495bSYour Name reg_val |= (pri << shift) & mask;
702*5113495bSYour Name
703*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
704*5113495bSYour Name }
705*5113495bSYour Name
706*5113495bSYour Name /*
707*5113495bSYour Name * hal_tx_dump_ppe_vp_entry_6432()
708*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
709*5113495bSYour Name *
710*5113495bSYour Name * Return: void
711*5113495bSYour Name */
712*5113495bSYour Name static inline
hal_tx_dump_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl)713*5113495bSYour Name void hal_tx_dump_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl)
714*5113495bSYour Name {
715*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
716*5113495bSYour Name uint32_t reg_addr, reg_val = 0, i;
717*5113495bSYour Name
718*5113495bSYour Name for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) {
719*5113495bSYour Name reg_addr =
720*5113495bSYour Name HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(
721*5113495bSYour Name MAC_TCL_REG_REG_BASE,
722*5113495bSYour Name i);
723*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
724*5113495bSYour Name hal_verbose_debug("%d: 0x%x\n", i, reg_val);
725*5113495bSYour Name }
726*5113495bSYour Name }
727*5113495bSYour Name
728*5113495bSYour Name /*
729*5113495bSYour Name * hal_tx_get_num_ppe_vp_tbl_entries_6432()
730*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
731*5113495bSYour Name *
732*5113495bSYour Name * Return: Number of PPE VP entries
733*5113495bSYour Name */
734*5113495bSYour Name static
hal_tx_get_num_ppe_vp_tbl_entries_6432(hal_soc_handle_t hal_soc_hdl)735*5113495bSYour Name uint32_t hal_tx_get_num_ppe_vp_tbl_entries_6432(hal_soc_handle_t hal_soc_hdl)
736*5113495bSYour Name {
737*5113495bSYour Name return HAL_PPE_VP_ENTRIES_MAX;
738*5113495bSYour Name }
739*5113495bSYour Name
740*5113495bSYour Name /**
741*5113495bSYour Name * hal_tx_ppe2tcl_ring_halt_set_6432() - Enable ring halt for the ppe2tcl ring
742*5113495bSYour Name * @hal_soc: HAL SoC context
743*5113495bSYour Name *
744*5113495bSYour Name * Return: none
745*5113495bSYour Name */
hal_tx_ppe2tcl_ring_halt_set_6432(hal_soc_handle_t hal_soc)746*5113495bSYour Name static void hal_tx_ppe2tcl_ring_halt_set_6432(hal_soc_handle_t hal_soc)
747*5113495bSYour Name {
748*5113495bSYour Name uint32_t cmn_reg_addr;
749*5113495bSYour Name uint32_t regval;
750*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
751*5113495bSYour Name
752*5113495bSYour Name cmn_reg_addr =
753*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
754*5113495bSYour Name
755*5113495bSYour Name /* Enable RING_HALT */
756*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
757*5113495bSYour Name regval |=
758*5113495bSYour Name (1 <<
759*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
760*5113495bSYour Name
761*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
762*5113495bSYour Name }
763*5113495bSYour Name
764*5113495bSYour Name /**
765*5113495bSYour Name * hal_tx_ppe2tcl_ring_halt_reset_6432() - Disable ring halt for the ppe2tcl ring
766*5113495bSYour Name * @hal_soc: HAL SoC context
767*5113495bSYour Name *
768*5113495bSYour Name * Return: none
769*5113495bSYour Name */
hal_tx_ppe2tcl_ring_halt_reset_6432(hal_soc_handle_t hal_soc)770*5113495bSYour Name static void hal_tx_ppe2tcl_ring_halt_reset_6432(hal_soc_handle_t hal_soc)
771*5113495bSYour Name {
772*5113495bSYour Name uint32_t cmn_reg_addr;
773*5113495bSYour Name uint32_t regval;
774*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
775*5113495bSYour Name
776*5113495bSYour Name cmn_reg_addr =
777*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
778*5113495bSYour Name
779*5113495bSYour Name /* Disable RING_HALT */
780*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
781*5113495bSYour Name regval &= ~(1 <<
782*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
783*5113495bSYour Name
784*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
785*5113495bSYour Name }
786*5113495bSYour Name
787*5113495bSYour Name /**
788*5113495bSYour Name * hal_tx_ppe2tcl_ring_halt_done_6432() - Check if ring halt is done for ppe2tcl ring
789*5113495bSYour Name * @hal_soc: HAL SoC context
790*5113495bSYour Name *
791*5113495bSYour Name * Return: true if halt done
792*5113495bSYour Name */
hal_tx_ppe2tcl_ring_halt_done_6432(hal_soc_handle_t hal_soc)793*5113495bSYour Name static bool hal_tx_ppe2tcl_ring_halt_done_6432(hal_soc_handle_t hal_soc)
794*5113495bSYour Name {
795*5113495bSYour Name uint32_t cmn_reg_addr;
796*5113495bSYour Name uint32_t regval;
797*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
798*5113495bSYour Name
799*5113495bSYour Name cmn_reg_addr =
800*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
801*5113495bSYour Name
802*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
803*5113495bSYour Name regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT);
804*5113495bSYour Name
805*5113495bSYour Name return(!!regval);
806*5113495bSYour Name }
807*5113495bSYour Name
808*5113495bSYour Name #endif /* _HAL_6432_TX_H_ */
809