xref: /wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qcn9000/hal_9000_tx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 #include "hal_hw_headers.h"
20 #include "hal_internal.h"
21 #include "cdp_txrx_mon_struct.h"
22 #include "qdf_trace.h"
23 #include "hal_rx.h"
24 #include "hal_tx.h"
25 #include "dp_types.h"
26 #include "hal_api_mon.h"
27 
28 /**
29  * hal_tx_desc_set_dscp_tid_table_id_9000() - Sets DSCP to TID conversion table
30  *                                            ID
31  * @desc: Handle to Tx Descriptor
32  * @id: DSCP to tid conversion table to be used for this frame
33  *
34  * Return: void
35  */
hal_tx_desc_set_dscp_tid_table_id_9000(void * desc,uint8_t id)36 static void hal_tx_desc_set_dscp_tid_table_id_9000(void *desc, uint8_t id)
37 {
38 	HAL_SET_FLD(desc, TCL_DATA_CMD_5,
39 		    DSCP_TID_TABLE_NUM) |=
40 		    HAL_TX_SM(TCL_DATA_CMD_5, DSCP_TID_TABLE_NUM, id);
41 }
42 
43 #define DSCP_TID_TABLE_SIZE 24
44 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
45 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
46 
47 /**
48  * hal_tx_set_dscp_tid_map_9000() - Configure default DSCP to TID map table
49  * @soc: HAL SoC context
50  * @map: DSCP-TID mapping table
51  * @id: mapping table ID - 0,1
52  *
53  * DSCP are mapped to 8 TID values using TID values programmed
54  * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0)
55  * and DSCP_TID2_MAP_<0 to 6> (id = 1)
56  * Each mapping register has TID mapping for 10 DSCP values
57  *
58  * Return: none
59  */
hal_tx_set_dscp_tid_map_9000(struct hal_soc * soc,uint8_t * map,uint8_t id)60 static void hal_tx_set_dscp_tid_map_9000(struct hal_soc *soc,
61 					 uint8_t *map, uint8_t id)
62 {
63 	int i;
64 	uint32_t addr, cmn_reg_addr;
65 	uint32_t value = 0, regval;
66 	uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
67 
68 	if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS)
69 		return;
70 
71 	cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
72 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
73 
74 	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
75 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
76 				id * NUM_WORDS_PER_DSCP_TID_TABLE);
77 
78 	/* Enable read/write access */
79 	regval = HAL_REG_READ(soc, cmn_reg_addr);
80 	regval |=
81 	(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
82 
83 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
84 
85 	/* Write 8 (24 bits) DSCP-TID mappings in each iteration */
86 	for (i = 0; i < 64; i += 8) {
87 		value = (map[i] |
88 			(map[i + 1] << 0x3) |
89 			(map[i + 2] << 0x6) |
90 			(map[i + 3] << 0x9) |
91 			(map[i + 4] << 0xc) |
92 			(map[i + 5] << 0xf) |
93 			(map[i + 6] << 0x12) |
94 			(map[i + 7] << 0x15));
95 
96 		qdf_mem_copy(&val[cnt], &value, 3);
97 		cnt += 3;
98 	}
99 
100 	for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
101 		regval = *(uint32_t *)(val + i);
102 		HAL_REG_WRITE(soc, addr,
103 			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
104 		addr += 4;
105 	}
106 
107 	/* Disable read/write access */
108 	regval = HAL_REG_READ(soc, cmn_reg_addr);
109 	regval &=
110 	~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
111 
112 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
113 }
114 
115 /**
116  * hal_tx_update_dscp_tid_9000() - Update the dscp tid map table as updated by
117  *                                 user
118  * @soc: HAL SoC context
119  * @tid: TID
120  * @id: MAP ID
121  * @dscp: DSCP
122  *
123  * Return: void
124  */
hal_tx_update_dscp_tid_9000(struct hal_soc * soc,uint8_t tid,uint8_t id,uint8_t dscp)125 static void hal_tx_update_dscp_tid_9000(struct hal_soc *soc, uint8_t tid,
126 					uint8_t id, uint8_t dscp)
127 {
128 	uint32_t addr, addr1, cmn_reg_addr;
129 	uint32_t start_value = 0, end_value = 0;
130 	uint32_t regval;
131 	uint8_t end_bits = 0;
132 	uint8_t start_bits = 0;
133 	uint32_t start_index, end_index;
134 
135 	cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
136 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
137 
138 	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
139 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
140 				id * NUM_WORDS_PER_DSCP_TID_TABLE);
141 
142 	start_index = dscp * HAL_TX_BITS_PER_TID;
143 	end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
144 		    % HAL_TX_NUM_DSCP_REGISTER_SIZE;
145 	start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
146 	addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
147 			HAL_TX_NUM_DSCP_REGISTER_SIZE));
148 
149 	if (end_index < start_index) {
150 		end_bits = end_index + 1;
151 		start_bits = HAL_TX_BITS_PER_TID - end_bits;
152 		start_value = tid << start_index;
153 		end_value = tid >> start_bits;
154 		addr1 = addr + 4;
155 	} else {
156 		start_bits = HAL_TX_BITS_PER_TID - end_bits;
157 		start_value = tid << start_index;
158 		addr1 = 0;
159 	}
160 
161 	/* Enable read/write access */
162 	regval = HAL_REG_READ(soc, cmn_reg_addr);
163 	regval |=
164 	(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
165 
166 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
167 
168 	regval = HAL_REG_READ(soc, addr);
169 
170 	if (end_index < start_index)
171 		regval &= (~0) >> start_bits;
172 	else
173 		regval &= ~(7 << start_index);
174 
175 	regval |= start_value;
176 
177 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
178 
179 	if (addr1) {
180 		regval = HAL_REG_READ(soc, addr1);
181 		regval &= (~0) << end_bits;
182 		regval |= end_value;
183 
184 		HAL_REG_WRITE(soc, addr1, (regval &
185 			     HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
186 	}
187 
188 	/* Disable read/write access */
189 	regval = HAL_REG_READ(soc, cmn_reg_addr);
190 	regval &=
191 	~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
192 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
193 }
194 
195 /**
196  * hal_tx_desc_set_lmac_id_9000() - Set the lmac_id value
197  * @desc: Handle to Tx Descriptor
198  * @lmac_id: mac Id to ast matching
199  *		     b00 – mac 0
200  *		     b01 – mac 1
201  *		     b10 – mac 2
202  *		     b11 – all macs (legacy HK way)
203  *
204  * Return: void
205  */
hal_tx_desc_set_lmac_id_9000(void * desc,uint8_t lmac_id)206 static void hal_tx_desc_set_lmac_id_9000(void *desc, uint8_t lmac_id)
207 {
208 	HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
209 		HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
210 }
211 
212 /**
213  * hal_tx_init_cmd_credit_ring_9000() - Initialize TCL command/credit SRNG
214  * @hal_soc_hdl: Handle to HAL SoC structure
215  * @hal_ring_hdl: Handle to HAL SRNG structure
216  *
217  * Return: none
218  */
hal_tx_init_cmd_credit_ring_9000(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)219 static inline void hal_tx_init_cmd_credit_ring_9000(hal_soc_handle_t hal_soc_hdl,
220 						    hal_ring_handle_t hal_ring_hdl)
221 {
222 	uint8_t *desc_addr;
223 	struct hal_srng_params srng_params;
224 	uint32_t desc_size;
225 	uint32_t num_desc;
226 
227 	hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
228 
229 	desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
230 	desc_size = sizeof(struct tcl_data_cmd);
231 	num_desc = srng_params.num_entries;
232 
233 	while (num_desc) {
234 		/* using CMD/CREDIT Ring to send DATA CMD tag */
235 		HAL_TX_DESC_SET_TLV_HDR(desc_addr, WIFITCL_DATA_CMD_E,
236 					desc_size);
237 		desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
238 		num_desc--;
239 	}
240 }
241