1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for
6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the
7*5113495bSYour Name * above copyright notice and this permission notice appear in all
8*5113495bSYour Name * copies.
9*5113495bSYour Name *
10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE.
18*5113495bSYour Name */
19*5113495bSYour Name #include "qdf_types.h"
20*5113495bSYour Name #include "qdf_util.h"
21*5113495bSYour Name #include "qdf_mem.h"
22*5113495bSYour Name #include "qdf_nbuf.h"
23*5113495bSYour Name #include "qdf_module.h"
24*5113495bSYour Name
25*5113495bSYour Name #include "target_type.h"
26*5113495bSYour Name #include "wcss_version.h"
27*5113495bSYour Name
28*5113495bSYour Name #include "hal_be_hw_headers.h"
29*5113495bSYour Name #include "hal_internal.h"
30*5113495bSYour Name #include "hal_api.h"
31*5113495bSYour Name #include "hal_flow.h"
32*5113495bSYour Name #include "rx_flow_search_entry.h"
33*5113495bSYour Name #include "hal_rx_flow_info.h"
34*5113495bSYour Name #include "hal_be_api.h"
35*5113495bSYour Name #include "tcl_entrance_from_ppe_ring.h"
36*5113495bSYour Name #include "sw_monitor_ring.h"
37*5113495bSYour Name #include "wcss_seq_hwioreg_umac.h"
38*5113495bSYour Name #include "wfss_ce_reg_seq_hwioreg.h"
39*5113495bSYour Name #include <uniform_reo_status_header.h>
40*5113495bSYour Name #include <wbm_release_ring_tx.h>
41*5113495bSYour Name #include <phyrx_location.h>
42*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \
43*5113495bSYour Name defined(WLAN_PKT_CAPTURE_RX_2_0)
44*5113495bSYour Name #include <mon_ingress_ring.h>
45*5113495bSYour Name #include <mon_destination_ring.h>
46*5113495bSYour Name #endif
47*5113495bSYour Name #include "rx_reo_queue_1k.h"
48*5113495bSYour Name
49*5113495bSYour Name #include <hal_be_rx.h>
50*5113495bSYour Name
51*5113495bSYour Name #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
52*5113495bSYour Name RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
53*5113495bSYour Name #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
54*5113495bSYour Name RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
55*5113495bSYour Name #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
56*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
57*5113495bSYour Name #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
58*5113495bSYour Name RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
59*5113495bSYour Name #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
60*5113495bSYour Name REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
61*5113495bSYour Name #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
62*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER
63*5113495bSYour Name #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
64*5113495bSYour Name STATUS_HEADER_TIMESTAMP
65*5113495bSYour Name #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
66*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
67*5113495bSYour Name #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
68*5113495bSYour Name RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
69*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
70*5113495bSYour Name TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
71*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
72*5113495bSYour Name TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
73*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
74*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
75*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
76*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
77*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
78*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
79*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
80*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
81*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
82*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
83*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
84*5113495bSYour Name BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
85*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
86*5113495bSYour Name BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
87*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
88*5113495bSYour Name BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
89*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
90*5113495bSYour Name BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
91*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
92*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
93*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
94*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
95*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
96*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
97*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
98*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
99*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
100*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
101*5113495bSYour Name
102*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0)
103*5113495bSYour Name #include "hal_be_api_mon.h"
104*5113495bSYour Name #endif
105*5113495bSYour Name
106*5113495bSYour Name #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
107*5113495bSYour Name #define CMEM_REG_BASE 0x0010e000
108*5113495bSYour Name
109*5113495bSYour Name #define CMEM_WINDOW_ADDRESS_9224 \
110*5113495bSYour Name ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
111*5113495bSYour Name #endif
112*5113495bSYour Name
113*5113495bSYour Name #define CE_WINDOW_ADDRESS_9224 \
114*5113495bSYour Name ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
115*5113495bSYour Name
116*5113495bSYour Name #define UMAC_WINDOW_ADDRESS_9224 \
117*5113495bSYour Name ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
118*5113495bSYour Name
119*5113495bSYour Name #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
120*5113495bSYour Name #define WINDOW_CONFIGURATION_VALUE_9224 \
121*5113495bSYour Name ((CE_WINDOW_ADDRESS_9224 << 6) |\
122*5113495bSYour Name (UMAC_WINDOW_ADDRESS_9224 << 12) | \
123*5113495bSYour Name CMEM_WINDOW_ADDRESS_9224 | \
124*5113495bSYour Name WINDOW_ENABLE_BIT)
125*5113495bSYour Name #else
126*5113495bSYour Name #define WINDOW_CONFIGURATION_VALUE_9224 \
127*5113495bSYour Name ((CE_WINDOW_ADDRESS_9224 << 6) |\
128*5113495bSYour Name (UMAC_WINDOW_ADDRESS_9224 << 12) | \
129*5113495bSYour Name WINDOW_ENABLE_BIT)
130*5113495bSYour Name #endif
131*5113495bSYour Name
132*5113495bSYour Name /* For Berryllium sw2rxdma ring size increased to 20 bits */
133*5113495bSYour Name #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
134*5113495bSYour Name
135*5113495bSYour Name #include "hal_9224_rx.h"
136*5113495bSYour Name #include "hal_9224_tx.h"
137*5113495bSYour Name #include "hal_be_rx_tlv.h"
138*5113495bSYour Name #include <hal_be_generic_api.h>
139*5113495bSYour Name
140*5113495bSYour Name enum hal_all_sigb_pkt_type {
141*5113495bSYour Name HAL_SIGB_RX_PKT_TYPE_11A = 0,
142*5113495bSYour Name HAL_SIGB_RX_PKT_TYPE_11B,
143*5113495bSYour Name HAL_SIGB_RX_PKT_TYPE_HT_MM,
144*5113495bSYour Name HAL_SIGB_RX_PKT_TYPE_11AC,
145*5113495bSYour Name HAL_SIGB_RX_PKT_TYPE_11AX,
146*5113495bSYour Name HAL_SIGB_RX_PKT_TYPE_HT_GF,
147*5113495bSYour Name HAL_SIGB_RX_PKT_TYPE_11BE,
148*5113495bSYour Name };
149*5113495bSYour Name
150*5113495bSYour Name #define PMM_REG_BASE_QCN9224 0xB500F8
151*5113495bSYour Name
152*5113495bSYour Name /**
153*5113495bSYour Name * hal_read_pmm_scratch_reg() - API to read PMM Scratch register
154*5113495bSYour Name * @soc: HAL soc
155*5113495bSYour Name * @base_addr: Base PMM register
156*5113495bSYour Name * @reg_enum: Enum of the scratch register
157*5113495bSYour Name *
158*5113495bSYour Name * Return: uint32_t
159*5113495bSYour Name */
160*5113495bSYour Name static inline
hal_read_pmm_scratch_reg(struct hal_soc * soc,uint32_t base_addr,enum hal_scratch_reg_enum reg_enum)161*5113495bSYour Name uint32_t hal_read_pmm_scratch_reg(struct hal_soc *soc,
162*5113495bSYour Name uint32_t base_addr,
163*5113495bSYour Name enum hal_scratch_reg_enum reg_enum)
164*5113495bSYour Name {
165*5113495bSYour Name uint32_t val = 0;
166*5113495bSYour Name
167*5113495bSYour Name pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL);
168*5113495bSYour Name return val;
169*5113495bSYour Name }
170*5113495bSYour Name
171*5113495bSYour Name /**
172*5113495bSYour Name * hal_get_tsf2_scratch_reg_qcn9224() - API to read tsf2 scratch register
173*5113495bSYour Name * @hal_soc_hdl: HAL soc context
174*5113495bSYour Name * @mac_id: mac id
175*5113495bSYour Name * @value: Pointer to update tsf2 value
176*5113495bSYour Name *
177*5113495bSYour Name * Return: void
178*5113495bSYour Name */
hal_get_tsf2_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,uint8_t mac_id,uint64_t * value)179*5113495bSYour Name static void hal_get_tsf2_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,
180*5113495bSYour Name uint8_t mac_id, uint64_t *value)
181*5113495bSYour Name {
182*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
183*5113495bSYour Name uint32_t offset_lo, offset_hi;
184*5113495bSYour Name enum hal_scratch_reg_enum enum_lo, enum_hi;
185*5113495bSYour Name
186*5113495bSYour Name hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
187*5113495bSYour Name
188*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg(soc,
189*5113495bSYour Name PMM_REG_BASE_QCN9224,
190*5113495bSYour Name enum_lo);
191*5113495bSYour Name
192*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg(soc,
193*5113495bSYour Name PMM_REG_BASE_QCN9224,
194*5113495bSYour Name enum_hi);
195*5113495bSYour Name
196*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
197*5113495bSYour Name }
198*5113495bSYour Name
199*5113495bSYour Name /**
200*5113495bSYour Name * hal_get_tqm_scratch_reg_qcn9224() - API to read tqm scratch register
201*5113495bSYour Name * @hal_soc_hdl: HAL soc context
202*5113495bSYour Name * @value: Pointer to update tqm value
203*5113495bSYour Name *
204*5113495bSYour Name * Return: void
205*5113495bSYour Name */
hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,uint64_t * value)206*5113495bSYour Name static void hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,
207*5113495bSYour Name uint64_t *value)
208*5113495bSYour Name {
209*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
210*5113495bSYour Name uint32_t offset_lo, offset_hi;
211*5113495bSYour Name
212*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg(soc,
213*5113495bSYour Name PMM_REG_BASE_QCN9224,
214*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_LO_US);
215*5113495bSYour Name
216*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg(soc,
217*5113495bSYour Name PMM_REG_BASE_QCN9224,
218*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_HI_US);
219*5113495bSYour Name
220*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
221*5113495bSYour Name }
222*5113495bSYour Name
223*5113495bSYour Name #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
224*5113495bSYour Name #define HAL_PPE_VP_ENTRIES_MAX 32
225*5113495bSYour Name #define HAL_PPE_VP_SEARCH_IDX_REG_MAX 8
226*5113495bSYour Name
227*5113495bSYour Name /**
228*5113495bSYour Name * hal_get_link_desc_size_9224() - API to get the link desc size
229*5113495bSYour Name *
230*5113495bSYour Name * Return: uint32_t
231*5113495bSYour Name */
hal_get_link_desc_size_9224(void)232*5113495bSYour Name static uint32_t hal_get_link_desc_size_9224(void)
233*5113495bSYour Name {
234*5113495bSYour Name return LINK_DESC_SIZE;
235*5113495bSYour Name }
236*5113495bSYour Name
237*5113495bSYour Name /**
238*5113495bSYour Name * hal_rx_get_tlv_9224() - API to get the tlv
239*5113495bSYour Name * @rx_tlv: TLV data extracted from the rx packet
240*5113495bSYour Name *
241*5113495bSYour Name * Return: uint8_t
242*5113495bSYour Name */
hal_rx_get_tlv_9224(void * rx_tlv)243*5113495bSYour Name static uint8_t hal_rx_get_tlv_9224(void *rx_tlv)
244*5113495bSYour Name {
245*5113495bSYour Name return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
246*5113495bSYour Name }
247*5113495bSYour Name
248*5113495bSYour Name /**
249*5113495bSYour Name * hal_rx_wbm_err_msdu_continuation_get_9224() - API to check if WBM msdu
250*5113495bSYour Name * continuation bit is set
251*5113495bSYour Name * @wbm_desc: wbm release ring descriptor
252*5113495bSYour Name *
253*5113495bSYour Name * Return: true if msdu continuation bit is set.
254*5113495bSYour Name */
255*5113495bSYour Name static inline
hal_rx_wbm_err_msdu_continuation_get_9224(void * wbm_desc)256*5113495bSYour Name uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc)
257*5113495bSYour Name {
258*5113495bSYour Name uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
259*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
260*5113495bSYour Name
261*5113495bSYour Name return (comp_desc &
262*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
263*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
264*5113495bSYour Name }
265*5113495bSYour Name
266*5113495bSYour Name #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
267*5113495bSYour Name #define HAL_RX_EVM_DEMF_SEGMENT_SIZE 128
268*5113495bSYour Name #define HAL_RX_EVM_DEMF_MAX_STREAMS 2
269*5113495bSYour Name #define HAL_RX_SU_EVM_MEMBER_LEN 4
270*5113495bSYour Name static inline void
hal_rx_update_su_evm_info(void * rx_tlv,void * ppdu_info_hdl)271*5113495bSYour Name hal_rx_update_su_evm_info(void *rx_tlv,
272*5113495bSYour Name void *ppdu_info_hdl)
273*5113495bSYour Name {
274*5113495bSYour Name uint32_t nss_count, pilot_count;
275*5113495bSYour Name uint16_t istream = 0, ipilot = 0;
276*5113495bSYour Name uint8_t pilot_shift = 0;
277*5113495bSYour Name uint8_t *pilot_ptr = NULL;
278*5113495bSYour Name uint16_t segment = 0;
279*5113495bSYour Name
280*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info =
281*5113495bSYour Name (struct hal_rx_ppdu_info *)ppdu_info_hdl;
282*5113495bSYour Name nss_count = ppdu_info->evm_info.nss_count;
283*5113495bSYour Name pilot_count = ppdu_info->evm_info.pilot_count;
284*5113495bSYour Name
285*5113495bSYour Name if (nss_count * pilot_count > HAL_RX_MAX_SU_EVM_COUNT)
286*5113495bSYour Name return;
287*5113495bSYour Name
288*5113495bSYour Name /* move rx_tlv by 4 to skip no_of_data_sym, nss_cnt and pilot_cnt */
289*5113495bSYour Name rx_tlv = (uint8_t *)rx_tlv + HAL_RX_SU_EVM_MEMBER_LEN;
290*5113495bSYour Name
291*5113495bSYour Name /* EVM values = number_of_streams * number_of_pilots
292*5113495bSYour Name * each EVM value is 8 bits, So, each variable acc_linear_evm_x_y
293*5113495bSYour Name * is (32 bits) will contain 4 EVM values.
294*5113495bSYour Name * For ex:
295*5113495bSYour Name * acc_linear_evm_0_0 : <Pilot0, stream0>, <Pilot0, stream1>,
296*5113495bSYour Name * <Pilot1, stream0>, <Pilot1, stream1>
297*5113495bSYour Name * .....
298*5113495bSYour Name * acc_linear_evm_1_15 : <Pilot62, stream0>, <Pilot62, stream1>,
299*5113495bSYour Name * <Pilot63, stream0>, <Pilot63, stream1> ...
300*5113495bSYour Name */
301*5113495bSYour Name
302*5113495bSYour Name for (istream = 0; istream < nss_count; istream++) {
303*5113495bSYour Name segment = HAL_RX_EVM_DEMF_SEGMENT_SIZE * (istream / HAL_RX_EVM_DEMF_MAX_STREAMS);
304*5113495bSYour Name pilot_ptr = (uint8_t *)rx_tlv + segment;
305*5113495bSYour Name for (ipilot = 0; ipilot < pilot_count; ipilot++) {
306*5113495bSYour Name /* In case there is one stream in Demf segment,
307*5113495bSYour Name * pilots are one after the other
308*5113495bSYour Name */
309*5113495bSYour Name if (nss_count == 1 ||
310*5113495bSYour Name ((nss_count == HAL_RX_EVM_DEMF_MAX_STREAMS + 1) &&
311*5113495bSYour Name (istream == HAL_RX_EVM_DEMF_MAX_STREAMS)))
312*5113495bSYour Name pilot_shift = ipilot;
313*5113495bSYour Name /* In case there are more than one stream in DemF
314*5113495bSYour Name * segment, pilot 0 of all streams come one after the
315*5113495bSYour Name * other before pilot 1
316*5113495bSYour Name */
317*5113495bSYour Name else
318*5113495bSYour Name pilot_shift = (ipilot * HAL_RX_EVM_DEMF_MAX_STREAMS)
319*5113495bSYour Name + (istream % HAL_RX_EVM_DEMF_MAX_STREAMS);
320*5113495bSYour Name
321*5113495bSYour Name ppdu_info->evm_info.pilot_evm[segment + pilot_shift] =
322*5113495bSYour Name *(pilot_ptr + pilot_shift);
323*5113495bSYour Name }
324*5113495bSYour Name }
325*5113495bSYour Name }
326*5113495bSYour Name
327*5113495bSYour Name /**
328*5113495bSYour Name * hal_rx_proc_phyrx_other_receive_info_tlv_9224() - API to get tlv info
329*5113495bSYour Name * @rx_tlv_hdr: RX TLV header
330*5113495bSYour Name * @ppdu_info_hdl: Handle to PPDU info to update
331*5113495bSYour Name *
332*5113495bSYour Name * Return: None
333*5113495bSYour Name */
334*5113495bSYour Name static inline
hal_rx_proc_phyrx_other_receive_info_tlv_9224(void * rx_tlv_hdr,void * ppdu_info_hdl)335*5113495bSYour Name void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
336*5113495bSYour Name void *ppdu_info_hdl)
337*5113495bSYour Name {
338*5113495bSYour Name uint32_t tlv_tag, tlv_len, pkt_type;
339*5113495bSYour Name void *rx_tlv;
340*5113495bSYour Name uint32_t ru_details_channel_0;
341*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info =
342*5113495bSYour Name (struct hal_rx_ppdu_info *)ppdu_info_hdl;
343*5113495bSYour Name
344*5113495bSYour Name hal_rx_proc_phyrx_all_sigb_tlv_9224(rx_tlv_hdr, ppdu_info_hdl);
345*5113495bSYour Name
346*5113495bSYour Name tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
347*5113495bSYour Name rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
348*5113495bSYour Name
349*5113495bSYour Name if (!tlv_len)
350*5113495bSYour Name return;
351*5113495bSYour Name
352*5113495bSYour Name tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
353*5113495bSYour Name rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV64_HDR_SIZE;
354*5113495bSYour Name
355*5113495bSYour Name pkt_type = HAL_RX_GET_64(rx_tlv,
356*5113495bSYour Name PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS,
357*5113495bSYour Name PKT_TYPE);
358*5113495bSYour Name
359*5113495bSYour Name switch (tlv_tag) {
360*5113495bSYour Name case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E:
361*5113495bSYour Name if (pkt_type ==
362*5113495bSYour Name HAL_RX_PKT_TYPE_11AX) {
363*5113495bSYour Name ru_details_channel_0 =
364*5113495bSYour Name HAL_RX_GET(rx_tlv,
365*5113495bSYour Name PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS,
366*5113495bSYour Name RU_DETAILS_CHANNEL_0);
367*5113495bSYour Name
368*5113495bSYour Name qdf_mem_copy(ppdu_info->rx_status.he_RU,
369*5113495bSYour Name &ru_details_channel_0,
370*5113495bSYour Name sizeof(ppdu_info->rx_status.he_RU));
371*5113495bSYour Name
372*5113495bSYour Name ppdu_info->rx_status.he_flags1 |=
373*5113495bSYour Name QDF_MON_STATUS_CHANNEL_1_RU_KNOWN;
374*5113495bSYour Name if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40) {
375*5113495bSYour Name ppdu_info->rx_status.he_flags1 |=
376*5113495bSYour Name QDF_MON_STATUS_CHANNEL_2_RU_KNOWN;
377*5113495bSYour Name }
378*5113495bSYour Name }
379*5113495bSYour Name
380*5113495bSYour Name break;
381*5113495bSYour Name default:
382*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
383*5113495bSYour Name "%s unhandled TLV type: %d, TLV len:%d",
384*5113495bSYour Name __func__, tlv_tag, tlv_len);
385*5113495bSYour Name break;
386*5113495bSYour Name }
387*5113495bSYour Name }
388*5113495bSYour Name
389*5113495bSYour Name static inline uint32_t
hal_rx_parse_ru_allocation_9224(struct hal_soc * hal_soc,void * tlv,struct hal_rx_ppdu_info * ppdu_info)390*5113495bSYour Name hal_rx_parse_ru_allocation_9224(struct hal_soc *hal_soc, void *tlv,
391*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info)
392*5113495bSYour Name {
393*5113495bSYour Name uint64_t *ehtsig_tlv = (uint64_t *)tlv;
394*5113495bSYour Name struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cc1_cmn_eb1;
395*5113495bSYour Name struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cc2_cmn_eb1;
396*5113495bSYour Name struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cc1_cmn_eb2;
397*5113495bSYour Name struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cc2_cmn_eb2;
398*5113495bSYour Name uint8_t num_ru_allocation_known = 0;
399*5113495bSYour Name
400*5113495bSYour Name ofdma_cc1_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv;
401*5113495bSYour Name ofdma_cc2_cmn_eb1 =
402*5113495bSYour Name (struct hal_eht_sig_ofdma_cmn_eb1 *)(ehtsig_tlv + 1);
403*5113495bSYour Name ofdma_cc1_cmn_eb2 =
404*5113495bSYour Name (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 2);
405*5113495bSYour Name ofdma_cc2_cmn_eb2 =
406*5113495bSYour Name (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 3);
407*5113495bSYour Name
408*5113495bSYour Name switch (ppdu_info->u_sig_info.bw) {
409*5113495bSYour Name case HAL_EHT_BW_320_2:
410*5113495bSYour Name case HAL_EHT_BW_320_1:
411*5113495bSYour Name num_ru_allocation_known += 8;
412*5113495bSYour Name
413*5113495bSYour Name ppdu_info->rx_status.eht_data[4] |=
414*5113495bSYour Name (ofdma_cc1_cmn_eb2->ru_allocation2_3 <<
415*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_5_SHIFT);
416*5113495bSYour Name ppdu_info->rx_status.eht_data[4] |= 1 <<
417*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_5_SHIFT;
418*5113495bSYour Name
419*5113495bSYour Name ppdu_info->rx_status.eht_data[4] |=
420*5113495bSYour Name (ofdma_cc2_cmn_eb2->ru_allocation2_3 <<
421*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_5_SHIFT);
422*5113495bSYour Name ppdu_info->rx_status.eht_data[4] |= 1 <<
423*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_5_SHIFT;
424*5113495bSYour Name
425*5113495bSYour Name ppdu_info->rx_status.eht_data[5] |=
426*5113495bSYour Name (ofdma_cc1_cmn_eb2->ru_allocation2_4 <<
427*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_6_SHIFT);
428*5113495bSYour Name ppdu_info->rx_status.eht_data[5] |= 1 <<
429*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_6_SHIFT;
430*5113495bSYour Name
431*5113495bSYour Name ppdu_info->rx_status.eht_data[5] |=
432*5113495bSYour Name (ofdma_cc2_cmn_eb2->ru_allocation2_4 <<
433*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_6_SHIFT);
434*5113495bSYour Name ppdu_info->rx_status.eht_data[5] |= 1 <<
435*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_6_SHIFT;
436*5113495bSYour Name
437*5113495bSYour Name ppdu_info->rx_status.eht_data[5] |=
438*5113495bSYour Name (ofdma_cc1_cmn_eb2->ru_allocation2_5 <<
439*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_7_SHIFT);
440*5113495bSYour Name ppdu_info->rx_status.eht_data[5] |= 1 <<
441*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_7_SHIFT;
442*5113495bSYour Name
443*5113495bSYour Name ppdu_info->rx_status.eht_data[6] |=
444*5113495bSYour Name (ofdma_cc2_cmn_eb2->ru_allocation2_5 <<
445*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_7_SHIFT);
446*5113495bSYour Name ppdu_info->rx_status.eht_data[6] |= 1 <<
447*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_7_SHIFT;
448*5113495bSYour Name
449*5113495bSYour Name ppdu_info->rx_status.eht_data[6] |=
450*5113495bSYour Name (ofdma_cc1_cmn_eb2->ru_allocation2_6 <<
451*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_8_SHIFT);
452*5113495bSYour Name ppdu_info->rx_status.eht_data[6] |= 1 <<
453*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_8_SHIFT;
454*5113495bSYour Name
455*5113495bSYour Name ppdu_info->rx_status.eht_data[6] |=
456*5113495bSYour Name (ofdma_cc2_cmn_eb2->ru_allocation2_6 <<
457*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_8_SHIFT);
458*5113495bSYour Name num_ru_allocation_known += 4;
459*5113495bSYour Name fallthrough;
460*5113495bSYour Name
461*5113495bSYour Name case HAL_EHT_BW_160:
462*5113495bSYour Name ppdu_info->rx_status.eht_data[3] |=
463*5113495bSYour Name (ofdma_cc1_cmn_eb2->ru_allocation2_1 <<
464*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_3_SHIFT);
465*5113495bSYour Name ppdu_info->rx_status.eht_data[3] |= 1 <<
466*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_3_SHIFT;
467*5113495bSYour Name ppdu_info->rx_status.eht_data[3] |=
468*5113495bSYour Name (ofdma_cc2_cmn_eb2->ru_allocation2_1 <<
469*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_3_SHIFT);
470*5113495bSYour Name ppdu_info->rx_status.eht_data[3] |= 1 <<
471*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_3_SHIFT;
472*5113495bSYour Name ppdu_info->rx_status.eht_data[3] |=
473*5113495bSYour Name (ofdma_cc1_cmn_eb2->ru_allocation2_2 <<
474*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_4_SHIFT);
475*5113495bSYour Name ppdu_info->rx_status.eht_data[3] |= 1 <<
476*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_4_SHIFT;
477*5113495bSYour Name ppdu_info->rx_status.eht_data[4] |=
478*5113495bSYour Name (ofdma_cc2_cmn_eb2->ru_allocation2_2 <<
479*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_4_SHIFT);
480*5113495bSYour Name ppdu_info->rx_status.eht_data[4] |= 1 <<
481*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_4_SHIFT;
482*5113495bSYour Name ppdu_info->tlv_aggr.rd_idx += 16;
483*5113495bSYour Name fallthrough;
484*5113495bSYour Name
485*5113495bSYour Name case HAL_EHT_BW_80:
486*5113495bSYour Name num_ru_allocation_known += 2;
487*5113495bSYour Name
488*5113495bSYour Name ppdu_info->rx_status.eht_data[2] |=
489*5113495bSYour Name (ofdma_cc1_cmn_eb1->ru_allocation1_2 <<
490*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_2_SHIFT);
491*5113495bSYour Name ppdu_info->rx_status.eht_data[2] |= 1 <<
492*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_2_SHIFT;
493*5113495bSYour Name ppdu_info->rx_status.eht_data[2] |=
494*5113495bSYour Name (ofdma_cc2_cmn_eb1->ru_allocation1_2 <<
495*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_2_SHIFT);
496*5113495bSYour Name ppdu_info->rx_status.eht_data[2] |= 1 <<
497*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_2_SHIFT;
498*5113495bSYour Name fallthrough;
499*5113495bSYour Name
500*5113495bSYour Name case HAL_EHT_BW_40:
501*5113495bSYour Name num_ru_allocation_known += 1;
502*5113495bSYour Name
503*5113495bSYour Name ppdu_info->rx_status.eht_data[2] |=
504*5113495bSYour Name (ofdma_cc2_cmn_eb1->ru_allocation1_1 <<
505*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_1_SHIFT);
506*5113495bSYour Name ppdu_info->rx_status.eht_data[2] |= 1 <<
507*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_1_SHIFT;
508*5113495bSYour Name ppdu_info->tlv_aggr.rd_idx += 8;
509*5113495bSYour Name fallthrough;
510*5113495bSYour Name
511*5113495bSYour Name case HAL_EHT_BW_20:
512*5113495bSYour Name num_ru_allocation_known += 1;
513*5113495bSYour Name
514*5113495bSYour Name ppdu_info->rx_status.eht_data[1] |=
515*5113495bSYour Name (ofdma_cc1_cmn_eb1->ru_allocation1_1 <<
516*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_1_SHIFT);
517*5113495bSYour Name ppdu_info->rx_status.eht_data[1] |= 1 <<
518*5113495bSYour Name QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_1_SHIFT;
519*5113495bSYour Name ppdu_info->tlv_aggr.rd_idx += 8;
520*5113495bSYour Name break;
521*5113495bSYour Name default:
522*5113495bSYour Name break;
523*5113495bSYour Name }
524*5113495bSYour Name
525*5113495bSYour Name ppdu_info->rx_status.eht_known |= (num_ru_allocation_known <<
526*5113495bSYour Name QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT);
527*5113495bSYour Name
528*5113495bSYour Name return HAL_TLV_STATUS_PPDU_NOT_DONE;
529*5113495bSYour Name }
530*5113495bSYour Name
531*5113495bSYour Name static inline uint32_t
hal_rx_parse_eht_sig_non_ofdma_9224(struct hal_soc * hal_soc,void * tlv,struct hal_rx_ppdu_info * ppdu_info)532*5113495bSYour Name hal_rx_parse_eht_sig_non_ofdma_9224(struct hal_soc *hal_soc, void *tlv,
533*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info)
534*5113495bSYour Name {
535*5113495bSYour Name hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info);
536*5113495bSYour Name hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info);
537*5113495bSYour Name
538*5113495bSYour Name if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info)) {
539*5113495bSYour Name ppdu_info->tlv_aggr.rd_idx += 16;
540*5113495bSYour Name hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, tlv,
541*5113495bSYour Name ppdu_info);
542*5113495bSYour Name } else {
543*5113495bSYour Name ppdu_info->tlv_aggr.rd_idx += 4;
544*5113495bSYour Name hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, tlv,
545*5113495bSYour Name ppdu_info);
546*5113495bSYour Name }
547*5113495bSYour Name
548*5113495bSYour Name return HAL_TLV_STATUS_PPDU_NOT_DONE;
549*5113495bSYour Name }
550*5113495bSYour Name
551*5113495bSYour Name static inline uint32_t
hal_rx_parse_eht_sig_ofdma_9224(struct hal_soc * hal_soc,void * tlv,struct hal_rx_ppdu_info * ppdu_info)552*5113495bSYour Name hal_rx_parse_eht_sig_ofdma_9224(struct hal_soc *hal_soc, void *tlv,
553*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info)
554*5113495bSYour Name {
555*5113495bSYour Name hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info);
556*5113495bSYour Name hal_rx_parse_ru_allocation_9224(hal_soc, tlv, ppdu_info);
557*5113495bSYour Name hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, tlv,
558*5113495bSYour Name ppdu_info);
559*5113495bSYour Name
560*5113495bSYour Name return HAL_TLV_STATUS_PPDU_NOT_DONE;
561*5113495bSYour Name }
562*5113495bSYour Name
563*5113495bSYour Name /**
564*5113495bSYour Name * hal_rx_parse_eht_sig_hdr_9224()
565*5113495bSYour Name * - process eht sig header
566*5113495bSYour Name * @hal_soc: HAL soc handle
567*5113495bSYour Name * @tlv: pointer to EHT SIG TLV buffer
568*5113495bSYour Name * @ppdu_info_handle: pointer to ppdu_info
569*5113495bSYour Name *
570*5113495bSYour Name * Return: None
571*5113495bSYour Name */
572*5113495bSYour Name static
hal_rx_parse_eht_sig_hdr_9224(struct hal_soc * hal_soc,uint8_t * tlv,void * ppdu_info_handle)573*5113495bSYour Name void hal_rx_parse_eht_sig_hdr_9224(struct hal_soc *hal_soc,
574*5113495bSYour Name uint8_t *tlv,
575*5113495bSYour Name void *ppdu_info_handle)
576*5113495bSYour Name {
577*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info = ppdu_info_handle;
578*5113495bSYour Name
579*5113495bSYour Name ppdu_info->rx_status.eht_flags = 1;
580*5113495bSYour Name
581*5113495bSYour Name if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info))
582*5113495bSYour Name hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info);
583*5113495bSYour Name else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info))
584*5113495bSYour Name hal_rx_parse_eht_sig_non_ofdma_9224(hal_soc, tlv, ppdu_info);
585*5113495bSYour Name else if (hal_rx_is_ofdma(hal_soc, ppdu_info))
586*5113495bSYour Name hal_rx_parse_eht_sig_ofdma_9224(hal_soc, tlv, ppdu_info);
587*5113495bSYour Name }
588*5113495bSYour Name
589*5113495bSYour Name #else
590*5113495bSYour Name /**
591*5113495bSYour Name * hal_rx_proc_phyrx_other_receive_info_tlv_9224() - API to get tlv info
592*5113495bSYour Name * @rx_tlv_hdr: RX TLV header
593*5113495bSYour Name * @ppdu_info_hdl: Handle to PPDU info to update
594*5113495bSYour Name *
595*5113495bSYour Name * Return: None
596*5113495bSYour Name */
597*5113495bSYour Name static inline
hal_rx_proc_phyrx_other_receive_info_tlv_9224(void * rx_tlv_hdr,void * ppdu_info_hdl)598*5113495bSYour Name void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
599*5113495bSYour Name void *ppdu_info_hdl)
600*5113495bSYour Name {
601*5113495bSYour Name }
602*5113495bSYour Name #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */
603*5113495bSYour Name
604*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
605*5113495bSYour Name static inline
hal_rx_get_bb_info_9224(void * rx_tlv,void * ppdu_info_hdl)606*5113495bSYour Name void hal_rx_get_bb_info_9224(void *rx_tlv, void *ppdu_info_hdl)
607*5113495bSYour Name {
608*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
609*5113495bSYour Name
610*5113495bSYour Name ppdu_info->cfr_info.bb_captured_channel =
611*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
612*5113495bSYour Name
613*5113495bSYour Name ppdu_info->cfr_info.bb_captured_timeout =
614*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
615*5113495bSYour Name
616*5113495bSYour Name ppdu_info->cfr_info.bb_captured_reason =
617*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
618*5113495bSYour Name }
619*5113495bSYour Name
620*5113495bSYour Name static inline
hal_rx_get_rtt_info_9224(void * rx_tlv,void * ppdu_info_hdl)621*5113495bSYour Name void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl)
622*5113495bSYour Name {
623*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
624*5113495bSYour Name
625*5113495bSYour Name ppdu_info->cfr_info.rx_location_info_valid =
626*5113495bSYour Name HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
627*5113495bSYour Name RX_LOCATION_INFO_VALID);
628*5113495bSYour Name
629*5113495bSYour Name ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
630*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
631*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
632*5113495bSYour Name RTT_CHE_BUFFER_POINTER_LOW32);
633*5113495bSYour Name
634*5113495bSYour Name ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
635*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
636*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
637*5113495bSYour Name RTT_CHE_BUFFER_POINTER_HIGH8);
638*5113495bSYour Name
639*5113495bSYour Name ppdu_info->cfr_info.chan_capture_status =
640*5113495bSYour Name HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
641*5113495bSYour Name
642*5113495bSYour Name ppdu_info->cfr_info.rx_start_ts =
643*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
644*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
645*5113495bSYour Name RX_START_TS);
646*5113495bSYour Name
647*5113495bSYour Name ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
648*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
649*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
650*5113495bSYour Name RTT_CFO_MEASUREMENT);
651*5113495bSYour Name
652*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info0 =
653*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
654*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
655*5113495bSYour Name GAIN_CHAIN0);
656*5113495bSYour Name
657*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info0 |=
658*5113495bSYour Name (((uint32_t)HAL_RX_GET_64(rx_tlv,
659*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
660*5113495bSYour Name GAIN_CHAIN1)) << 16);
661*5113495bSYour Name
662*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info1 =
663*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
664*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
665*5113495bSYour Name GAIN_CHAIN2);
666*5113495bSYour Name
667*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info1 |=
668*5113495bSYour Name (((uint32_t)HAL_RX_GET_64(rx_tlv,
669*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
670*5113495bSYour Name GAIN_CHAIN3)) << 16);
671*5113495bSYour Name
672*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info2 = 0;
673*5113495bSYour Name
674*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info3 = 0;
675*5113495bSYour Name
676*5113495bSYour Name ppdu_info->cfr_info.mcs_rate =
677*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
678*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
679*5113495bSYour Name RTT_MCS_RATE);
680*5113495bSYour Name ppdu_info->cfr_info.gi_type =
681*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
682*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
683*5113495bSYour Name RTT_GI_TYPE);
684*5113495bSYour Name }
685*5113495bSYour Name #endif
686*5113495bSYour Name
687*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
688*5113495bSYour Name /**
689*5113495bSYour Name * hal_rx_dump_mpdu_start_tlv_9224() - dump RX mpdu_start TLV in structured
690*5113495bSYour Name * human readable format.
691*5113495bSYour Name * @mpdustart: pointer the rx_attention TLV in pkt.
692*5113495bSYour Name * @dbg_level: log level.
693*5113495bSYour Name *
694*5113495bSYour Name * Return: void
695*5113495bSYour Name */
hal_rx_dump_mpdu_start_tlv_9224(void * mpdustart,uint8_t dbg_level)696*5113495bSYour Name static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
697*5113495bSYour Name uint8_t dbg_level)
698*5113495bSYour Name {
699*5113495bSYour Name struct rx_mpdu_start_compact *mpdu_info =
700*5113495bSYour Name (struct rx_mpdu_start_compact *)mpdustart;
701*5113495bSYour Name
702*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
703*5113495bSYour Name "rx_mpdu_start tlv (1/5) - "
704*5113495bSYour Name "rx_reo_queue_desc_addr_39_32 :%x"
705*5113495bSYour Name "receive_queue_number:%x "
706*5113495bSYour Name "pre_delim_err_warning:%x "
707*5113495bSYour Name "first_delim_err:%x "
708*5113495bSYour Name "pn_31_0:%x "
709*5113495bSYour Name "pn_63_32:%x "
710*5113495bSYour Name "pn_95_64:%x ",
711*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_39_32,
712*5113495bSYour Name mpdu_info->receive_queue_number,
713*5113495bSYour Name mpdu_info->pre_delim_err_warning,
714*5113495bSYour Name mpdu_info->first_delim_err,
715*5113495bSYour Name mpdu_info->pn_31_0,
716*5113495bSYour Name mpdu_info->pn_63_32,
717*5113495bSYour Name mpdu_info->pn_95_64);
718*5113495bSYour Name
719*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
720*5113495bSYour Name "rx_mpdu_start tlv (2/5) - "
721*5113495bSYour Name "ast_index:%x "
722*5113495bSYour Name "sw_peer_id:%x "
723*5113495bSYour Name "mpdu_frame_control_valid:%x "
724*5113495bSYour Name "mpdu_duration_valid:%x "
725*5113495bSYour Name "mac_addr_ad1_valid:%x "
726*5113495bSYour Name "mac_addr_ad2_valid:%x "
727*5113495bSYour Name "mac_addr_ad3_valid:%x "
728*5113495bSYour Name "mac_addr_ad4_valid:%x "
729*5113495bSYour Name "mpdu_sequence_control_valid :%x"
730*5113495bSYour Name "mpdu_qos_control_valid:%x "
731*5113495bSYour Name "mpdu_ht_control_valid:%x "
732*5113495bSYour Name "frame_encryption_info_valid :%x",
733*5113495bSYour Name mpdu_info->ast_index,
734*5113495bSYour Name mpdu_info->sw_peer_id,
735*5113495bSYour Name mpdu_info->mpdu_frame_control_valid,
736*5113495bSYour Name mpdu_info->mpdu_duration_valid,
737*5113495bSYour Name mpdu_info->mac_addr_ad1_valid,
738*5113495bSYour Name mpdu_info->mac_addr_ad2_valid,
739*5113495bSYour Name mpdu_info->mac_addr_ad3_valid,
740*5113495bSYour Name mpdu_info->mac_addr_ad4_valid,
741*5113495bSYour Name mpdu_info->mpdu_sequence_control_valid,
742*5113495bSYour Name mpdu_info->mpdu_qos_control_valid,
743*5113495bSYour Name mpdu_info->mpdu_ht_control_valid,
744*5113495bSYour Name mpdu_info->frame_encryption_info_valid);
745*5113495bSYour Name
746*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
747*5113495bSYour Name "rx_mpdu_start tlv (3/5) - "
748*5113495bSYour Name "mpdu_fragment_number:%x "
749*5113495bSYour Name "more_fragment_flag:%x "
750*5113495bSYour Name "fr_ds:%x "
751*5113495bSYour Name "to_ds:%x "
752*5113495bSYour Name "encrypted:%x "
753*5113495bSYour Name "mpdu_retry:%x "
754*5113495bSYour Name "mpdu_sequence_number:%x ",
755*5113495bSYour Name mpdu_info->mpdu_fragment_number,
756*5113495bSYour Name mpdu_info->more_fragment_flag,
757*5113495bSYour Name mpdu_info->fr_ds,
758*5113495bSYour Name mpdu_info->to_ds,
759*5113495bSYour Name mpdu_info->encrypted,
760*5113495bSYour Name mpdu_info->mpdu_retry,
761*5113495bSYour Name mpdu_info->mpdu_sequence_number);
762*5113495bSYour Name
763*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
764*5113495bSYour Name "rx_mpdu_start tlv (4/5) - "
765*5113495bSYour Name "mpdu_frame_control_field:%x "
766*5113495bSYour Name "mpdu_duration_field:%x ",
767*5113495bSYour Name mpdu_info->mpdu_frame_control_field,
768*5113495bSYour Name mpdu_info->mpdu_duration_field);
769*5113495bSYour Name
770*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
771*5113495bSYour Name "rx_mpdu_start tlv (5/5) - "
772*5113495bSYour Name "mac_addr_ad1_31_0:%x "
773*5113495bSYour Name "mac_addr_ad1_47_32:%x "
774*5113495bSYour Name "mac_addr_ad2_15_0:%x "
775*5113495bSYour Name "mac_addr_ad2_47_16:%x "
776*5113495bSYour Name "mac_addr_ad3_31_0:%x "
777*5113495bSYour Name "mac_addr_ad3_47_32:%x "
778*5113495bSYour Name "mpdu_sequence_control_field :%x",
779*5113495bSYour Name mpdu_info->mac_addr_ad1_31_0,
780*5113495bSYour Name mpdu_info->mac_addr_ad1_47_32,
781*5113495bSYour Name mpdu_info->mac_addr_ad2_15_0,
782*5113495bSYour Name mpdu_info->mac_addr_ad2_47_16,
783*5113495bSYour Name mpdu_info->mac_addr_ad3_31_0,
784*5113495bSYour Name mpdu_info->mac_addr_ad3_47_32,
785*5113495bSYour Name mpdu_info->mpdu_sequence_control_field);
786*5113495bSYour Name }
787*5113495bSYour Name
788*5113495bSYour Name /**
789*5113495bSYour Name * hal_rx_dump_msdu_end_tlv_9224() - dump RX msdu_end TLV in structured human
790*5113495bSYour Name * readable format.
791*5113495bSYour Name * @msduend: pointer the msdu_end TLV in pkt.
792*5113495bSYour Name * @dbg_level: log level.
793*5113495bSYour Name *
794*5113495bSYour Name * Return: void
795*5113495bSYour Name */
hal_rx_dump_msdu_end_tlv_9224(void * msduend,uint8_t dbg_level)796*5113495bSYour Name static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
797*5113495bSYour Name uint8_t dbg_level)
798*5113495bSYour Name {
799*5113495bSYour Name struct rx_msdu_end_compact *msdu_end =
800*5113495bSYour Name (struct rx_msdu_end_compact *)msduend;
801*5113495bSYour Name
802*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
803*5113495bSYour Name "rx_msdu_end tlv - "
804*5113495bSYour Name "key_id_octet: %d "
805*5113495bSYour Name "tcp_udp_chksum: %d "
806*5113495bSYour Name "sa_idx_timeout: %d "
807*5113495bSYour Name "da_idx_timeout: %d "
808*5113495bSYour Name "msdu_limit_error: %d "
809*5113495bSYour Name "flow_idx_timeout: %d "
810*5113495bSYour Name "flow_idx_invalid: %d "
811*5113495bSYour Name "wifi_parser_error: %d "
812*5113495bSYour Name "sa_is_valid: %d "
813*5113495bSYour Name "da_is_valid: %d "
814*5113495bSYour Name "da_is_mcbc: %d "
815*5113495bSYour Name "tkip_mic_err: %d "
816*5113495bSYour Name "l3_header_padding: %d "
817*5113495bSYour Name "first_msdu: %d "
818*5113495bSYour Name "last_msdu: %d "
819*5113495bSYour Name "sa_idx: %d "
820*5113495bSYour Name "msdu_drop: %d "
821*5113495bSYour Name "reo_destination_indication: %d "
822*5113495bSYour Name "flow_idx: %d "
823*5113495bSYour Name "fse_metadata: %d "
824*5113495bSYour Name "cce_metadata: %d "
825*5113495bSYour Name "sa_sw_peer_id: %d ",
826*5113495bSYour Name msdu_end->key_id_octet,
827*5113495bSYour Name msdu_end->tcp_udp_chksum,
828*5113495bSYour Name msdu_end->sa_idx_timeout,
829*5113495bSYour Name msdu_end->da_idx_timeout,
830*5113495bSYour Name msdu_end->msdu_limit_error,
831*5113495bSYour Name msdu_end->flow_idx_timeout,
832*5113495bSYour Name msdu_end->flow_idx_invalid,
833*5113495bSYour Name msdu_end->wifi_parser_error,
834*5113495bSYour Name msdu_end->sa_is_valid,
835*5113495bSYour Name msdu_end->da_is_valid,
836*5113495bSYour Name msdu_end->da_is_mcbc,
837*5113495bSYour Name msdu_end->tkip_mic_err,
838*5113495bSYour Name msdu_end->l3_header_padding,
839*5113495bSYour Name msdu_end->first_msdu,
840*5113495bSYour Name msdu_end->last_msdu,
841*5113495bSYour Name msdu_end->sa_idx,
842*5113495bSYour Name msdu_end->msdu_drop,
843*5113495bSYour Name msdu_end->reo_destination_indication,
844*5113495bSYour Name msdu_end->flow_idx,
845*5113495bSYour Name msdu_end->fse_metadata,
846*5113495bSYour Name msdu_end->cce_metadata,
847*5113495bSYour Name msdu_end->sa_sw_peer_id);
848*5113495bSYour Name }
849*5113495bSYour Name #else
hal_rx_dump_mpdu_start_tlv_9224(void * mpdustart,uint8_t dbg_level)850*5113495bSYour Name static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
851*5113495bSYour Name uint8_t dbg_level)
852*5113495bSYour Name {
853*5113495bSYour Name struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
854*5113495bSYour Name struct rx_mpdu_info *mpdu_info =
855*5113495bSYour Name (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
856*5113495bSYour Name
857*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
858*5113495bSYour Name "rx_mpdu_start tlv (1/5) - "
859*5113495bSYour Name "rx_reo_queue_desc_addr_31_0 :%x"
860*5113495bSYour Name "rx_reo_queue_desc_addr_39_32 :%x"
861*5113495bSYour Name "receive_queue_number:%x "
862*5113495bSYour Name "pre_delim_err_warning:%x "
863*5113495bSYour Name "first_delim_err:%x "
864*5113495bSYour Name "reserved_2a:%x "
865*5113495bSYour Name "pn_31_0:%x "
866*5113495bSYour Name "pn_63_32:%x "
867*5113495bSYour Name "pn_95_64:%x "
868*5113495bSYour Name "pn_127_96:%x "
869*5113495bSYour Name "epd_en:%x "
870*5113495bSYour Name "all_frames_shall_be_encrypted :%x"
871*5113495bSYour Name "encrypt_type:%x "
872*5113495bSYour Name "wep_key_width_for_variable_key :%x"
873*5113495bSYour Name "mesh_sta:%x "
874*5113495bSYour Name "bssid_hit:%x "
875*5113495bSYour Name "bssid_number:%x "
876*5113495bSYour Name "tid:%x "
877*5113495bSYour Name "reserved_7a:%x ",
878*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_31_0,
879*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_39_32,
880*5113495bSYour Name mpdu_info->receive_queue_number,
881*5113495bSYour Name mpdu_info->pre_delim_err_warning,
882*5113495bSYour Name mpdu_info->first_delim_err,
883*5113495bSYour Name mpdu_info->reserved_2a,
884*5113495bSYour Name mpdu_info->pn_31_0,
885*5113495bSYour Name mpdu_info->pn_63_32,
886*5113495bSYour Name mpdu_info->pn_95_64,
887*5113495bSYour Name mpdu_info->pn_127_96,
888*5113495bSYour Name mpdu_info->epd_en,
889*5113495bSYour Name mpdu_info->all_frames_shall_be_encrypted,
890*5113495bSYour Name mpdu_info->encrypt_type,
891*5113495bSYour Name mpdu_info->wep_key_width_for_variable_key,
892*5113495bSYour Name mpdu_info->mesh_sta,
893*5113495bSYour Name mpdu_info->bssid_hit,
894*5113495bSYour Name mpdu_info->bssid_number,
895*5113495bSYour Name mpdu_info->tid,
896*5113495bSYour Name mpdu_info->reserved_7a);
897*5113495bSYour Name
898*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
899*5113495bSYour Name "rx_mpdu_start tlv (2/5) - "
900*5113495bSYour Name "ast_index:%x "
901*5113495bSYour Name "sw_peer_id:%x "
902*5113495bSYour Name "mpdu_frame_control_valid:%x "
903*5113495bSYour Name "mpdu_duration_valid:%x "
904*5113495bSYour Name "mac_addr_ad1_valid:%x "
905*5113495bSYour Name "mac_addr_ad2_valid:%x "
906*5113495bSYour Name "mac_addr_ad3_valid:%x "
907*5113495bSYour Name "mac_addr_ad4_valid:%x "
908*5113495bSYour Name "mpdu_sequence_control_valid :%x"
909*5113495bSYour Name "mpdu_qos_control_valid:%x "
910*5113495bSYour Name "mpdu_ht_control_valid:%x "
911*5113495bSYour Name "frame_encryption_info_valid :%x",
912*5113495bSYour Name mpdu_info->ast_index,
913*5113495bSYour Name mpdu_info->sw_peer_id,
914*5113495bSYour Name mpdu_info->mpdu_frame_control_valid,
915*5113495bSYour Name mpdu_info->mpdu_duration_valid,
916*5113495bSYour Name mpdu_info->mac_addr_ad1_valid,
917*5113495bSYour Name mpdu_info->mac_addr_ad2_valid,
918*5113495bSYour Name mpdu_info->mac_addr_ad3_valid,
919*5113495bSYour Name mpdu_info->mac_addr_ad4_valid,
920*5113495bSYour Name mpdu_info->mpdu_sequence_control_valid,
921*5113495bSYour Name mpdu_info->mpdu_qos_control_valid,
922*5113495bSYour Name mpdu_info->mpdu_ht_control_valid,
923*5113495bSYour Name mpdu_info->frame_encryption_info_valid);
924*5113495bSYour Name
925*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
926*5113495bSYour Name "rx_mpdu_start tlv (3/5) - "
927*5113495bSYour Name "mpdu_fragment_number:%x "
928*5113495bSYour Name "more_fragment_flag:%x "
929*5113495bSYour Name "reserved_11a:%x "
930*5113495bSYour Name "fr_ds:%x "
931*5113495bSYour Name "to_ds:%x "
932*5113495bSYour Name "encrypted:%x "
933*5113495bSYour Name "mpdu_retry:%x "
934*5113495bSYour Name "mpdu_sequence_number:%x ",
935*5113495bSYour Name mpdu_info->mpdu_fragment_number,
936*5113495bSYour Name mpdu_info->more_fragment_flag,
937*5113495bSYour Name mpdu_info->reserved_11a,
938*5113495bSYour Name mpdu_info->fr_ds,
939*5113495bSYour Name mpdu_info->to_ds,
940*5113495bSYour Name mpdu_info->encrypted,
941*5113495bSYour Name mpdu_info->mpdu_retry,
942*5113495bSYour Name mpdu_info->mpdu_sequence_number);
943*5113495bSYour Name
944*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
945*5113495bSYour Name "rx_mpdu_start tlv (4/5) - "
946*5113495bSYour Name "mpdu_frame_control_field:%x "
947*5113495bSYour Name "mpdu_duration_field:%x ",
948*5113495bSYour Name mpdu_info->mpdu_frame_control_field,
949*5113495bSYour Name mpdu_info->mpdu_duration_field);
950*5113495bSYour Name
951*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
952*5113495bSYour Name "rx_mpdu_start tlv (5/5) - "
953*5113495bSYour Name "mac_addr_ad1_31_0:%x "
954*5113495bSYour Name "mac_addr_ad1_47_32:%x "
955*5113495bSYour Name "mac_addr_ad2_15_0:%x "
956*5113495bSYour Name "mac_addr_ad2_47_16:%x "
957*5113495bSYour Name "mac_addr_ad3_31_0:%x "
958*5113495bSYour Name "mac_addr_ad3_47_32:%x "
959*5113495bSYour Name "mpdu_sequence_control_field :%x"
960*5113495bSYour Name "mac_addr_ad4_31_0:%x "
961*5113495bSYour Name "mac_addr_ad4_47_32:%x "
962*5113495bSYour Name "mpdu_qos_control_field:%x ",
963*5113495bSYour Name mpdu_info->mac_addr_ad1_31_0,
964*5113495bSYour Name mpdu_info->mac_addr_ad1_47_32,
965*5113495bSYour Name mpdu_info->mac_addr_ad2_15_0,
966*5113495bSYour Name mpdu_info->mac_addr_ad2_47_16,
967*5113495bSYour Name mpdu_info->mac_addr_ad3_31_0,
968*5113495bSYour Name mpdu_info->mac_addr_ad3_47_32,
969*5113495bSYour Name mpdu_info->mpdu_sequence_control_field,
970*5113495bSYour Name mpdu_info->mac_addr_ad4_31_0,
971*5113495bSYour Name mpdu_info->mac_addr_ad4_47_32,
972*5113495bSYour Name mpdu_info->mpdu_qos_control_field);
973*5113495bSYour Name }
974*5113495bSYour Name
hal_rx_dump_msdu_end_tlv_9224(void * msduend,uint8_t dbg_level)975*5113495bSYour Name static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
976*5113495bSYour Name uint8_t dbg_level)
977*5113495bSYour Name {
978*5113495bSYour Name struct rx_msdu_end *msdu_end =
979*5113495bSYour Name (struct rx_msdu_end *)msduend;
980*5113495bSYour Name
981*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
982*5113495bSYour Name "rx_msdu_end tlv - "
983*5113495bSYour Name "key_id_octet: %d "
984*5113495bSYour Name "cce_super_rule: %d "
985*5113495bSYour Name "cce_classify_not_done_truncat: %d "
986*5113495bSYour Name "cce_classify_not_done_cce_dis: %d "
987*5113495bSYour Name "rule_indication_31_0: %d "
988*5113495bSYour Name "tcp_udp_chksum: %d "
989*5113495bSYour Name "sa_idx_timeout: %d "
990*5113495bSYour Name "da_idx_timeout: %d "
991*5113495bSYour Name "msdu_limit_error: %d "
992*5113495bSYour Name "flow_idx_timeout: %d "
993*5113495bSYour Name "flow_idx_invalid: %d "
994*5113495bSYour Name "wifi_parser_error: %d "
995*5113495bSYour Name "sa_is_valid: %d "
996*5113495bSYour Name "da_is_valid: %d "
997*5113495bSYour Name "da_is_mcbc: %d "
998*5113495bSYour Name "tkip_mic_err: %d "
999*5113495bSYour Name "l3_header_padding: %d "
1000*5113495bSYour Name "first_msdu: %d "
1001*5113495bSYour Name "last_msdu: %d "
1002*5113495bSYour Name "sa_idx: %d "
1003*5113495bSYour Name "msdu_drop: %d "
1004*5113495bSYour Name "reo_destination_indication: %d "
1005*5113495bSYour Name "flow_idx: %d "
1006*5113495bSYour Name "fse_metadata: %d "
1007*5113495bSYour Name "cce_metadata: %d "
1008*5113495bSYour Name "sa_sw_peer_id: %d ",
1009*5113495bSYour Name msdu_end->key_id_octet,
1010*5113495bSYour Name msdu_end->cce_super_rule,
1011*5113495bSYour Name msdu_end->cce_classify_not_done_truncate,
1012*5113495bSYour Name msdu_end->cce_classify_not_done_cce_dis,
1013*5113495bSYour Name msdu_end->rule_indication_31_0,
1014*5113495bSYour Name msdu_end->tcp_udp_chksum,
1015*5113495bSYour Name msdu_end->sa_idx_timeout,
1016*5113495bSYour Name msdu_end->da_idx_timeout,
1017*5113495bSYour Name msdu_end->msdu_limit_error,
1018*5113495bSYour Name msdu_end->flow_idx_timeout,
1019*5113495bSYour Name msdu_end->flow_idx_invalid,
1020*5113495bSYour Name msdu_end->wifi_parser_error,
1021*5113495bSYour Name msdu_end->sa_is_valid,
1022*5113495bSYour Name msdu_end->da_is_valid,
1023*5113495bSYour Name msdu_end->da_is_mcbc,
1024*5113495bSYour Name msdu_end->tkip_mic_err,
1025*5113495bSYour Name msdu_end->l3_header_padding,
1026*5113495bSYour Name msdu_end->first_msdu,
1027*5113495bSYour Name msdu_end->last_msdu,
1028*5113495bSYour Name msdu_end->sa_idx,
1029*5113495bSYour Name msdu_end->msdu_drop,
1030*5113495bSYour Name msdu_end->reo_destination_indication,
1031*5113495bSYour Name msdu_end->flow_idx,
1032*5113495bSYour Name msdu_end->fse_metadata,
1033*5113495bSYour Name msdu_end->cce_metadata,
1034*5113495bSYour Name msdu_end->sa_sw_peer_id);
1035*5113495bSYour Name }
1036*5113495bSYour Name #endif
1037*5113495bSYour Name
1038*5113495bSYour Name /**
1039*5113495bSYour Name * hal_reo_status_get_header_9224() - Process reo desc info
1040*5113495bSYour Name * @ring_desc: Pointer to reo descriptor
1041*5113495bSYour Name * @b: tlv type info
1042*5113495bSYour Name * @h1: Pointer to hal_reo_status_header where info to be stored
1043*5113495bSYour Name *
1044*5113495bSYour Name * Return: none.
1045*5113495bSYour Name *
1046*5113495bSYour Name */
hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc,int b,void * h1)1047*5113495bSYour Name static void hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc,
1048*5113495bSYour Name int b, void *h1)
1049*5113495bSYour Name {
1050*5113495bSYour Name uint64_t *d = (uint64_t *)ring_desc;
1051*5113495bSYour Name uint64_t val1 = 0;
1052*5113495bSYour Name struct hal_reo_status_header *h =
1053*5113495bSYour Name (struct hal_reo_status_header *)h1;
1054*5113495bSYour Name
1055*5113495bSYour Name /* Offsets of descriptor fields defined in HW headers start
1056*5113495bSYour Name * from the field after TLV header
1057*5113495bSYour Name */
1058*5113495bSYour Name d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
1059*5113495bSYour Name
1060*5113495bSYour Name switch (b) {
1061*5113495bSYour Name case HAL_REO_QUEUE_STATS_STATUS_TLV:
1062*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
1063*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
1064*5113495bSYour Name break;
1065*5113495bSYour Name case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1066*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
1067*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
1068*5113495bSYour Name break;
1069*5113495bSYour Name case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1070*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
1071*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
1072*5113495bSYour Name break;
1073*5113495bSYour Name case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1074*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
1075*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
1076*5113495bSYour Name break;
1077*5113495bSYour Name case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1078*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1079*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
1080*5113495bSYour Name break;
1081*5113495bSYour Name case HAL_REO_DESC_THRES_STATUS_TLV:
1082*5113495bSYour Name val1 =
1083*5113495bSYour Name d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1084*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
1085*5113495bSYour Name break;
1086*5113495bSYour Name case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1087*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
1088*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
1089*5113495bSYour Name break;
1090*5113495bSYour Name default:
1091*5113495bSYour Name qdf_nofl_err("ERROR: Unknown tlv\n");
1092*5113495bSYour Name break;
1093*5113495bSYour Name }
1094*5113495bSYour Name h->cmd_num =
1095*5113495bSYour Name HAL_GET_FIELD(
1096*5113495bSYour Name UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
1097*5113495bSYour Name val1);
1098*5113495bSYour Name h->exec_time =
1099*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
1100*5113495bSYour Name CMD_EXECUTION_TIME, val1);
1101*5113495bSYour Name h->status =
1102*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
1103*5113495bSYour Name REO_CMD_EXECUTION_STATUS, val1);
1104*5113495bSYour Name switch (b) {
1105*5113495bSYour Name case HAL_REO_QUEUE_STATS_STATUS_TLV:
1106*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
1107*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
1108*5113495bSYour Name break;
1109*5113495bSYour Name case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1110*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
1111*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
1112*5113495bSYour Name break;
1113*5113495bSYour Name case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1114*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
1115*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
1116*5113495bSYour Name break;
1117*5113495bSYour Name case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1118*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
1119*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
1120*5113495bSYour Name break;
1121*5113495bSYour Name case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1122*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1123*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
1124*5113495bSYour Name break;
1125*5113495bSYour Name case HAL_REO_DESC_THRES_STATUS_TLV:
1126*5113495bSYour Name val1 =
1127*5113495bSYour Name d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1128*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
1129*5113495bSYour Name break;
1130*5113495bSYour Name case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1131*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
1132*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
1133*5113495bSYour Name break;
1134*5113495bSYour Name default:
1135*5113495bSYour Name qdf_nofl_err("ERROR: Unknown tlv\n");
1136*5113495bSYour Name break;
1137*5113495bSYour Name }
1138*5113495bSYour Name h->tstamp =
1139*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
1140*5113495bSYour Name }
1141*5113495bSYour Name
1142*5113495bSYour Name static
hal_rx_msdu0_buffer_addr_lsb_9224(void * link_desc_va)1143*5113495bSYour Name void *hal_rx_msdu0_buffer_addr_lsb_9224(void *link_desc_va)
1144*5113495bSYour Name {
1145*5113495bSYour Name return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
1146*5113495bSYour Name }
1147*5113495bSYour Name
1148*5113495bSYour Name static
hal_rx_msdu_desc_info_ptr_get_9224(void * msdu0)1149*5113495bSYour Name void *hal_rx_msdu_desc_info_ptr_get_9224(void *msdu0)
1150*5113495bSYour Name {
1151*5113495bSYour Name return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
1152*5113495bSYour Name }
1153*5113495bSYour Name
1154*5113495bSYour Name static
hal_ent_mpdu_desc_info_9224(void * ent_ring_desc)1155*5113495bSYour Name void *hal_ent_mpdu_desc_info_9224(void *ent_ring_desc)
1156*5113495bSYour Name {
1157*5113495bSYour Name return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
1158*5113495bSYour Name }
1159*5113495bSYour Name
1160*5113495bSYour Name static
hal_dst_mpdu_desc_info_9224(void * dst_ring_desc)1161*5113495bSYour Name void *hal_dst_mpdu_desc_info_9224(void *dst_ring_desc)
1162*5113495bSYour Name {
1163*5113495bSYour Name return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
1164*5113495bSYour Name }
1165*5113495bSYour Name
1166*5113495bSYour Name /**
1167*5113495bSYour Name * hal_reo_config_9224() - Set reo config parameters
1168*5113495bSYour Name * @soc: hal soc handle
1169*5113495bSYour Name * @reg_val: value to be set
1170*5113495bSYour Name * @reo_params: reo parameters
1171*5113495bSYour Name *
1172*5113495bSYour Name * Return: void
1173*5113495bSYour Name */
1174*5113495bSYour Name static void
hal_reo_config_9224(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)1175*5113495bSYour Name hal_reo_config_9224(struct hal_soc *soc,
1176*5113495bSYour Name uint32_t reg_val,
1177*5113495bSYour Name struct hal_reo_params *reo_params)
1178*5113495bSYour Name {
1179*5113495bSYour Name HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
1180*5113495bSYour Name }
1181*5113495bSYour Name
1182*5113495bSYour Name /**
1183*5113495bSYour Name * hal_rx_msdu_desc_info_get_ptr_9224() - Get msdu desc info ptr
1184*5113495bSYour Name * @msdu_details_ptr: Pointer to msdu_details_ptr
1185*5113495bSYour Name *
1186*5113495bSYour Name * Return: Pointer to rx_msdu_desc_info structure.
1187*5113495bSYour Name *
1188*5113495bSYour Name */
hal_rx_msdu_desc_info_get_ptr_9224(void * msdu_details_ptr)1189*5113495bSYour Name static void *hal_rx_msdu_desc_info_get_ptr_9224(void *msdu_details_ptr)
1190*5113495bSYour Name {
1191*5113495bSYour Name return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
1192*5113495bSYour Name }
1193*5113495bSYour Name
1194*5113495bSYour Name /**
1195*5113495bSYour Name * hal_rx_link_desc_msdu0_ptr_9224() - Get pointer to rx_msdu details
1196*5113495bSYour Name * @link_desc: Pointer to link desc
1197*5113495bSYour Name *
1198*5113495bSYour Name * Return: Pointer to rx_msdu_details structure
1199*5113495bSYour Name *
1200*5113495bSYour Name */
hal_rx_link_desc_msdu0_ptr_9224(void * link_desc)1201*5113495bSYour Name static void *hal_rx_link_desc_msdu0_ptr_9224(void *link_desc)
1202*5113495bSYour Name {
1203*5113495bSYour Name return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
1204*5113495bSYour Name }
1205*5113495bSYour Name
1206*5113495bSYour Name /**
1207*5113495bSYour Name * hal_get_window_address_9224() - Function to get hp/tp address
1208*5113495bSYour Name * @hal_soc: Pointer to hal_soc
1209*5113495bSYour Name * @addr: address offset of register
1210*5113495bSYour Name *
1211*5113495bSYour Name * Return: modified address offset of register
1212*5113495bSYour Name */
1213*5113495bSYour Name
hal_get_window_address_9224(struct hal_soc * hal_soc,qdf_iomem_t addr)1214*5113495bSYour Name static inline qdf_iomem_t hal_get_window_address_9224(struct hal_soc *hal_soc,
1215*5113495bSYour Name qdf_iomem_t addr)
1216*5113495bSYour Name {
1217*5113495bSYour Name uint32_t offset = addr - hal_soc->dev_base_addr;
1218*5113495bSYour Name qdf_iomem_t new_offset;
1219*5113495bSYour Name
1220*5113495bSYour Name /*
1221*5113495bSYour Name * If offset lies within DP register range, use 3rd window to write
1222*5113495bSYour Name * into DP region.
1223*5113495bSYour Name */
1224*5113495bSYour Name if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) {
1225*5113495bSYour Name new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) +
1226*5113495bSYour Name (offset & WINDOW_RANGE_MASK));
1227*5113495bSYour Name /*
1228*5113495bSYour Name * If offset lies within CE register range, use 2nd window to write
1229*5113495bSYour Name * into CE region.
1230*5113495bSYour Name */
1231*5113495bSYour Name } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) {
1232*5113495bSYour Name new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) +
1233*5113495bSYour Name (offset & WINDOW_RANGE_MASK));
1234*5113495bSYour Name } else {
1235*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
1236*5113495bSYour Name "%s: ERROR: Accessing Wrong register\n", __func__);
1237*5113495bSYour Name qdf_assert_always(0);
1238*5113495bSYour Name return 0;
1239*5113495bSYour Name }
1240*5113495bSYour Name return new_offset;
1241*5113495bSYour Name }
1242*5113495bSYour Name
hal_write_window_register(struct hal_soc * hal_soc)1243*5113495bSYour Name static inline void hal_write_window_register(struct hal_soc *hal_soc)
1244*5113495bSYour Name {
1245*5113495bSYour Name /* Write value into window configuration register */
1246*5113495bSYour Name qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
1247*5113495bSYour Name WINDOW_CONFIGURATION_VALUE_9224);
1248*5113495bSYour Name }
1249*5113495bSYour Name
1250*5113495bSYour Name static
hal_compute_reo_remap_ix2_ix3_9224(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1251*5113495bSYour Name void hal_compute_reo_remap_ix2_ix3_9224(uint32_t *ring, uint32_t num_rings,
1252*5113495bSYour Name uint32_t *remap1, uint32_t *remap2)
1253*5113495bSYour Name {
1254*5113495bSYour Name switch (num_rings) {
1255*5113495bSYour Name case 1:
1256*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1257*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 17) |
1258*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 18) |
1259*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 19) |
1260*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
1261*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 21) |
1262*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 22) |
1263*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 23);
1264*5113495bSYour Name
1265*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1266*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
1267*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 26) |
1268*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 27) |
1269*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
1270*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 29) |
1271*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 30) |
1272*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 31);
1273*5113495bSYour Name break;
1274*5113495bSYour Name case 2:
1275*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1276*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 17) |
1277*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 18) |
1278*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 19) |
1279*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
1280*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 21) |
1281*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 22) |
1282*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 23);
1283*5113495bSYour Name
1284*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1285*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
1286*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 26) |
1287*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 27) |
1288*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
1289*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 29) |
1290*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 30) |
1291*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 31);
1292*5113495bSYour Name break;
1293*5113495bSYour Name case 3:
1294*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1295*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 17) |
1296*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 18) |
1297*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 19) |
1298*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 20) |
1299*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 21) |
1300*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 22) |
1301*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 23);
1302*5113495bSYour Name
1303*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1304*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
1305*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 26) |
1306*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 27) |
1307*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
1308*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 29) |
1309*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 30) |
1310*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 31);
1311*5113495bSYour Name break;
1312*5113495bSYour Name case 4:
1313*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1314*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 17) |
1315*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 18) |
1316*5113495bSYour Name HAL_REO_REMAP_IX2(ring[3], 19) |
1317*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
1318*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 21) |
1319*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 22) |
1320*5113495bSYour Name HAL_REO_REMAP_IX2(ring[3], 23);
1321*5113495bSYour Name
1322*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1323*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 25) |
1324*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 26) |
1325*5113495bSYour Name HAL_REO_REMAP_IX3(ring[3], 27) |
1326*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
1327*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 29) |
1328*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 30) |
1329*5113495bSYour Name HAL_REO_REMAP_IX3(ring[3], 31);
1330*5113495bSYour Name break;
1331*5113495bSYour Name }
1332*5113495bSYour Name }
1333*5113495bSYour Name
1334*5113495bSYour Name static
hal_compute_reo_remap_ix0_9224(struct hal_soc * soc)1335*5113495bSYour Name void hal_compute_reo_remap_ix0_9224(struct hal_soc *soc)
1336*5113495bSYour Name {
1337*5113495bSYour Name uint32_t remap0;
1338*5113495bSYour Name
1339*5113495bSYour Name remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1340*5113495bSYour Name (REO_REG_REG_BASE));
1341*5113495bSYour Name
1342*5113495bSYour Name remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6));
1343*5113495bSYour Name remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6);
1344*5113495bSYour Name
1345*5113495bSYour Name HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1346*5113495bSYour Name (REO_REG_REG_BASE), remap0);
1347*5113495bSYour Name
1348*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x",
1349*5113495bSYour Name HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1350*5113495bSYour Name (REO_REG_REG_BASE)));
1351*5113495bSYour Name }
1352*5113495bSYour Name
1353*5113495bSYour Name /**
1354*5113495bSYour Name * hal_rx_flow_setup_fse_9224() - Setup a flow search entry in HW FST
1355*5113495bSYour Name * @rx_fst: Pointer to the Rx Flow Search Table
1356*5113495bSYour Name * @table_offset: offset into the table where the flow is to be setup
1357*5113495bSYour Name * @rx_flow: Flow Parameters
1358*5113495bSYour Name *
1359*5113495bSYour Name * Return: Success/Failure
1360*5113495bSYour Name */
1361*5113495bSYour Name static void *
hal_rx_flow_setup_fse_9224(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1362*5113495bSYour Name hal_rx_flow_setup_fse_9224(uint8_t *rx_fst, uint32_t table_offset,
1363*5113495bSYour Name uint8_t *rx_flow)
1364*5113495bSYour Name {
1365*5113495bSYour Name struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1366*5113495bSYour Name struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1367*5113495bSYour Name uint8_t *fse;
1368*5113495bSYour Name bool fse_valid;
1369*5113495bSYour Name
1370*5113495bSYour Name if (table_offset >= fst->max_entries) {
1371*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1372*5113495bSYour Name "HAL FSE table offset %u exceeds max entries %u",
1373*5113495bSYour Name table_offset, fst->max_entries);
1374*5113495bSYour Name return NULL;
1375*5113495bSYour Name }
1376*5113495bSYour Name
1377*5113495bSYour Name fse = (uint8_t *)fst->base_vaddr +
1378*5113495bSYour Name (table_offset * HAL_RX_FST_ENTRY_SIZE);
1379*5113495bSYour Name
1380*5113495bSYour Name fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1381*5113495bSYour Name
1382*5113495bSYour Name if (fse_valid) {
1383*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1384*5113495bSYour Name "HAL FSE %pK already valid", fse);
1385*5113495bSYour Name return NULL;
1386*5113495bSYour Name }
1387*5113495bSYour Name
1388*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
1389*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
1390*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_127_96));
1391*5113495bSYour Name
1392*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
1393*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
1394*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_95_64));
1395*5113495bSYour Name
1396*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
1397*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
1398*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_63_32));
1399*5113495bSYour Name
1400*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
1401*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
1402*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_31_0));
1403*5113495bSYour Name
1404*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
1405*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
1406*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_127_96));
1407*5113495bSYour Name
1408*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
1409*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
1410*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_95_64));
1411*5113495bSYour Name
1412*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
1413*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
1414*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_63_32));
1415*5113495bSYour Name
1416*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
1417*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
1418*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_31_0));
1419*5113495bSYour Name
1420*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
1421*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
1422*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
1423*5113495bSYour Name (flow->tuple_info.dest_port));
1424*5113495bSYour Name
1425*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
1426*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
1427*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
1428*5113495bSYour Name (flow->tuple_info.src_port));
1429*5113495bSYour Name
1430*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
1431*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
1432*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
1433*5113495bSYour Name flow->tuple_info.l4_protocol);
1434*5113495bSYour Name
1435*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE);
1436*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE) |=
1437*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, USE_PPE, flow->use_ppe_ds);
1438*5113495bSYour Name
1439*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID);
1440*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID) |=
1441*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID,
1442*5113495bSYour Name flow->priority_vld);
1443*5113495bSYour Name
1444*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE);
1445*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE) |=
1446*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SERVICE_CODE,
1447*5113495bSYour Name flow->service_code);
1448*5113495bSYour Name
1449*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
1450*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
1451*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
1452*5113495bSYour Name flow->reo_destination_handler);
1453*5113495bSYour Name
1454*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1455*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
1456*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
1457*5113495bSYour Name
1458*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
1459*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
1460*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
1461*5113495bSYour Name flow->fse_metadata);
1462*5113495bSYour Name
1463*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
1464*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
1465*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
1466*5113495bSYour Name REO_DESTINATION_INDICATION,
1467*5113495bSYour Name flow->reo_destination_indication);
1468*5113495bSYour Name
1469*5113495bSYour Name /* Reset all the other fields in FSE */
1470*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
1471*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
1472*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
1473*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
1474*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
1475*5113495bSYour Name
1476*5113495bSYour Name return fse;
1477*5113495bSYour Name }
1478*5113495bSYour Name
1479*5113495bSYour Name /**
1480*5113495bSYour Name * hal_rx_dump_pkt_hdr_tlv_9224() - dump RX pkt header TLV in hex format
1481*5113495bSYour Name * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
1482*5113495bSYour Name * @dbg_level: log level.
1483*5113495bSYour Name *
1484*5113495bSYour Name * Return: void
1485*5113495bSYour Name */
1486*5113495bSYour Name #ifndef NO_RX_PKT_HDR_TLV
hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1487*5113495bSYour Name static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs,
1488*5113495bSYour Name uint8_t dbg_level)
1489*5113495bSYour Name {
1490*5113495bSYour Name struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
1491*5113495bSYour Name
1492*5113495bSYour Name hal_verbose_debug("\n---------------\n"
1493*5113495bSYour Name "rx_pkt_hdr_tlv\n"
1494*5113495bSYour Name "---------------\n"
1495*5113495bSYour Name "phy_ppdu_id 0x%x ",
1496*5113495bSYour Name pkt_hdr_tlv->phy_ppdu_id);
1497*5113495bSYour Name
1498*5113495bSYour Name hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
1499*5113495bSYour Name sizeof(pkt_hdr_tlv->rx_pkt_hdr));
1500*5113495bSYour Name }
1501*5113495bSYour Name #else
hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1502*5113495bSYour Name static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs,
1503*5113495bSYour Name uint8_t dbg_level)
1504*5113495bSYour Name {
1505*5113495bSYour Name }
1506*5113495bSYour Name #endif
1507*5113495bSYour Name
1508*5113495bSYour Name /**
1509*5113495bSYour Name * hal_tx_dump_ppe_vp_entry_9224() - API to print PPE VP entries
1510*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
1511*5113495bSYour Name *
1512*5113495bSYour Name * Return: void
1513*5113495bSYour Name */
1514*5113495bSYour Name static inline
hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl)1515*5113495bSYour Name void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl)
1516*5113495bSYour Name {
1517*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
1518*5113495bSYour Name uint32_t reg_addr, reg_val = 0, i;
1519*5113495bSYour Name
1520*5113495bSYour Name for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) {
1521*5113495bSYour Name reg_addr =
1522*5113495bSYour Name HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(
1523*5113495bSYour Name MAC_TCL_REG_REG_BASE,
1524*5113495bSYour Name i);
1525*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
1526*5113495bSYour Name hal_verbose_debug("%d: 0x%x\n", i, reg_val);
1527*5113495bSYour Name }
1528*5113495bSYour Name }
1529*5113495bSYour Name
1530*5113495bSYour Name /**
1531*5113495bSYour Name * hal_rx_dump_pkt_tlvs_9224() - API to print RX Pkt TLVS QCN9224
1532*5113495bSYour Name * @hal_soc_hdl: hal_soc handle
1533*5113495bSYour Name * @buf: pointer the pkt buffer
1534*5113495bSYour Name * @dbg_level: log level
1535*5113495bSYour Name *
1536*5113495bSYour Name * Return: void
1537*5113495bSYour Name */
1538*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1539*5113495bSYour Name static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
1540*5113495bSYour Name uint8_t *buf, uint8_t dbg_level)
1541*5113495bSYour Name {
1542*5113495bSYour Name struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1543*5113495bSYour Name struct rx_msdu_end_compact *msdu_end =
1544*5113495bSYour Name &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1545*5113495bSYour Name struct rx_mpdu_start_compact *mpdu_start =
1546*5113495bSYour Name &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1547*5113495bSYour Name
1548*5113495bSYour Name hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level);
1549*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level);
1550*5113495bSYour Name hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level);
1551*5113495bSYour Name }
1552*5113495bSYour Name #else
hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1553*5113495bSYour Name static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
1554*5113495bSYour Name uint8_t *buf, uint8_t dbg_level)
1555*5113495bSYour Name {
1556*5113495bSYour Name struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1557*5113495bSYour Name struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1558*5113495bSYour Name struct rx_mpdu_start *mpdu_start =
1559*5113495bSYour Name &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1560*5113495bSYour Name
1561*5113495bSYour Name hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level);
1562*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level);
1563*5113495bSYour Name hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level);
1564*5113495bSYour Name }
1565*5113495bSYour Name #endif
1566*5113495bSYour Name
1567*5113495bSYour Name #define HAL_NUM_TCL_BANKS_9224 48
1568*5113495bSYour Name
1569*5113495bSYour Name /**
1570*5113495bSYour Name * hal_cmem_write_9224() - function for CMEM buffer writing
1571*5113495bSYour Name * @hal_soc_hdl: HAL SOC handle
1572*5113495bSYour Name * @offset: CMEM address
1573*5113495bSYour Name * @value: value to write
1574*5113495bSYour Name *
1575*5113495bSYour Name * Return: None.
1576*5113495bSYour Name */
hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl,uint32_t offset,uint32_t value)1577*5113495bSYour Name static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl,
1578*5113495bSYour Name uint32_t offset,
1579*5113495bSYour Name uint32_t value)
1580*5113495bSYour Name {
1581*5113495bSYour Name struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
1582*5113495bSYour Name
1583*5113495bSYour Name pld_reg_write(hal->qdf_dev->dev, offset, value, NULL);
1584*5113495bSYour Name }
1585*5113495bSYour Name
1586*5113495bSYour Name /**
1587*5113495bSYour Name * hal_tx_get_num_tcl_banks_9224() - Get number of banks in target
1588*5113495bSYour Name *
1589*5113495bSYour Name * Return: number of bank
1590*5113495bSYour Name */
hal_tx_get_num_tcl_banks_9224(void)1591*5113495bSYour Name static uint8_t hal_tx_get_num_tcl_banks_9224(void)
1592*5113495bSYour Name {
1593*5113495bSYour Name return HAL_NUM_TCL_BANKS_9224;
1594*5113495bSYour Name }
1595*5113495bSYour Name
hal_reo_setup_9224(struct hal_soc * soc,void * reoparams,int qref_reset)1596*5113495bSYour Name static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams,
1597*5113495bSYour Name int qref_reset)
1598*5113495bSYour Name {
1599*5113495bSYour Name uint32_t reg_val;
1600*5113495bSYour Name struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
1601*5113495bSYour Name
1602*5113495bSYour Name reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
1603*5113495bSYour Name REO_REG_REG_BASE));
1604*5113495bSYour Name
1605*5113495bSYour Name hal_reo_config_9224(soc, reg_val, reo_params);
1606*5113495bSYour Name /* Other ring enable bits and REO_ENABLE will be set by FW */
1607*5113495bSYour Name
1608*5113495bSYour Name /* TODO: Setup destination ring mapping if enabled */
1609*5113495bSYour Name
1610*5113495bSYour Name /* TODO: Error destination ring setting is left to default.
1611*5113495bSYour Name * Default setting is to send all errors to release ring.
1612*5113495bSYour Name */
1613*5113495bSYour Name
1614*5113495bSYour Name /* Set the reo descriptor swap bits in case of BIG endian platform */
1615*5113495bSYour Name hal_setup_reo_swap(soc);
1616*5113495bSYour Name
1617*5113495bSYour Name HAL_REG_WRITE(soc,
1618*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
1619*5113495bSYour Name HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
1620*5113495bSYour Name
1621*5113495bSYour Name HAL_REG_WRITE(soc,
1622*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
1623*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1624*5113495bSYour Name
1625*5113495bSYour Name HAL_REG_WRITE(soc,
1626*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
1627*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1628*5113495bSYour Name
1629*5113495bSYour Name HAL_REG_WRITE(soc,
1630*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
1631*5113495bSYour Name (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
1632*5113495bSYour Name
1633*5113495bSYour Name /*
1634*5113495bSYour Name * When hash based routing is enabled, routing of the rx packet
1635*5113495bSYour Name * is done based on the following value: 1 _ _ _ _ The last 4
1636*5113495bSYour Name * bits are based on hash[3:0]. This means the possible values
1637*5113495bSYour Name * are 0x10 to 0x1f. This value is used to look-up the
1638*5113495bSYour Name * ring ID configured in Destination_Ring_Ctrl_IX_* register.
1639*5113495bSYour Name * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
1640*5113495bSYour Name * registers need to be configured to set-up the 16 entries to
1641*5113495bSYour Name * map the hash values to a ring number. There are 3 bits per
1642*5113495bSYour Name * hash entry which are mapped as follows:
1643*5113495bSYour Name * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
1644*5113495bSYour Name * 7: NOT_USED.
1645*5113495bSYour Name */
1646*5113495bSYour Name if (reo_params->rx_hash_enabled) {
1647*5113495bSYour Name hal_compute_reo_remap_ix0_9224(soc);
1648*5113495bSYour Name
1649*5113495bSYour Name HAL_REG_WRITE(soc,
1650*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
1651*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap0);
1652*5113495bSYour Name
1653*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1654*5113495bSYour Name HAL_REG_READ(soc,
1655*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
1656*5113495bSYour Name REO_REG_REG_BASE)));
1657*5113495bSYour Name
1658*5113495bSYour Name HAL_REG_WRITE(soc,
1659*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
1660*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap1);
1661*5113495bSYour Name
1662*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1663*5113495bSYour Name HAL_REG_READ(soc,
1664*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
1665*5113495bSYour Name REO_REG_REG_BASE)));
1666*5113495bSYour Name
1667*5113495bSYour Name HAL_REG_WRITE(soc,
1668*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
1669*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap2);
1670*5113495bSYour Name
1671*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
1672*5113495bSYour Name HAL_REG_READ(soc,
1673*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
1674*5113495bSYour Name REO_REG_REG_BASE)));
1675*5113495bSYour Name }
1676*5113495bSYour Name
1677*5113495bSYour Name /* TODO: Check if the following registers shoould be setup by host:
1678*5113495bSYour Name * AGING_CONTROL
1679*5113495bSYour Name * HIGH_MEMORY_THRESHOLD
1680*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
1681*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_CTRL
1682*5113495bSYour Name */
1683*5113495bSYour Name
1684*5113495bSYour Name soc->reo_qref = *reo_params->reo_qref;
1685*5113495bSYour Name hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
1686*5113495bSYour Name }
1687*5113495bSYour Name
hal_get_rx_max_ba_window_qcn9224(int tid)1688*5113495bSYour Name static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid)
1689*5113495bSYour Name {
1690*5113495bSYour Name return HAL_RX_BA_WINDOW_1024;
1691*5113495bSYour Name }
1692*5113495bSYour Name
1693*5113495bSYour Name /**
1694*5113495bSYour Name * hal_qcn9224_get_reo_qdesc_size() - Get the reo queue descriptor size from the
1695*5113495bSYour Name * given Block-Ack window size
1696*5113495bSYour Name * @ba_window_size: Block-Ack window size
1697*5113495bSYour Name * @tid: Traffic id
1698*5113495bSYour Name *
1699*5113495bSYour Name * Return: reo queue descriptor size
1700*5113495bSYour Name */
hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size,int tid)1701*5113495bSYour Name static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
1702*5113495bSYour Name {
1703*5113495bSYour Name /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
1704*5113495bSYour Name * NON_QOS_TID until HW issues are resolved.
1705*5113495bSYour Name */
1706*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
1707*5113495bSYour Name ba_window_size = hal_get_rx_max_ba_window_qcn9224(tid);
1708*5113495bSYour Name
1709*5113495bSYour Name /* Return descriptor size corresponding to window size of 2 since
1710*5113495bSYour Name * we set ba_window_size to 2 while setting up REO descriptors as
1711*5113495bSYour Name * a WAR to get 2k jump exception aggregates are received without
1712*5113495bSYour Name * a BA session.
1713*5113495bSYour Name */
1714*5113495bSYour Name if (ba_window_size <= 1) {
1715*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
1716*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1717*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
1718*5113495bSYour Name else
1719*5113495bSYour Name return sizeof(struct rx_reo_queue);
1720*5113495bSYour Name }
1721*5113495bSYour Name
1722*5113495bSYour Name if (ba_window_size <= 105)
1723*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1724*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
1725*5113495bSYour Name
1726*5113495bSYour Name if (ba_window_size <= 210)
1727*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1728*5113495bSYour Name (2 * sizeof(struct rx_reo_queue_ext));
1729*5113495bSYour Name
1730*5113495bSYour Name if (ba_window_size <= 256)
1731*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1732*5113495bSYour Name (3 * sizeof(struct rx_reo_queue_ext));
1733*5113495bSYour Name
1734*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1735*5113495bSYour Name (10 * sizeof(struct rx_reo_queue_ext)) +
1736*5113495bSYour Name sizeof(struct rx_reo_queue_1k);
1737*5113495bSYour Name }
1738*5113495bSYour Name
1739*5113495bSYour Name /**
1740*5113495bSYour Name * hal_tx_get_num_ppe_vp_tbl_entries_9224() - get number of PPE VP entries
1741*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
1742*5113495bSYour Name *
1743*5113495bSYour Name * Return: Number of PPE VP entries
1744*5113495bSYour Name */
1745*5113495bSYour Name static
hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl)1746*5113495bSYour Name uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl)
1747*5113495bSYour Name {
1748*5113495bSYour Name return HAL_PPE_VP_ENTRIES_MAX;
1749*5113495bSYour Name }
1750*5113495bSYour Name
1751*5113495bSYour Name /**
1752*5113495bSYour Name * hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224() - get number of PPE VP
1753*5113495bSYour Name * search index registers
1754*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
1755*5113495bSYour Name *
1756*5113495bSYour Name * Return: Number of PPE VP search index registers
1757*5113495bSYour Name */
1758*5113495bSYour Name static
hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224(hal_soc_handle_t hal_soc_hdl)1759*5113495bSYour Name uint32_t hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224(hal_soc_handle_t hal_soc_hdl)
1760*5113495bSYour Name {
1761*5113495bSYour Name return HAL_PPE_VP_SEARCH_IDX_REG_MAX;
1762*5113495bSYour Name }
1763*5113495bSYour Name
1764*5113495bSYour Name /**
1765*5113495bSYour Name * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv
1766*5113495bSYour Name * @buf: pointer the RX TLV
1767*5113495bSYour Name *
1768*5113495bSYour Name * Return: msdu done copy bit
1769*5113495bSYour Name */
hal_rx_tlv_msdu_done_copy_get_9224(uint8_t * buf)1770*5113495bSYour Name static inline uint32_t hal_rx_tlv_msdu_done_copy_get_9224(uint8_t *buf)
1771*5113495bSYour Name {
1772*5113495bSYour Name return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
1773*5113495bSYour Name }
1774*5113495bSYour Name
hal_hw_txrx_ops_attach_qcn9224(struct hal_soc * hal_soc)1775*5113495bSYour Name static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
1776*5113495bSYour Name {
1777*5113495bSYour Name /* init and setup */
1778*5113495bSYour Name hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1779*5113495bSYour Name hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1780*5113495bSYour Name hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic;
1781*5113495bSYour Name hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1782*5113495bSYour Name hal_soc->ops->hal_get_window_address = hal_get_window_address_9224;
1783*5113495bSYour Name hal_soc->ops->hal_cmem_write = hal_cmem_write_9224;
1784*5113495bSYour Name
1785*5113495bSYour Name /* tx */
1786*5113495bSYour Name hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224;
1787*5113495bSYour Name hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224;
1788*5113495bSYour Name hal_soc->ops->hal_tx_comp_get_status =
1789*5113495bSYour Name hal_tx_comp_get_status_generic_be;
1790*5113495bSYour Name hal_soc->ops->hal_tx_init_cmd_credit_ring =
1791*5113495bSYour Name hal_tx_init_cmd_credit_ring_9224;
1792*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_cmn_cfg =
1793*5113495bSYour Name hal_tx_set_ppe_cmn_config_9224;
1794*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_vp_entry =
1795*5113495bSYour Name hal_tx_set_ppe_vp_entry_9224;
1796*5113495bSYour Name hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg =
1797*5113495bSYour Name hal_ppeds_cfg_ast_override_map_reg_9224;
1798*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_pri2tid =
1799*5113495bSYour Name hal_tx_set_ppe_pri2tid_map_9224;
1800*5113495bSYour Name hal_soc->ops->hal_tx_update_ppe_pri2tid =
1801*5113495bSYour Name hal_tx_update_ppe_pri2tid_9224;
1802*5113495bSYour Name hal_soc->ops->hal_tx_dump_ppe_vp_entry =
1803*5113495bSYour Name hal_tx_dump_ppe_vp_entry_9224;
1804*5113495bSYour Name hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries =
1805*5113495bSYour Name hal_tx_get_num_ppe_vp_tbl_entries_9224;
1806*5113495bSYour Name hal_soc->ops->hal_tx_enable_pri2tid_map =
1807*5113495bSYour Name hal_tx_enable_pri2tid_map_9224;
1808*5113495bSYour Name hal_soc->ops->hal_tx_config_rbm_mapping_be =
1809*5113495bSYour Name hal_tx_config_rbm_mapping_be_9224;
1810*5113495bSYour Name
1811*5113495bSYour Name /* rx */
1812*5113495bSYour Name hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
1813*5113495bSYour Name hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1814*5113495bSYour Name hal_rx_mon_hw_desc_get_mpdu_status_be;
1815*5113495bSYour Name hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224;
1816*5113495bSYour Name hal_soc->ops->hal_rx_parse_eht_sig_hdr =
1817*5113495bSYour Name hal_rx_parse_eht_sig_hdr_9224;
1818*5113495bSYour Name hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1819*5113495bSYour Name hal_rx_proc_phyrx_other_receive_info_tlv_9224;
1820*5113495bSYour Name
1821*5113495bSYour Name hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9224;
1822*5113495bSYour Name hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1823*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_9224;
1824*5113495bSYour Name hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_9224;
1825*5113495bSYour Name
1826*5113495bSYour Name hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9224;
1827*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
1828*5113495bSYour Name hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1829*5113495bSYour Name hal_rx_tlv_reception_type_get_be;
1830*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1831*5113495bSYour Name hal_rx_msdu_end_da_idx_get_be;
1832*5113495bSYour Name hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1833*5113495bSYour Name hal_rx_msdu_desc_info_get_ptr_9224;
1834*5113495bSYour Name hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1835*5113495bSYour Name hal_rx_link_desc_msdu0_ptr_9224;
1836*5113495bSYour Name hal_soc->ops->hal_reo_status_get_header =
1837*5113495bSYour Name hal_reo_status_get_header_9224;
1838*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_RX_2_0
1839*5113495bSYour Name hal_soc->ops->hal_rx_status_get_tlv_info =
1840*5113495bSYour Name hal_rx_status_get_tlv_info_wrapper_be;
1841*5113495bSYour Name #endif
1842*5113495bSYour Name hal_soc->ops->hal_rx_wbm_err_info_get =
1843*5113495bSYour Name hal_rx_wbm_err_info_get_generic_be;
1844*5113495bSYour Name hal_soc->ops->hal_tx_set_pcp_tid_map =
1845*5113495bSYour Name hal_tx_set_pcp_tid_map_generic_be;
1846*5113495bSYour Name hal_soc->ops->hal_tx_update_pcp_tid_map =
1847*5113495bSYour Name hal_tx_update_pcp_tid_generic_be;
1848*5113495bSYour Name hal_soc->ops->hal_tx_set_tidmap_prty =
1849*5113495bSYour Name hal_tx_update_tidmap_prty_generic_be;
1850*5113495bSYour Name hal_soc->ops->hal_rx_get_rx_fragment_number =
1851*5113495bSYour Name hal_rx_get_rx_fragment_number_be,
1852*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1853*5113495bSYour Name hal_rx_tlv_da_is_mcbc_get_be;
1854*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
1855*5113495bSYour Name hal_rx_tlv_is_tkip_mic_err_get_be;
1856*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1857*5113495bSYour Name hal_rx_tlv_sa_is_valid_get_be;
1858*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
1859*5113495bSYour Name hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
1860*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1861*5113495bSYour Name hal_rx_tlv_l3_hdr_padding_get_be;
1862*5113495bSYour Name hal_soc->ops->hal_rx_encryption_info_valid =
1863*5113495bSYour Name hal_rx_encryption_info_valid_be;
1864*5113495bSYour Name hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
1865*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1866*5113495bSYour Name hal_rx_tlv_first_msdu_get_be;
1867*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1868*5113495bSYour Name hal_rx_tlv_da_is_valid_get_be;
1869*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1870*5113495bSYour Name hal_rx_tlv_last_msdu_get_be;
1871*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1872*5113495bSYour Name hal_rx_get_mpdu_mac_ad4_valid_be;
1873*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1874*5113495bSYour Name hal_rx_mpdu_start_sw_peer_id_get_be;
1875*5113495bSYour Name hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1876*5113495bSYour Name hal_rx_msdu_peer_meta_data_get_be;
1877*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
1878*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
1879*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1880*5113495bSYour Name hal_rx_get_mpdu_frame_control_valid_be;
1881*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
1882*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
1883*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
1884*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1885*5113495bSYour Name hal_rx_get_mpdu_sequence_control_valid_be;
1886*5113495bSYour Name hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
1887*5113495bSYour Name hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
1888*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1889*5113495bSYour Name hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
1890*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1891*5113495bSYour Name hal_rx_msdu_end_sa_sw_peer_id_get_be;
1892*5113495bSYour Name hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1893*5113495bSYour Name hal_rx_msdu0_buffer_addr_lsb_9224;
1894*5113495bSYour Name hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1895*5113495bSYour Name hal_rx_msdu_desc_info_ptr_get_9224;
1896*5113495bSYour Name hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9224;
1897*5113495bSYour Name hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9224;
1898*5113495bSYour Name hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
1899*5113495bSYour Name hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
1900*5113495bSYour Name hal_soc->ops->hal_rx_get_mac_addr2_valid =
1901*5113495bSYour Name hal_rx_get_mac_addr2_valid_be;
1902*5113495bSYour Name hal_soc->ops->hal_reo_config = hal_reo_config_9224;
1903*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
1904*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1905*5113495bSYour Name hal_rx_msdu_flow_idx_invalid_be;
1906*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1907*5113495bSYour Name hal_rx_msdu_flow_idx_timeout_be;
1908*5113495bSYour Name hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1909*5113495bSYour Name hal_rx_msdu_fse_metadata_get_be;
1910*5113495bSYour Name hal_soc->ops->hal_rx_msdu_cce_match_get =
1911*5113495bSYour Name hal_rx_msdu_cce_match_get_be;
1912*5113495bSYour Name hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1913*5113495bSYour Name hal_rx_msdu_cce_metadata_get_be;
1914*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_flow_params =
1915*5113495bSYour Name hal_rx_msdu_get_flow_params_be;
1916*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
1917*5113495bSYour Name hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
1918*5113495bSYour Name
1919*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
1920*5113495bSYour Name hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9224;
1921*5113495bSYour Name hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9224;
1922*5113495bSYour Name #else
1923*5113495bSYour Name hal_soc->ops->hal_rx_get_bb_info = NULL;
1924*5113495bSYour Name hal_soc->ops->hal_rx_get_rtt_info = NULL;
1925*5113495bSYour Name #endif
1926*5113495bSYour Name
1927*5113495bSYour Name /* rx - msdu fast path info fields */
1928*5113495bSYour Name hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1929*5113495bSYour Name hal_rx_msdu_packet_metadata_get_generic_be;
1930*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1931*5113495bSYour Name hal_rx_mpdu_start_tlv_tag_valid_be;
1932*5113495bSYour Name hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
1933*5113495bSYour Name hal_rx_wbm_err_msdu_continuation_get_9224;
1934*5113495bSYour Name
1935*5113495bSYour Name /* rx - TLV struct offsets */
1936*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_offset_get =
1937*5113495bSYour Name hal_rx_msdu_end_offset_get_generic;
1938*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_offset_get =
1939*5113495bSYour Name hal_rx_mpdu_start_offset_get_generic;
1940*5113495bSYour Name #ifndef NO_RX_PKT_HDR_TLV
1941*5113495bSYour Name hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1942*5113495bSYour Name hal_rx_pkt_tlv_offset_get_generic;
1943*5113495bSYour Name #endif
1944*5113495bSYour Name hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9224;
1945*5113495bSYour Name
1946*5113495bSYour Name hal_soc->ops->hal_rx_flow_get_tuple_info =
1947*5113495bSYour Name hal_rx_flow_get_tuple_info_be;
1948*5113495bSYour Name hal_soc->ops->hal_rx_flow_delete_entry =
1949*5113495bSYour Name hal_rx_flow_delete_entry_be;
1950*5113495bSYour Name hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
1951*5113495bSYour Name hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1952*5113495bSYour Name hal_compute_reo_remap_ix2_ix3_9224;
1953*5113495bSYour Name
1954*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
1955*5113495bSYour Name hal_rx_msdu_get_reo_destination_indication_be;
1956*5113495bSYour Name hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
1957*5113495bSYour Name hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
1958*5113495bSYour Name hal_rx_msdu_is_wlan_mcast_generic_be;
1959*5113495bSYour Name hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_9224;
1960*5113495bSYour Name hal_soc->ops->hal_rx_tlv_decap_format_get =
1961*5113495bSYour Name hal_rx_tlv_decap_format_get_be;
1962*5113495bSYour Name #ifdef RECEIVE_OFFLOAD
1963*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_offload_info =
1964*5113495bSYour Name hal_rx_tlv_get_offload_info_be;
1965*5113495bSYour Name hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
1966*5113495bSYour Name hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
1967*5113495bSYour Name #endif
1968*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_done_get =
1969*5113495bSYour Name hal_rx_tlv_msdu_done_copy_get_9224;
1970*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_len_get =
1971*5113495bSYour Name hal_rx_msdu_start_msdu_len_get_be;
1972*5113495bSYour Name hal_soc->ops->hal_rx_get_frame_ctrl_field =
1973*5113495bSYour Name hal_rx_get_frame_ctrl_field_be;
1974*5113495bSYour Name hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
1975*5113495bSYour Name #ifndef CONFIG_WORD_BASED_TLV
1976*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1977*5113495bSYour Name hal_rx_mpdu_info_ampdu_flag_get_be;
1978*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
1979*5113495bSYour Name hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1980*5113495bSYour Name hal_rx_hw_desc_get_ppduid_get_be;
1981*5113495bSYour Name hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
1982*5113495bSYour Name hal_rx_attn_phy_ppdu_id_get_be;
1983*5113495bSYour Name hal_soc->ops->hal_rx_get_filter_category =
1984*5113495bSYour Name hal_rx_get_filter_category_be;
1985*5113495bSYour Name #endif
1986*5113495bSYour Name hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
1987*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_len_set =
1988*5113495bSYour Name hal_rx_msdu_start_msdu_len_set_be;
1989*5113495bSYour Name hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
1990*5113495bSYour Name hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
1991*5113495bSYour Name hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
1992*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
1993*5113495bSYour Name hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
1994*5113495bSYour Name hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1995*5113495bSYour Name hal_rx_tlv_decrypt_err_get_be;
1996*5113495bSYour Name hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
1997*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_is_decrypted =
1998*5113495bSYour Name hal_rx_tlv_get_is_decrypted_be;
1999*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
2000*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
2001*5113495bSYour Name hal_soc->ops->hal_rx_priv_info_set_in_tlv =
2002*5113495bSYour Name hal_rx_priv_info_set_in_tlv_be;
2003*5113495bSYour Name hal_soc->ops->hal_rx_priv_info_get_from_tlv =
2004*5113495bSYour Name hal_rx_priv_info_get_from_tlv_be;
2005*5113495bSYour Name hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
2006*5113495bSYour Name hal_soc->ops->hal_reo_setup = hal_reo_setup_9224;
2007*5113495bSYour Name hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL;
2008*5113495bSYour Name #ifdef REO_SHARED_QREF_TABLE_EN
2009*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
2010*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
2011*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
2012*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
2013*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
2014*5113495bSYour Name #endif
2015*5113495bSYour Name /* Overwrite the default BE ops */
2016*5113495bSYour Name hal_soc->ops->hal_get_rx_max_ba_window =
2017*5113495bSYour Name hal_get_rx_max_ba_window_qcn9224;
2018*5113495bSYour Name hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn9224_get_reo_qdesc_size;
2019*5113495bSYour Name /* TX MONITOR */
2020*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_TX_2_0
2021*5113495bSYour Name hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
2022*5113495bSYour Name hal_txmon_is_mon_buf_addr_tlv_generic_be;
2023*5113495bSYour Name hal_soc->ops->hal_txmon_populate_packet_info =
2024*5113495bSYour Name hal_txmon_populate_packet_info_generic_be;
2025*5113495bSYour Name hal_soc->ops->hal_txmon_status_parse_tlv =
2026*5113495bSYour Name hal_txmon_status_parse_tlv_generic_be;
2027*5113495bSYour Name hal_soc->ops->hal_txmon_status_get_num_users =
2028*5113495bSYour Name hal_txmon_status_get_num_users_generic_be;
2029*5113495bSYour Name #if defined(TX_MONITOR_WORD_MASK)
2030*5113495bSYour Name hal_soc->ops->hal_txmon_get_word_mask =
2031*5113495bSYour Name hal_txmon_get_word_mask_qcn9224;
2032*5113495bSYour Name #else
2033*5113495bSYour Name hal_soc->ops->hal_txmon_get_word_mask =
2034*5113495bSYour Name hal_txmon_get_word_mask_generic_be;
2035*5113495bSYour Name #endif /* TX_MONITOR_WORD_MASK */
2036*5113495bSYour Name #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
2037*5113495bSYour Name hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
2038*5113495bSYour Name hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
2039*5113495bSYour Name hal_tx_vdev_mismatch_routing_set_generic_be;
2040*5113495bSYour Name hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
2041*5113495bSYour Name hal_tx_mcast_mlo_reinject_routing_set_generic_be;
2042*5113495bSYour Name hal_soc->ops->hal_get_ba_aging_timeout =
2043*5113495bSYour Name hal_get_ba_aging_timeout_be_generic;
2044*5113495bSYour Name hal_soc->ops->hal_setup_link_idle_list =
2045*5113495bSYour Name hal_setup_link_idle_list_generic_be;
2046*5113495bSYour Name hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
2047*5113495bSYour Name hal_cookie_conversion_reg_cfg_generic_be;
2048*5113495bSYour Name hal_soc->ops->hal_set_ba_aging_timeout =
2049*5113495bSYour Name hal_set_ba_aging_timeout_be_generic;
2050*5113495bSYour Name hal_soc->ops->hal_tx_populate_bank_register =
2051*5113495bSYour Name hal_tx_populate_bank_register_be;
2052*5113495bSYour Name hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
2053*5113495bSYour Name hal_tx_vdev_mcast_ctrl_set_be;
2054*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
2055*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_wmask_get =
2056*5113495bSYour Name hal_rx_mpdu_start_wmask_get_be;
2057*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_wmask_get =
2058*5113495bSYour Name hal_rx_msdu_end_wmask_get_be;
2059*5113495bSYour Name #endif
2060*5113495bSYour Name hal_soc->ops->hal_get_tsf2_scratch_reg =
2061*5113495bSYour Name hal_get_tsf2_scratch_reg_qcn9224;
2062*5113495bSYour Name hal_soc->ops->hal_get_tqm_scratch_reg =
2063*5113495bSYour Name hal_get_tqm_scratch_reg_qcn9224;
2064*5113495bSYour Name hal_soc->ops->hal_tx_ring_halt_set = hal_tx_ppe2tcl_ring_halt_set_9224;
2065*5113495bSYour Name hal_soc->ops->hal_tx_ring_halt_reset =
2066*5113495bSYour Name hal_tx_ppe2tcl_ring_halt_reset_9224;
2067*5113495bSYour Name hal_soc->ops->hal_tx_ring_halt_poll =
2068*5113495bSYour Name hal_tx_ppe2tcl_ring_halt_done_9224;
2069*5113495bSYour Name hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries =
2070*5113495bSYour Name hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224;
2071*5113495bSYour Name hal_soc->ops->hal_tx_ring_halt_get = hal_tx_ppe2tcl_ring_halt_get_9224;
2072*5113495bSYour Name };
2073*5113495bSYour Name
2074*5113495bSYour Name /**
2075*5113495bSYour Name * hal_srng_hw_reg_offset_init_qcn9224() - Initialize the HW srng reg offset
2076*5113495bSYour Name * applicable only for QCN9224
2077*5113495bSYour Name * @hal_soc: HAL Soc handle
2078*5113495bSYour Name *
2079*5113495bSYour Name * Return: None
2080*5113495bSYour Name */
hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc * hal_soc)2081*5113495bSYour Name static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc)
2082*5113495bSYour Name {
2083*5113495bSYour Name int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
2084*5113495bSYour Name
2085*5113495bSYour Name hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
2086*5113495bSYour Name hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
2087*5113495bSYour Name hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
2088*5113495bSYour Name hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
2089*5113495bSYour Name REG_OFFSET(DST, PRODUCER_INT2_SETUP);
2090*5113495bSYour Name }
2091