1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name #ifndef _HAL_9224_RX_H_ 21*5113495bSYour Name #define _HAL_9224_RX_H_ 22*5113495bSYour Name #include "qdf_util.h" 23*5113495bSYour Name #include "qdf_types.h" 24*5113495bSYour Name #include "qdf_lock.h" 25*5113495bSYour Name #include "qdf_mem.h" 26*5113495bSYour Name #include "qdf_nbuf.h" 27*5113495bSYour Name #include "tcl_data_cmd.h" 28*5113495bSYour Name #include "phyrx_rssi_legacy.h" 29*5113495bSYour Name #include "rx_msdu_start.h" 30*5113495bSYour Name #include "tlv_tag_def.h" 31*5113495bSYour Name #include "hal_hw_headers.h" 32*5113495bSYour Name #include "hal_internal.h" 33*5113495bSYour Name #include "cdp_txrx_mon_struct.h" 34*5113495bSYour Name #include "qdf_trace.h" 35*5113495bSYour Name #include "hal_rx.h" 36*5113495bSYour Name #include "hal_tx.h" 37*5113495bSYour Name #include "dp_types.h" 38*5113495bSYour Name #include "hal_api_mon.h" 39*5113495bSYour Name #include "phyrx_other_receive_info_ru_details.h" 40*5113495bSYour Name #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) 41*5113495bSYour Name #include "phyrx_other_receive_info_evm_details.h" 42*5113495bSYour Name #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 43*5113495bSYour Name 44*5113495bSYour Name #include "phyrx_other_receive_info_all_sigb_details.h" 45*5113495bSYour Name 46*5113495bSYour Name #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 47*5113495bSYour Name (uint8_t *)(link_desc_va) + \ 48*5113495bSYour Name RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 49*5113495bSYour Name 50*5113495bSYour Name #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 51*5113495bSYour Name (uint8_t *)(msdu0) + \ 52*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 53*5113495bSYour Name 54*5113495bSYour Name #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 55*5113495bSYour Name (uint8_t *)(ent_ring_desc) + \ 56*5113495bSYour Name RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 57*5113495bSYour Name 58*5113495bSYour Name #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 59*5113495bSYour Name (uint8_t *)(dst_ring_desc) + \ 60*5113495bSYour Name REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 61*5113495bSYour Name 62*5113495bSYour Name #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 63*5113495bSYour Name HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID) 64*5113495bSYour Name 65*5113495bSYour Name #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 66*5113495bSYour Name HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID) 67*5113495bSYour Name 68*5113495bSYour Name /* 69*5113495bSYour Name * In Beryllium chipset msdu_start was removed and merged in msdu_end. 70*5113495bSYour Name * Due to this valid contents will be present only in last msdu. 71*5113495bSYour Name * After setting the 5th bit of spare control field, REO will copy the contents 72*5113495bSYour Name * from last buffer to all the other buffers of MSDU. 73*5113495bSYour Name */ 74*5113495bSYour Name #define HAL_REO_MSDU_END_COPY 0x20 75*5113495bSYour Name #define HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 76*5113495bSYour Name 77*5113495bSYour Name #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 78*5113495bSYour Name do { \ 79*5113495bSYour Name reg_val &= \ 80*5113495bSYour Name ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 81*5113495bSYour Name HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 82*5113495bSYour Name reg_val |= \ 83*5113495bSYour Name HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 84*5113495bSYour Name AGING_LIST_ENABLE, 1) | \ 85*5113495bSYour Name HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 86*5113495bSYour Name AGING_FLUSH_ENABLE, 1); \ 87*5113495bSYour Name HAL_REG_WRITE(soc, \ 88*5113495bSYour Name HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 89*5113495bSYour Name REO_REG_REG_BASE), \ 90*5113495bSYour Name reg_val); \ 91*5113495bSYour Name reg_val = HAL_REG_READ(soc, \ 92*5113495bSYour Name HWIO_REO_R0_MISC_CTL_ADDR( \ 93*5113495bSYour Name REO_REG_REG_BASE)); \ 94*5113495bSYour Name reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 95*5113495bSYour Name reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \ 96*5113495bSYour Name FRAGMENT_DEST_RING, \ 97*5113495bSYour Name (reo_params)->frag_dst_ring); \ 98*5113495bSYour Name reg_val |= ((HAL_REO_MSDU_END_COPY) << \ 99*5113495bSYour Name HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT); \ 100*5113495bSYour Name HAL_REG_WRITE(soc, \ 101*5113495bSYour Name HWIO_REO_R0_MISC_CTL_ADDR( \ 102*5113495bSYour Name REO_REG_REG_BASE), \ 103*5113495bSYour Name reg_val); \ 104*5113495bSYour Name } while (0) 105*5113495bSYour Name 106*5113495bSYour Name #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 107*5113495bSYour Name ((struct rx_msdu_desc_info *) \ 108*5113495bSYour Name _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 109*5113495bSYour Name UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 110*5113495bSYour Name 111*5113495bSYour Name #define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \ 112*5113495bSYour Name HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy 113*5113495bSYour Name 114*5113495bSYour Name #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 115*5113495bSYour Name ((struct rx_msdu_details *) \ 116*5113495bSYour Name _OFFSET_TO_BYTE_PTR((link_desc),\ 117*5113495bSYour Name RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 118*5113495bSYour Name 119*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 120*5113495bSYour Name #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006 121*5113495bSYour Name #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1 122*5113495bSYour Name #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2 123*5113495bSYour Name 124*5113495bSYour Name #define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \ 125*5113495bSYour Name ((HAL_RX_GET_64((rx_tlv), \ 126*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \ 127*5113495bSYour Name RTT_CFR_STATUS) & \ 128*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \ 129*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB) 130*5113495bSYour Name #endif 131*5113495bSYour Name #endif 132