1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_9224_RX_H_ 21 #define _HAL_9224_RX_H_ 22 #include "qdf_util.h" 23 #include "qdf_types.h" 24 #include "qdf_lock.h" 25 #include "qdf_mem.h" 26 #include "qdf_nbuf.h" 27 #include "tcl_data_cmd.h" 28 #include "phyrx_rssi_legacy.h" 29 #include "rx_msdu_start.h" 30 #include "tlv_tag_def.h" 31 #include "hal_hw_headers.h" 32 #include "hal_internal.h" 33 #include "cdp_txrx_mon_struct.h" 34 #include "qdf_trace.h" 35 #include "hal_rx.h" 36 #include "hal_tx.h" 37 #include "dp_types.h" 38 #include "hal_api_mon.h" 39 #include "phyrx_other_receive_info_ru_details.h" 40 #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) 41 #include "phyrx_other_receive_info_evm_details.h" 42 #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 43 44 #include "phyrx_other_receive_info_all_sigb_details.h" 45 46 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 47 (uint8_t *)(link_desc_va) + \ 48 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 49 50 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 51 (uint8_t *)(msdu0) + \ 52 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 53 54 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 55 (uint8_t *)(ent_ring_desc) + \ 56 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 57 58 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 59 (uint8_t *)(dst_ring_desc) + \ 60 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 61 62 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 63 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID) 64 65 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 66 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID) 67 68 /* 69 * In Beryllium chipset msdu_start was removed and merged in msdu_end. 70 * Due to this valid contents will be present only in last msdu. 71 * After setting the 5th bit of spare control field, REO will copy the contents 72 * from last buffer to all the other buffers of MSDU. 73 */ 74 #define HAL_REO_MSDU_END_COPY 0x20 75 #define HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 76 77 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 78 do { \ 79 reg_val &= \ 80 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 81 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 82 reg_val |= \ 83 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 84 AGING_LIST_ENABLE, 1) | \ 85 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 86 AGING_FLUSH_ENABLE, 1); \ 87 HAL_REG_WRITE(soc, \ 88 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 89 REO_REG_REG_BASE), \ 90 reg_val); \ 91 reg_val = HAL_REG_READ(soc, \ 92 HWIO_REO_R0_MISC_CTL_ADDR( \ 93 REO_REG_REG_BASE)); \ 94 reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 95 reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \ 96 FRAGMENT_DEST_RING, \ 97 (reo_params)->frag_dst_ring); \ 98 reg_val |= ((HAL_REO_MSDU_END_COPY) << \ 99 HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT); \ 100 HAL_REG_WRITE(soc, \ 101 HWIO_REO_R0_MISC_CTL_ADDR( \ 102 REO_REG_REG_BASE), \ 103 reg_val); \ 104 } while (0) 105 106 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 107 ((struct rx_msdu_desc_info *) \ 108 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 109 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 110 111 #define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \ 112 HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy 113 114 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 115 ((struct rx_msdu_details *) \ 116 _OFFSET_TO_BYTE_PTR((link_desc),\ 117 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 118 119 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 120 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006 121 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1 122 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2 123 124 #define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \ 125 ((HAL_RX_GET_64((rx_tlv), \ 126 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \ 127 RTT_CFR_STATUS) & \ 128 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \ 129 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB) 130 #endif 131 #endif 132