1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for
6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the
7*5113495bSYour Name * above copyright notice and this permission notice appear in all
8*5113495bSYour Name * copies.
9*5113495bSYour Name *
10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE.
18*5113495bSYour Name */
19*5113495bSYour Name #ifndef _HAL_9224_TX_H_
20*5113495bSYour Name #define _HAL_9224_TX_H_
21*5113495bSYour Name
22*5113495bSYour Name #include "tcl_data_cmd.h"
23*5113495bSYour Name #include "phyrx_rssi_legacy.h"
24*5113495bSYour Name #include "hal_internal.h"
25*5113495bSYour Name #include "qdf_trace.h"
26*5113495bSYour Name #include "hal_rx.h"
27*5113495bSYour Name #include "hal_tx.h"
28*5113495bSYour Name #include "hal_api_mon.h"
29*5113495bSYour Name #include <hal_be_tx.h>
30*5113495bSYour Name
31*5113495bSYour Name #define DSCP_TID_TABLE_SIZE 24
32*5113495bSYour Name #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
33*5113495bSYour Name #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
34*5113495bSYour Name
35*5113495bSYour Name /**
36*5113495bSYour Name * hal_tx_ppe2tcl_ring_halt_get_9224() - Get ring halt for the ppe2tcl ring
37*5113495bSYour Name * @hal_soc: HAL SoC context
38*5113495bSYour Name *
39*5113495bSYour Name * Return: Ring halt status.
40*5113495bSYour Name */
hal_tx_ppe2tcl_ring_halt_get_9224(hal_soc_handle_t hal_soc)41*5113495bSYour Name static uint32_t hal_tx_ppe2tcl_ring_halt_get_9224(hal_soc_handle_t hal_soc)
42*5113495bSYour Name {
43*5113495bSYour Name uint32_t cmn_reg_addr;
44*5113495bSYour Name uint32_t regval;
45*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
46*5113495bSYour Name
47*5113495bSYour Name cmn_reg_addr =
48*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
49*5113495bSYour Name
50*5113495bSYour Name /* Get RING_HALT status */
51*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
52*5113495bSYour Name return (regval &
53*5113495bSYour Name (1 <<
54*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT));
55*5113495bSYour Name }
56*5113495bSYour Name
57*5113495bSYour Name /**
58*5113495bSYour Name * hal_tx_ppe2tcl_ring_halt_set_9224() - Enable ring halt for the ppe2tcl ring
59*5113495bSYour Name * @hal_soc: HAL SoC context
60*5113495bSYour Name *
61*5113495bSYour Name * Return: none
62*5113495bSYour Name */
hal_tx_ppe2tcl_ring_halt_set_9224(hal_soc_handle_t hal_soc)63*5113495bSYour Name static void hal_tx_ppe2tcl_ring_halt_set_9224(hal_soc_handle_t hal_soc)
64*5113495bSYour Name {
65*5113495bSYour Name uint32_t cmn_reg_addr;
66*5113495bSYour Name uint32_t regval;
67*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
68*5113495bSYour Name
69*5113495bSYour Name cmn_reg_addr =
70*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
71*5113495bSYour Name
72*5113495bSYour Name /* Enable RING_HALT */
73*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
74*5113495bSYour Name regval |=
75*5113495bSYour Name (1 <<
76*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
77*5113495bSYour Name
78*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
79*5113495bSYour Name }
80*5113495bSYour Name
81*5113495bSYour Name /**
82*5113495bSYour Name * hal_tx_ppe2tcl_ring_halt_reset_9224() - Disable ring halt for the ppe2tcl
83*5113495bSYour Name * ring
84*5113495bSYour Name * @hal_soc: HAL SoC context
85*5113495bSYour Name *
86*5113495bSYour Name * Return: none
87*5113495bSYour Name */
hal_tx_ppe2tcl_ring_halt_reset_9224(hal_soc_handle_t hal_soc)88*5113495bSYour Name static void hal_tx_ppe2tcl_ring_halt_reset_9224(hal_soc_handle_t hal_soc)
89*5113495bSYour Name {
90*5113495bSYour Name uint32_t cmn_reg_addr;
91*5113495bSYour Name uint32_t regval;
92*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
93*5113495bSYour Name
94*5113495bSYour Name cmn_reg_addr =
95*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
96*5113495bSYour Name
97*5113495bSYour Name /* Disable RING_HALT */
98*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
99*5113495bSYour Name regval &= ~(1 <<
100*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
101*5113495bSYour Name
102*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
103*5113495bSYour Name }
104*5113495bSYour Name
105*5113495bSYour Name /**
106*5113495bSYour Name * hal_tx_ppe2tcl_ring_halt_done_9224() - Check if ring halt is done
107*5113495bSYour Name * for ppe2tcl ring
108*5113495bSYour Name * @hal_soc: HAL SoC context
109*5113495bSYour Name *
110*5113495bSYour Name * Return: true if halt done
111*5113495bSYour Name */
hal_tx_ppe2tcl_ring_halt_done_9224(hal_soc_handle_t hal_soc)112*5113495bSYour Name static bool hal_tx_ppe2tcl_ring_halt_done_9224(hal_soc_handle_t hal_soc)
113*5113495bSYour Name {
114*5113495bSYour Name uint32_t cmn_reg_addr;
115*5113495bSYour Name uint32_t regval;
116*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
117*5113495bSYour Name
118*5113495bSYour Name cmn_reg_addr =
119*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
120*5113495bSYour Name
121*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
122*5113495bSYour Name regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT);
123*5113495bSYour Name
124*5113495bSYour Name return(!!regval);
125*5113495bSYour Name }
126*5113495bSYour Name
127*5113495bSYour Name /**
128*5113495bSYour Name * hal_tx_set_dscp_tid_map_9224() - Configure default DSCP to TID map table
129*5113495bSYour Name * @hal_soc: HAL SoC context
130*5113495bSYour Name * @map: DSCP-TID mapping table
131*5113495bSYour Name * @id: mapping table ID - 0-31
132*5113495bSYour Name *
133*5113495bSYour Name * DSCP are mapped to 8 TID values using TID values programmed
134*5113495bSYour Name * in any of the 32 DSCP_TID_MAPS (id = 0-31).
135*5113495bSYour Name *
136*5113495bSYour Name * Return: none
137*5113495bSYour Name */
hal_tx_set_dscp_tid_map_9224(struct hal_soc * hal_soc,uint8_t * map,uint8_t id)138*5113495bSYour Name static void hal_tx_set_dscp_tid_map_9224(struct hal_soc *hal_soc, uint8_t *map,
139*5113495bSYour Name uint8_t id)
140*5113495bSYour Name {
141*5113495bSYour Name int i;
142*5113495bSYour Name uint32_t addr, cmn_reg_addr;
143*5113495bSYour Name uint32_t value = 0, regval;
144*5113495bSYour Name uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
145*5113495bSYour Name
146*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc;
147*5113495bSYour Name
148*5113495bSYour Name if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS)
149*5113495bSYour Name return;
150*5113495bSYour Name
151*5113495bSYour Name cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
152*5113495bSYour Name MAC_TCL_REG_REG_BASE);
153*5113495bSYour Name
154*5113495bSYour Name addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
155*5113495bSYour Name MAC_TCL_REG_REG_BASE,
156*5113495bSYour Name id * NUM_WORDS_PER_DSCP_TID_TABLE);
157*5113495bSYour Name
158*5113495bSYour Name /* Enable read/write access */
159*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
160*5113495bSYour Name regval |=
161*5113495bSYour Name (1 <<
162*5113495bSYour Name HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
163*5113495bSYour Name
164*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
165*5113495bSYour Name
166*5113495bSYour Name /* Write 8 (24 bits) DSCP-TID mappings in each iteration */
167*5113495bSYour Name for (i = 0; i < 64; i += 8) {
168*5113495bSYour Name value = (map[i] |
169*5113495bSYour Name (map[i + 1] << 0x3) |
170*5113495bSYour Name (map[i + 2] << 0x6) |
171*5113495bSYour Name (map[i + 3] << 0x9) |
172*5113495bSYour Name (map[i + 4] << 0xc) |
173*5113495bSYour Name (map[i + 5] << 0xf) |
174*5113495bSYour Name (map[i + 6] << 0x12) |
175*5113495bSYour Name (map[i + 7] << 0x15));
176*5113495bSYour Name
177*5113495bSYour Name qdf_mem_copy(&val[cnt], (void *)&value, 3);
178*5113495bSYour Name cnt += 3;
179*5113495bSYour Name }
180*5113495bSYour Name
181*5113495bSYour Name for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
182*5113495bSYour Name regval = *(uint32_t *)(val + i);
183*5113495bSYour Name HAL_REG_WRITE(soc, addr,
184*5113495bSYour Name (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
185*5113495bSYour Name addr += 4;
186*5113495bSYour Name }
187*5113495bSYour Name
188*5113495bSYour Name /* Disable read/write access */
189*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
190*5113495bSYour Name regval &=
191*5113495bSYour Name ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
192*5113495bSYour Name
193*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
194*5113495bSYour Name }
195*5113495bSYour Name
196*5113495bSYour Name /**
197*5113495bSYour Name * hal_tx_update_dscp_tid_9224() - Update the dscp tid map table as updated
198*5113495bSYour Name * by the user
199*5113495bSYour Name * @soc: HAL SoC context
200*5113495bSYour Name * @tid: TID
201*5113495bSYour Name * @id: MAP ID
202*5113495bSYour Name * @dscp: DSCP
203*5113495bSYour Name *
204*5113495bSYour Name * Return: void
205*5113495bSYour Name */
hal_tx_update_dscp_tid_9224(struct hal_soc * soc,uint8_t tid,uint8_t id,uint8_t dscp)206*5113495bSYour Name static void hal_tx_update_dscp_tid_9224(struct hal_soc *soc, uint8_t tid,
207*5113495bSYour Name uint8_t id, uint8_t dscp)
208*5113495bSYour Name {
209*5113495bSYour Name uint32_t addr, addr1, cmn_reg_addr;
210*5113495bSYour Name uint32_t start_value = 0, end_value = 0;
211*5113495bSYour Name uint32_t regval;
212*5113495bSYour Name uint8_t end_bits = 0;
213*5113495bSYour Name uint8_t start_bits = 0;
214*5113495bSYour Name uint32_t start_index, end_index;
215*5113495bSYour Name
216*5113495bSYour Name cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
217*5113495bSYour Name MAC_TCL_REG_REG_BASE);
218*5113495bSYour Name
219*5113495bSYour Name addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
220*5113495bSYour Name MAC_TCL_REG_REG_BASE,
221*5113495bSYour Name id * NUM_WORDS_PER_DSCP_TID_TABLE);
222*5113495bSYour Name
223*5113495bSYour Name start_index = dscp * HAL_TX_BITS_PER_TID;
224*5113495bSYour Name end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
225*5113495bSYour Name % HAL_TX_NUM_DSCP_REGISTER_SIZE;
226*5113495bSYour Name start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
227*5113495bSYour Name addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
228*5113495bSYour Name HAL_TX_NUM_DSCP_REGISTER_SIZE));
229*5113495bSYour Name
230*5113495bSYour Name if (end_index < start_index) {
231*5113495bSYour Name end_bits = end_index + 1;
232*5113495bSYour Name start_bits = HAL_TX_BITS_PER_TID - end_bits;
233*5113495bSYour Name start_value = tid << start_index;
234*5113495bSYour Name end_value = tid >> start_bits;
235*5113495bSYour Name addr1 = addr + 4;
236*5113495bSYour Name } else {
237*5113495bSYour Name start_bits = HAL_TX_BITS_PER_TID - end_bits;
238*5113495bSYour Name start_value = tid << start_index;
239*5113495bSYour Name addr1 = 0;
240*5113495bSYour Name }
241*5113495bSYour Name
242*5113495bSYour Name /* Enable read/write access */
243*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
244*5113495bSYour Name regval |=
245*5113495bSYour Name (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
246*5113495bSYour Name
247*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
248*5113495bSYour Name
249*5113495bSYour Name regval = HAL_REG_READ(soc, addr);
250*5113495bSYour Name
251*5113495bSYour Name if (end_index < start_index)
252*5113495bSYour Name regval &= (~0) >> start_bits;
253*5113495bSYour Name else
254*5113495bSYour Name regval &= ~(7 << start_index);
255*5113495bSYour Name
256*5113495bSYour Name regval |= start_value;
257*5113495bSYour Name
258*5113495bSYour Name HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
259*5113495bSYour Name
260*5113495bSYour Name if (addr1) {
261*5113495bSYour Name regval = HAL_REG_READ(soc, addr1);
262*5113495bSYour Name regval &= (~0) << end_bits;
263*5113495bSYour Name regval |= end_value;
264*5113495bSYour Name
265*5113495bSYour Name HAL_REG_WRITE(soc, addr1, (regval &
266*5113495bSYour Name HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
267*5113495bSYour Name }
268*5113495bSYour Name
269*5113495bSYour Name /* Disable read/write access */
270*5113495bSYour Name regval = HAL_REG_READ(soc, cmn_reg_addr);
271*5113495bSYour Name regval &=
272*5113495bSYour Name ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
273*5113495bSYour Name HAL_REG_WRITE(soc, cmn_reg_addr, regval);
274*5113495bSYour Name }
275*5113495bSYour Name
276*5113495bSYour Name #ifdef DP_TX_IMPLICIT_RBM_MAPPING
277*5113495bSYour Name
278*5113495bSYour Name #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
279*5113495bSYour Name #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
280*5113495bSYour Name
281*5113495bSYour Name #define RBM_PPE2TCL_OFFSET \
282*5113495bSYour Name (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2)
283*5113495bSYour Name #define RBM_TCL_CMD_CREDIT_OFFSET \
284*5113495bSYour Name (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
285*5113495bSYour Name
286*5113495bSYour Name /**
287*5113495bSYour Name * hal_tx_config_rbm_mapping_be_9224() - Update return buffer manager ring id
288*5113495bSYour Name * @hal_soc_hdl: HAL SoC context
289*5113495bSYour Name * @hal_ring_hdl: Source ring pointer
290*5113495bSYour Name * @rbm_id: return buffer manager ring id
291*5113495bSYour Name *
292*5113495bSYour Name * Return: void
293*5113495bSYour Name */
294*5113495bSYour Name static inline void
hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,uint8_t rbm_id)295*5113495bSYour Name hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl,
296*5113495bSYour Name hal_ring_handle_t hal_ring_hdl,
297*5113495bSYour Name uint8_t rbm_id)
298*5113495bSYour Name {
299*5113495bSYour Name struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
300*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
301*5113495bSYour Name uint32_t reg_addr = 0;
302*5113495bSYour Name uint32_t reg_val = 0;
303*5113495bSYour Name uint32_t val = 0;
304*5113495bSYour Name uint8_t ring_num;
305*5113495bSYour Name enum hal_ring_type ring_type;
306*5113495bSYour Name
307*5113495bSYour Name ring_type = srng->ring_type;
308*5113495bSYour Name ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
309*5113495bSYour Name ring_num = srng->ring_id - ring_num;
310*5113495bSYour Name
311*5113495bSYour Name reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
312*5113495bSYour Name
313*5113495bSYour Name if (ring_type == PPE2TCL)
314*5113495bSYour Name ring_num = ring_num + RBM_PPE2TCL_OFFSET;
315*5113495bSYour Name else if (ring_type == TCL_CMD_CREDIT)
316*5113495bSYour Name ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
317*5113495bSYour Name
318*5113495bSYour Name /* get current value stored in register address */
319*5113495bSYour Name val = HAL_REG_READ(hal_soc, reg_addr);
320*5113495bSYour Name
321*5113495bSYour Name /* mask out other stored value */
322*5113495bSYour Name val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
323*5113495bSYour Name
324*5113495bSYour Name reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
325*5113495bSYour Name (RBM_MAPPING_SHFT * ring_num));
326*5113495bSYour Name
327*5113495bSYour Name /* write rbm mapped value to register address */
328*5113495bSYour Name HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
329*5113495bSYour Name }
330*5113495bSYour Name #else
331*5113495bSYour Name static inline void
hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,uint8_t rbm_id)332*5113495bSYour Name hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl,
333*5113495bSYour Name hal_ring_handle_t hal_ring_hdl,
334*5113495bSYour Name uint8_t rbm_id)
335*5113495bSYour Name {
336*5113495bSYour Name }
337*5113495bSYour Name #endif
338*5113495bSYour Name
339*5113495bSYour Name /**
340*5113495bSYour Name * hal_tx_init_cmd_credit_ring_9224() - Initialize command/credit SRNG
341*5113495bSYour Name * @hal_soc_hdl: Handle to HAL SoC structure
342*5113495bSYour Name * @hal_ring_hdl: Handle to HAL SRNG structure
343*5113495bSYour Name *
344*5113495bSYour Name * Return: none
345*5113495bSYour Name */
346*5113495bSYour Name static inline void
hal_tx_init_cmd_credit_ring_9224(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)347*5113495bSYour Name hal_tx_init_cmd_credit_ring_9224(hal_soc_handle_t hal_soc_hdl,
348*5113495bSYour Name hal_ring_handle_t hal_ring_hdl)
349*5113495bSYour Name {
350*5113495bSYour Name }
351*5113495bSYour Name
352*5113495bSYour Name /* TX MONITOR */
353*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) && defined(TX_MONITOR_WORD_MASK)
354*5113495bSYour Name
355*5113495bSYour Name #define TX_FES_SETUP_MASK 0x3
356*5113495bSYour Name typedef struct tx_fes_setup_compact_9224 hal_tx_fes_setup_t;
357*5113495bSYour Name struct tx_fes_setup_compact_9224 {
358*5113495bSYour Name /* DWORD - 0 */
359*5113495bSYour Name uint32_t schedule_id;
360*5113495bSYour Name /* DWORD - 1 */
361*5113495bSYour Name uint32_t reserved_1a : 7, // [0: 6]
362*5113495bSYour Name transmit_start_reason : 3, // [7: 9]
363*5113495bSYour Name reserved_1b : 13, // [10: 22]
364*5113495bSYour Name number_of_users : 6, // [28: 23]
365*5113495bSYour Name mu_type : 1, // [29]
366*5113495bSYour Name reserved_1c : 2; // [30]
367*5113495bSYour Name /* DWORD - 2 */
368*5113495bSYour Name uint32_t reserved_2a : 4, // [0: 3]
369*5113495bSYour Name ndp_frame : 2, // [4: 5]
370*5113495bSYour Name txbf : 1, // [6]
371*5113495bSYour Name reserved_2b : 3, // [7: 9]
372*5113495bSYour Name static_bandwidth : 3, // [12: 10]
373*5113495bSYour Name reserved_2c : 1, // [13]
374*5113495bSYour Name transmission_contains_mu_rts : 1, // [14]
375*5113495bSYour Name reserved_2d : 17; // [15: 31]
376*5113495bSYour Name /* DWORD - 3 */
377*5113495bSYour Name uint32_t reserved_3a : 15, // [0: 14]
378*5113495bSYour Name mu_ndp : 1, // [15]
379*5113495bSYour Name reserved_3b : 11, // [16: 26]
380*5113495bSYour Name ndpa : 1, // [27]
381*5113495bSYour Name reserved_3c : 4; // [28: 31]
382*5113495bSYour Name };
383*5113495bSYour Name
384*5113495bSYour Name #define TX_PEER_ENTRY_MASK 0x103
385*5113495bSYour Name typedef struct tx_peer_entry_compact_9224 hal_tx_peer_entry_t;
386*5113495bSYour Name struct tx_peer_entry_compact_9224 {
387*5113495bSYour Name /* DWORD - 0 */
388*5113495bSYour Name uint32_t mac_addr_a_31_0 : 32;
389*5113495bSYour Name /* DWORD - 1 */
390*5113495bSYour Name uint32_t mac_addr_a_47_32 : 16,
391*5113495bSYour Name mac_addr_b_15_0 : 16;
392*5113495bSYour Name /* DWORD - 2 */
393*5113495bSYour Name uint32_t mac_addr_b_47_16 : 32;
394*5113495bSYour Name /* DWORD - 3 */
395*5113495bSYour Name uint32_t reserved_3 : 32;
396*5113495bSYour Name /* DWORD - 16 */
397*5113495bSYour Name uint32_t reserved_16 : 32;
398*5113495bSYour Name /* DWORD - 17 */
399*5113495bSYour Name uint32_t multi_link_addr_crypto_enable : 1,
400*5113495bSYour Name reserved_17_a : 15,
401*5113495bSYour Name sw_peer_id : 16;
402*5113495bSYour Name };
403*5113495bSYour Name
404*5113495bSYour Name #define TX_QUEUE_EXT_MASK 0x1
405*5113495bSYour Name typedef struct tx_queue_ext_compact_9224 hal_tx_queue_ext_t;
406*5113495bSYour Name struct tx_queue_ext_compact_9224 {
407*5113495bSYour Name /* DWORD - 0 */
408*5113495bSYour Name uint32_t frame_ctl : 16,
409*5113495bSYour Name qos_ctl : 16;
410*5113495bSYour Name /* DWORD - 1 */
411*5113495bSYour Name uint32_t ampdu_flag : 1,
412*5113495bSYour Name reserved_1 : 31;
413*5113495bSYour Name };
414*5113495bSYour Name
415*5113495bSYour Name #define TX_MSDU_START_MASK 0x1
416*5113495bSYour Name typedef struct tx_msdu_start_compact_9224 hal_tx_msdu_start_t;
417*5113495bSYour Name struct tx_msdu_start_compact_9224 {
418*5113495bSYour Name /* DWORD - 0 */
419*5113495bSYour Name uint32_t reserved_0 : 32;
420*5113495bSYour Name /* DWORD - 1 */
421*5113495bSYour Name uint32_t reserved_1 : 32;
422*5113495bSYour Name };
423*5113495bSYour Name
424*5113495bSYour Name #define TX_MPDU_START_MASK 0x3
425*5113495bSYour Name typedef struct tx_mpdu_start_compact_9224 hal_tx_mpdu_start_t;
426*5113495bSYour Name struct tx_mpdu_start_compact_9224 {
427*5113495bSYour Name /* DWORD - 0 */
428*5113495bSYour Name uint32_t mpdu_length : 14,
429*5113495bSYour Name frame_not_from_tqm : 1,
430*5113495bSYour Name vht_control_present : 1,
431*5113495bSYour Name mpdu_header_length : 8,
432*5113495bSYour Name retry_count : 7,
433*5113495bSYour Name wds : 1;
434*5113495bSYour Name /* DWORD - 1 */
435*5113495bSYour Name uint32_t pn_31_0 : 32;
436*5113495bSYour Name /* DWORD - 2 */
437*5113495bSYour Name uint32_t pn_47_32 : 16,
438*5113495bSYour Name mpdu_sequence_number : 12,
439*5113495bSYour Name raw_already_encrypted : 1,
440*5113495bSYour Name frame_type : 2,
441*5113495bSYour Name txdma_dropped_mpdu_warning : 1;
442*5113495bSYour Name /* DWORD - 3 */
443*5113495bSYour Name uint32_t reserved_3 : 32;
444*5113495bSYour Name };
445*5113495bSYour Name
446*5113495bSYour Name typedef struct rxpcu_user_setup_compact_9224 hal_rxpcu_user_setup_t;
447*5113495bSYour Name struct rxpcu_user_setup_compact_9224 {
448*5113495bSYour Name };
449*5113495bSYour Name
450*5113495bSYour Name #define TX_FES_STATUS_END_MASK 0x7
451*5113495bSYour Name typedef struct tx_fes_status_end_compact_9224 hal_tx_fes_status_end_t;
452*5113495bSYour Name struct tx_fes_status_end_compact_9224 {
453*5113495bSYour Name /* DWORD - 0 */
454*5113495bSYour Name uint32_t reserved_0 : 32;
455*5113495bSYour Name /* DWORD - 1 */
456*5113495bSYour Name struct {
457*5113495bSYour Name uint16_t phytx_abort_reason : 8,
458*5113495bSYour Name user_number : 6,
459*5113495bSYour Name reserved_1a : 2;
460*5113495bSYour Name } phytx_abort_request_info_details;
461*5113495bSYour Name uint16_t reserved_1b : 12,
462*5113495bSYour Name phytx_abort_request_info_valid : 1,
463*5113495bSYour Name reserved_1c : 3;
464*5113495bSYour Name /* DWORD - 2 */
465*5113495bSYour Name uint32_t start_of_frame_timestamp_15_0 : 16,
466*5113495bSYour Name start_of_frame_timestamp_31_16 : 16;
467*5113495bSYour Name /* DWORD - 3 */
468*5113495bSYour Name uint32_t end_of_frame_timestamp_15_0 : 16,
469*5113495bSYour Name end_of_frame_timestamp_31_16 : 16;
470*5113495bSYour Name /* DWORD - 4 */
471*5113495bSYour Name uint32_t terminate_ranging_sequence : 1,
472*5113495bSYour Name reserved_4a : 7,
473*5113495bSYour Name timing_status : 2,
474*5113495bSYour Name response_type : 5,
475*5113495bSYour Name r2r_end_status_to_follow : 1,
476*5113495bSYour Name transmit_delay : 16;
477*5113495bSYour Name /* DWORD - 5 */
478*5113495bSYour Name uint32_t reserved_5 : 32;
479*5113495bSYour Name };
480*5113495bSYour Name
481*5113495bSYour Name #define RESPONSE_END_STATUS_MASK 0xD
482*5113495bSYour Name typedef struct response_end_status_compact_9224 hal_response_end_status_t;
483*5113495bSYour Name struct response_end_status_compact_9224 {
484*5113495bSYour Name /* DWORD - 0 */
485*5113495bSYour Name uint32_t coex_bt_tx_while_wlan_tx : 1,
486*5113495bSYour Name coex_wan_tx_while_wlan_tx : 1,
487*5113495bSYour Name coex_wlan_tx_while_wlan_tx : 1,
488*5113495bSYour Name global_data_underflow_warning : 1,
489*5113495bSYour Name response_transmit_status : 4,
490*5113495bSYour Name phytx_pkt_end_info_valid : 1,
491*5113495bSYour Name phytx_abort_request_info_valid : 1,
492*5113495bSYour Name generated_response : 3,
493*5113495bSYour Name mba_user_count : 7,
494*5113495bSYour Name mba_fake_bitmap_count : 7,
495*5113495bSYour Name coex_based_tx_bw : 3,
496*5113495bSYour Name trig_response_related : 1,
497*5113495bSYour Name dpdtrain_done : 1;
498*5113495bSYour Name /* DWORD - 1 */
499*5113495bSYour Name uint32_t reserved_1 : 32;
500*5113495bSYour Name /* DWORD - 4 */
501*5113495bSYour Name uint32_t reserved_4 : 32;
502*5113495bSYour Name /* DWORD - 5 */
503*5113495bSYour Name uint32_t start_of_frame_timestamp_15_0 : 16,
504*5113495bSYour Name start_of_frame_timestamp_31_16 : 16;
505*5113495bSYour Name /* DWORD - 6 */
506*5113495bSYour Name uint32_t end_of_frame_timestamp_15_0 : 16,
507*5113495bSYour Name end_of_frame_timestamp_31_16 : 16;
508*5113495bSYour Name /* DWORD - 7 */
509*5113495bSYour Name uint32_t reserved_7 : 32;
510*5113495bSYour Name };
511*5113495bSYour Name
512*5113495bSYour Name #define TX_FES_STATUS_PROT_MASK 0x2
513*5113495bSYour Name typedef struct tx_fes_status_prot_compact_9224 hal_tx_fes_status_prot_t;
514*5113495bSYour Name struct tx_fes_status_prot_compact_9224 {
515*5113495bSYour Name /* DWORD - 2 */
516*5113495bSYour Name uint32_t start_of_frame_timestamp_15_0 : 16,
517*5113495bSYour Name start_of_frame_timestamp_31_16 : 16;
518*5113495bSYour Name /* DWROD - 3 */
519*5113495bSYour Name uint32_t end_of_frame_timestamp_15_0 : 16,
520*5113495bSYour Name end_of_frame_timestamp_31_16 : 16;
521*5113495bSYour Name };
522*5113495bSYour Name
523*5113495bSYour Name #define PCU_PPDU_SETUP_INIT_MASK 0x1E800000
524*5113495bSYour Name typedef struct pcu_ppdu_setup_init_compact_9224 hal_pcu_ppdu_setup_t;
525*5113495bSYour Name struct pcu_ppdu_setup_init_compact_9224 {
526*5113495bSYour Name /* DWORD - 46 */
527*5113495bSYour Name uint32_t reserved_46 : 32;
528*5113495bSYour Name /* DWORD - 47 */
529*5113495bSYour Name uint32_t r2r_group_id : 6,
530*5113495bSYour Name r2r_response_frame_type : 4,
531*5113495bSYour Name r2r_sta_partial_aid : 11,
532*5113495bSYour Name use_address_fields_for_protection : 1,
533*5113495bSYour Name r2r_set_required_response_time : 1,
534*5113495bSYour Name reserved_47 : 9;
535*5113495bSYour Name /* DWORD - 50 */
536*5113495bSYour Name uint32_t reserved_50 : 32;
537*5113495bSYour Name /* DWORD - 51 */
538*5113495bSYour Name uint32_t protection_frame_ad1_31_0 : 32;
539*5113495bSYour Name /* DWORD - 52 */
540*5113495bSYour Name uint32_t protection_frame_ad1_47_32 : 16,
541*5113495bSYour Name protection_frame_ad2_15_0 : 16;
542*5113495bSYour Name /* DWORD - 53 */
543*5113495bSYour Name uint32_t protection_frame_ad2_47_16 : 32;
544*5113495bSYour Name /* DWORD - 54 */
545*5113495bSYour Name uint32_t reserved_54 : 32;
546*5113495bSYour Name /* DWORD - 55 */
547*5113495bSYour Name uint32_t protection_frame_ad3_31_0 : 32;
548*5113495bSYour Name /* DWORD - 56 */
549*5113495bSYour Name uint32_t protection_frame_ad3_47_32 : 16,
550*5113495bSYour Name protection_frame_ad4_15_0 : 16;
551*5113495bSYour Name /* DWORD - 57 */
552*5113495bSYour Name uint32_t protection_frame_ad4_47_16 : 32;
553*5113495bSYour Name };
554*5113495bSYour Name
555*5113495bSYour Name /**
556*5113495bSYour Name * hal_txmon_get_word_mask_qcn9224() - api to get word mask for tx monitor
557*5113495bSYour Name * @wmask: pointer to hal_txmon_word_mask_config_t
558*5113495bSYour Name *
559*5113495bSYour Name * Return: void
560*5113495bSYour Name */
561*5113495bSYour Name static inline
hal_txmon_get_word_mask_qcn9224(void * wmask)562*5113495bSYour Name void hal_txmon_get_word_mask_qcn9224(void *wmask)
563*5113495bSYour Name {
564*5113495bSYour Name hal_txmon_word_mask_config_t *word_mask = NULL;
565*5113495bSYour Name
566*5113495bSYour Name word_mask = (hal_txmon_word_mask_config_t *)wmask;
567*5113495bSYour Name
568*5113495bSYour Name word_mask->compaction_enable = 1;
569*5113495bSYour Name word_mask->tx_fes_setup = TX_FES_SETUP_MASK;
570*5113495bSYour Name word_mask->tx_peer_entry = TX_PEER_ENTRY_MASK;
571*5113495bSYour Name word_mask->tx_queue_ext = TX_QUEUE_EXT_MASK;
572*5113495bSYour Name word_mask->tx_msdu_start = TX_MSDU_START_MASK;
573*5113495bSYour Name word_mask->pcu_ppdu_setup_init = PCU_PPDU_SETUP_INIT_MASK;
574*5113495bSYour Name word_mask->tx_mpdu_start = TX_MPDU_START_MASK;
575*5113495bSYour Name word_mask->rxpcu_user_setup = 0xFF;
576*5113495bSYour Name word_mask->tx_fes_status_end = TX_FES_STATUS_END_MASK;
577*5113495bSYour Name word_mask->response_end_status = RESPONSE_END_STATUS_MASK;
578*5113495bSYour Name word_mask->tx_fes_status_prot = TX_FES_STATUS_PROT_MASK;
579*5113495bSYour Name }
580*5113495bSYour Name #endif
581*5113495bSYour Name
582*5113495bSYour Name /**
583*5113495bSYour Name * hal_tx_set_ppe_cmn_config_9224() - Set the PPE common config register
584*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
585*5113495bSYour Name * @cmn_cfg: Common PPE config
586*5113495bSYour Name *
587*5113495bSYour Name * Based on the PPE2TCL descriptor below errors, if the below register
588*5113495bSYour Name * values are set then the packets are forward to Tx rule handler if 1'0b
589*5113495bSYour Name * or to TCL exit base if 1'1b.
590*5113495bSYour Name *
591*5113495bSYour Name * Return: void
592*5113495bSYour Name */
593*5113495bSYour Name static inline
hal_tx_set_ppe_cmn_config_9224(hal_soc_handle_t hal_soc_hdl,union hal_tx_cmn_config_ppe * cmn_cfg)594*5113495bSYour Name void hal_tx_set_ppe_cmn_config_9224(hal_soc_handle_t hal_soc_hdl,
595*5113495bSYour Name union hal_tx_cmn_config_ppe *cmn_cfg)
596*5113495bSYour Name {
597*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
598*5113495bSYour Name union hal_tx_cmn_config_ppe *cfg =
599*5113495bSYour Name (union hal_tx_cmn_config_ppe *)cmn_cfg;
600*5113495bSYour Name uint32_t reg_addr, reg_val = 0;
601*5113495bSYour Name
602*5113495bSYour Name reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE);
603*5113495bSYour Name
604*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
605*5113495bSYour Name
606*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;
607*5113495bSYour Name reg_val |=
608*5113495bSYour Name (cfg->drop_prec_err &
609*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) <<
610*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT;
611*5113495bSYour Name
612*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;
613*5113495bSYour Name reg_val |=
614*5113495bSYour Name (cfg->fake_mac_hdr &
615*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) <<
616*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT;
617*5113495bSYour Name
618*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;
619*5113495bSYour Name reg_val |=
620*5113495bSYour Name (cfg->cpu_code_inv &
621*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) <<
622*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT;
623*5113495bSYour Name
624*5113495bSYour Name reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;
625*5113495bSYour Name reg_val |=
626*5113495bSYour Name (cfg->l3_l4_err &
627*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) <<
628*5113495bSYour Name HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT;
629*5113495bSYour Name
630*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
631*5113495bSYour Name }
632*5113495bSYour Name
633*5113495bSYour Name /**
634*5113495bSYour Name * hal_tx_set_ppe_vp_entry_9224() - Set the PPE VP entry
635*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
636*5113495bSYour Name * @cfg: PPE VP config
637*5113495bSYour Name * @ppe_vp_idx : PPE VP index to the table
638*5113495bSYour Name *
639*5113495bSYour Name * Return: void
640*5113495bSYour Name */
641*5113495bSYour Name static inline
hal_tx_set_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl,union hal_tx_ppe_vp_config * cfg,int ppe_vp_idx)642*5113495bSYour Name void hal_tx_set_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl,
643*5113495bSYour Name union hal_tx_ppe_vp_config *cfg,
644*5113495bSYour Name int ppe_vp_idx)
645*5113495bSYour Name {
646*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
647*5113495bSYour Name uint32_t reg_addr;
648*5113495bSYour Name
649*5113495bSYour Name reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
650*5113495bSYour Name ppe_vp_idx);
651*5113495bSYour Name
652*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, cfg->val);
653*5113495bSYour Name }
654*5113495bSYour Name
655*5113495bSYour Name /**
656*5113495bSYour Name * hal_ppeds_cfg_ast_override_map_reg_9224() - Set the PPE index mapping table
657*5113495bSYour Name * @hal_soc_hdl: HAL SoC context
658*5113495bSYour Name * @idx: index into the table
659*5113495bSYour Name * @idx_map: HAL PPE INDESX MAPPING config
660*5113495bSYour Name *
661*5113495bSYour Name * Return: void
662*5113495bSYour Name */
663*5113495bSYour Name static inline void
hal_ppeds_cfg_ast_override_map_reg_9224(hal_soc_handle_t hal_soc_hdl,uint8_t idx,union hal_tx_ppe_idx_map_config * idx_map)664*5113495bSYour Name hal_ppeds_cfg_ast_override_map_reg_9224(hal_soc_handle_t hal_soc_hdl,
665*5113495bSYour Name uint8_t idx,
666*5113495bSYour Name union hal_tx_ppe_idx_map_config *idx_map)
667*5113495bSYour Name {
668*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
669*5113495bSYour Name uint32_t reg_addr;
670*5113495bSYour Name
671*5113495bSYour Name reg_addr =
672*5113495bSYour Name HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
673*5113495bSYour Name idx);
674*5113495bSYour Name
675*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, idx_map->val);
676*5113495bSYour Name }
677*5113495bSYour Name
678*5113495bSYour Name /**
679*5113495bSYour Name * hal_tx_set_ppe_pri2tid_map_9224() - Set PPE PRI to TID map
680*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
681*5113495bSYour Name * @val : PRI to TID value
682*5113495bSYour Name * @map_no: Map number
683*5113495bSYour Name *
684*5113495bSYour Name * Return: void
685*5113495bSYour Name */
686*5113495bSYour Name static inline
hal_tx_set_ppe_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,uint32_t val,uint8_t map_no)687*5113495bSYour Name void hal_tx_set_ppe_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,
688*5113495bSYour Name uint32_t val, uint8_t map_no)
689*5113495bSYour Name {
690*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
691*5113495bSYour Name uint32_t reg_addr, reg_val = 0;
692*5113495bSYour Name
693*5113495bSYour Name if (map_no == 0)
694*5113495bSYour Name reg_addr =
695*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
696*5113495bSYour Name else
697*5113495bSYour Name reg_addr =
698*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
699*5113495bSYour Name
700*5113495bSYour Name reg_val |= val;
701*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
702*5113495bSYour Name }
703*5113495bSYour Name
704*5113495bSYour Name /**
705*5113495bSYour Name * hal_tx_enable_pri2tid_map_9224() - Enable PRI to TID map
706*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
707*5113495bSYour Name * @val: PRI to TID value
708*5113495bSYour Name * @ppe_vp_idx: Map number
709*5113495bSYour Name *
710*5113495bSYour Name * Return: void
711*5113495bSYour Name */
712*5113495bSYour Name static inline
hal_tx_enable_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,bool val,uint8_t ppe_vp_idx)713*5113495bSYour Name void hal_tx_enable_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,
714*5113495bSYour Name bool val, uint8_t ppe_vp_idx)
715*5113495bSYour Name {
716*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
717*5113495bSYour Name uint32_t reg_addr, reg_val = 0;
718*5113495bSYour Name
719*5113495bSYour Name reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
720*5113495bSYour Name ppe_vp_idx);
721*5113495bSYour Name
722*5113495bSYour Name /*
723*5113495bSYour Name * Drop precedence is enabled by default.
724*5113495bSYour Name */
725*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
726*5113495bSYour Name
727*5113495bSYour Name reg_val &=
728*5113495bSYour Name ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
729*5113495bSYour Name
730*5113495bSYour Name reg_val |=
731*5113495bSYour Name (val &
732*5113495bSYour Name HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
733*5113495bSYour Name HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
734*5113495bSYour Name
735*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
736*5113495bSYour Name }
737*5113495bSYour Name
738*5113495bSYour Name /**
739*5113495bSYour Name * hal_tx_update_ppe_pri2tid_9224() - Update PPE PRI to TID
740*5113495bSYour Name * @hal_soc_hdl: HAL SoC handle
741*5113495bSYour Name * @pri: INT_PRI
742*5113495bSYour Name * @tid: Wi-Fi TID
743*5113495bSYour Name *
744*5113495bSYour Name * Return: void
745*5113495bSYour Name */
746*5113495bSYour Name static inline
hal_tx_update_ppe_pri2tid_9224(hal_soc_handle_t hal_soc_hdl,uint8_t pri,uint8_t tid)747*5113495bSYour Name void hal_tx_update_ppe_pri2tid_9224(hal_soc_handle_t hal_soc_hdl,
748*5113495bSYour Name uint8_t pri, uint8_t tid)
749*5113495bSYour Name {
750*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
751*5113495bSYour Name uint32_t reg_addr, reg_val = 0, mask, shift;
752*5113495bSYour Name
753*5113495bSYour Name /*
754*5113495bSYour Name * INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15
755*5113495bSYour Name * is in MAP1 register.
756*5113495bSYour Name */
757*5113495bSYour Name switch (pri) {
758*5113495bSYour Name case 0 ... 9:
759*5113495bSYour Name reg_addr =
760*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
761*5113495bSYour Name mask =
762*5113495bSYour Name (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri));
763*5113495bSYour Name shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3);
764*5113495bSYour Name break;
765*5113495bSYour Name case 10 ... 15:
766*5113495bSYour Name pri = pri - 10;
767*5113495bSYour Name reg_addr =
768*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
769*5113495bSYour Name mask =
770*5113495bSYour Name (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri));
771*5113495bSYour Name shift =
772*5113495bSYour Name HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3);
773*5113495bSYour Name break;
774*5113495bSYour Name default:
775*5113495bSYour Name return;
776*5113495bSYour Name }
777*5113495bSYour Name
778*5113495bSYour Name reg_val = HAL_REG_READ(soc, reg_addr);
779*5113495bSYour Name reg_val &= ~mask;
780*5113495bSYour Name reg_val |= (pri << shift) & mask;
781*5113495bSYour Name
782*5113495bSYour Name HAL_REG_WRITE(soc, reg_addr, reg_val);
783*5113495bSYour Name }
784*5113495bSYour Name #endif /* _HAL_9224_TX_H_ */
785