xref: /wlan-driver/qca-wifi-host-cmn/hif/inc/host_reg_init.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef HOST_REG_INIT_H
20 #define HOST_REG_INIT_H
21 
22 #include "reg_struct.h"
23 #include "targaddrs.h"
24 
25 #if defined(MY_HOST_DEF)
26 
27 #if !defined(FW_IND_HOST_READY)
28 #define FW_IND_HOST_READY 0
29 #endif
30 
31 #if !defined(PCIE_LOCAL_BASE_ADDRESS)
32 #define PCIE_LOCAL_BASE_ADDRESS 0
33 #define PCIE_SOC_WAKE_RESET 0
34 #define PCIE_SOC_WAKE_ADDRESS 0
35 #define PCIE_SOC_WAKE_V_MASK 0
36 #define RTC_STATE_ADDRESS 0
37 #define RTC_STATE_COLD_RESET_MASK 0
38 #define RTC_STATE_V_MASK 0
39 #define RTC_STATE_V_LSB 0
40 #define RTC_STATE_V_ON 0
41 #define SOC_GLOBAL_RESET_ADDRESS 0
42 #endif
43 
44 #if !defined(CE_COUNT)
45 #define CE_COUNT 0
46 #endif
47 
48 #if !defined(TRANSACTION_ID_MASK)
49 #define TRANSACTION_ID_MASK 0xfff
50 #endif
51 
52 static struct hostdef_s my_host_def = {
53 	.d_INT_STATUS_ENABLE_ERROR_LSB = INT_STATUS_ENABLE_ERROR_LSB,
54 	.d_INT_STATUS_ENABLE_ERROR_MASK = INT_STATUS_ENABLE_ERROR_MASK,
55 	.d_INT_STATUS_ENABLE_CPU_LSB = INT_STATUS_ENABLE_CPU_LSB,
56 	.d_INT_STATUS_ENABLE_CPU_MASK = INT_STATUS_ENABLE_CPU_MASK,
57 	.d_INT_STATUS_ENABLE_COUNTER_LSB = INT_STATUS_ENABLE_COUNTER_LSB,
58 	.d_INT_STATUS_ENABLE_COUNTER_MASK = INT_STATUS_ENABLE_COUNTER_MASK,
59 	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB = INT_STATUS_ENABLE_MBOX_DATA_LSB,
60 	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK = INT_STATUS_ENABLE_MBOX_DATA_MASK,
61 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB
62 		= ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
63 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK
64 		= ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
65 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB
66 		= ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
67 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK
68 		= ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
69 	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB
70 		= COUNTER_INT_STATUS_ENABLE_BIT_LSB,
71 	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK
72 		= COUNTER_INT_STATUS_ENABLE_BIT_MASK,
73 	.d_INT_STATUS_ENABLE_ADDRESS = INT_STATUS_ENABLE_ADDRESS,
74 	.d_CPU_INT_STATUS_ENABLE_BIT_LSB = CPU_INT_STATUS_ENABLE_BIT_LSB,
75 	.d_CPU_INT_STATUS_ENABLE_BIT_MASK = CPU_INT_STATUS_ENABLE_BIT_MASK,
76 	.d_HOST_INT_STATUS_ADDRESS = HOST_INT_STATUS_ADDRESS,
77 	.d_CPU_INT_STATUS_ADDRESS = CPU_INT_STATUS_ADDRESS,
78 	.d_ERROR_INT_STATUS_ADDRESS = ERROR_INT_STATUS_ADDRESS,
79 	.d_ERROR_INT_STATUS_WAKEUP_MASK = ERROR_INT_STATUS_WAKEUP_MASK,
80 	.d_ERROR_INT_STATUS_WAKEUP_LSB = ERROR_INT_STATUS_WAKEUP_LSB,
81 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK
82 		= ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
83 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB
84 		= ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
85 	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK
86 		= ERROR_INT_STATUS_TX_OVERFLOW_MASK,
87 	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = ERROR_INT_STATUS_TX_OVERFLOW_LSB,
88 	.d_COUNT_DEC_ADDRESS = COUNT_DEC_ADDRESS,
89 	.d_HOST_INT_STATUS_CPU_MASK = HOST_INT_STATUS_CPU_MASK,
90 	.d_HOST_INT_STATUS_CPU_LSB = HOST_INT_STATUS_CPU_LSB,
91 	.d_HOST_INT_STATUS_ERROR_MASK = HOST_INT_STATUS_ERROR_MASK,
92 	.d_HOST_INT_STATUS_ERROR_LSB = HOST_INT_STATUS_ERROR_LSB,
93 	.d_HOST_INT_STATUS_COUNTER_MASK = HOST_INT_STATUS_COUNTER_MASK,
94 	.d_HOST_INT_STATUS_COUNTER_LSB = HOST_INT_STATUS_COUNTER_LSB,
95 	.d_RX_LOOKAHEAD_VALID_ADDRESS = RX_LOOKAHEAD_VALID_ADDRESS,
96 	.d_WINDOW_DATA_ADDRESS = WINDOW_DATA_ADDRESS,
97 	.d_WINDOW_READ_ADDR_ADDRESS = WINDOW_READ_ADDR_ADDRESS,
98 	.d_WINDOW_WRITE_ADDR_ADDRESS = WINDOW_WRITE_ADDR_ADDRESS,
99 	.d_SOC_GLOBAL_RESET_ADDRESS = SOC_GLOBAL_RESET_ADDRESS,
100 	.d_RTC_STATE_ADDRESS = RTC_STATE_ADDRESS,
101 	.d_RTC_STATE_COLD_RESET_MASK = RTC_STATE_COLD_RESET_MASK,
102 	.d_PCIE_LOCAL_BASE_ADDRESS = PCIE_LOCAL_BASE_ADDRESS,
103 	.d_PCIE_SOC_WAKE_RESET = PCIE_SOC_WAKE_RESET,
104 	.d_PCIE_SOC_WAKE_ADDRESS = PCIE_SOC_WAKE_ADDRESS,
105 	.d_PCIE_SOC_WAKE_V_MASK = PCIE_SOC_WAKE_V_MASK,
106 	.d_RTC_STATE_V_MASK = RTC_STATE_V_MASK,
107 	.d_RTC_STATE_V_LSB = RTC_STATE_V_LSB,
108 	.d_FW_IND_EVENT_PENDING = FW_IND_EVENT_PENDING,
109 	.d_FW_IND_INITIALIZED = FW_IND_INITIALIZED,
110 	.d_RTC_STATE_V_ON = RTC_STATE_V_ON,
111 #if defined(SDIO_3_0)
112 	.d_HOST_INT_STATUS_MBOX_DATA_MASK = HOST_INT_STATUS_MBOX_DATA_MASK,
113 	.d_HOST_INT_STATUS_MBOX_DATA_LSB = HOST_INT_STATUS_MBOX_DATA_LSB,
114 #endif
115 	.d_FW_IND_HOST_READY = FW_IND_HOST_READY,
116 	.d_HOST_CE_COUNT = CE_COUNT,
117 	.d_TRANSACTION_ID_MASK = TRANSACTION_ID_MASK,
118 };
119 
120 struct hostdef_s *MY_HOST_DEF = &my_host_def;
121 #else /* MY_HOST_DEF */
122 #endif /* MY_HOST_DEF */
123 
124 
125 
126 #if defined(MY_HOST_SHADOW_REGS)
127 struct host_shadow_regs_s my_host_shadow_regs = {
128 	.d_A_LOCAL_SHADOW_REG_VALUE_0 = A_LOCAL_SHADOW_REG_VALUE_0;
129 	.d_A_LOCAL_SHADOW_REG_VALUE_1 = A_LOCAL_SHADOW_REG_VALUE_1;
130 	.d_A_LOCAL_SHADOW_REG_VALUE_2 = A_LOCAL_SHADOW_REG_VALUE_2;
131 	.d_A_LOCAL_SHADOW_REG_VALUE_3 = A_LOCAL_SHADOW_REG_VALUE_3;
132 	.d_A_LOCAL_SHADOW_REG_VALUE_4 = A_LOCAL_SHADOW_REG_VALUE_4;
133 	.d_A_LOCAL_SHADOW_REG_VALUE_5 = A_LOCAL_SHADOW_REG_VALUE_5;
134 	.d_A_LOCAL_SHADOW_REG_VALUE_6 = A_LOCAL_SHADOW_REG_VALUE_6;
135 	.d_A_LOCAL_SHADOW_REG_VALUE_7 = A_LOCAL_SHADOW_REG_VALUE_7;
136 	.d_A_LOCAL_SHADOW_REG_VALUE_8 = A_LOCAL_SHADOW_REG_VALUE_8;
137 	.d_A_LOCAL_SHADOW_REG_VALUE_9 = A_LOCAL_SHADOW_REG_VALUE_9;
138 	.d_A_LOCAL_SHADOW_REG_VALUE_10 = A_LOCAL_SHADOW_REG_VALUE_10;
139 	.d_A_LOCAL_SHADOW_REG_VALUE_11 = A_LOCAL_SHADOW_REG_VALUE_11;
140 	.d_A_LOCAL_SHADOW_REG_VALUE_12 = A_LOCAL_SHADOW_REG_VALUE_12;
141 	.d_A_LOCAL_SHADOW_REG_VALUE_13 = A_LOCAL_SHADOW_REG_VALUE_13;
142 	.d_A_LOCAL_SHADOW_REG_VALUE_14 = A_LOCAL_SHADOW_REG_VALUE_14;
143 	.d_A_LOCAL_SHADOW_REG_VALUE_15 = A_LOCAL_SHADOW_REG_VALUE_15;
144 	.d_A_LOCAL_SHADOW_REG_VALUE_16 = A_LOCAL_SHADOW_REG_VALUE_16;
145 	.d_A_LOCAL_SHADOW_REG_VALUE_17 = A_LOCAL_SHADOW_REG_VALUE_17;
146 	.d_A_LOCAL_SHADOW_REG_VALUE_18 = A_LOCAL_SHADOW_REG_VALUE_18;
147 	.d_A_LOCAL_SHADOW_REG_VALUE_19 = A_LOCAL_SHADOW_REG_VALUE_19;
148 	.d_A_LOCAL_SHADOW_REG_VALUE_20 = A_LOCAL_SHADOW_REG_VALUE_20;
149 	.d_A_LOCAL_SHADOW_REG_VALUE_21 = A_LOCAL_SHADOW_REG_VALUE_21;
150 	.d_A_LOCAL_SHADOW_REG_VALUE_22 = A_LOCAL_SHADOW_REG_VALUE_22;
151 	.d_A_LOCAL_SHADOW_REG_VALUE_23 = A_LOCAL_SHADOW_REG_VALUE_23;
152 	.d_A_LOCAL_SHADOW_REG_ADDRESS_0 = A_LOCAL_SHADOW_REG_ADDRESS_0;
153 	.d_A_LOCAL_SHADOW_REG_ADDRESS_1 = A_LOCAL_SHADOW_REG_ADDRESS_1;
154 	.d_A_LOCAL_SHADOW_REG_ADDRESS_2 = A_LOCAL_SHADOW_REG_ADDRESS_2;
155 	.d_A_LOCAL_SHADOW_REG_ADDRESS_3 = A_LOCAL_SHADOW_REG_ADDRESS_3;
156 	.d_A_LOCAL_SHADOW_REG_ADDRESS_4 = A_LOCAL_SHADOW_REG_ADDRESS_4;
157 	.d_A_LOCAL_SHADOW_REG_ADDRESS_5 = A_LOCAL_SHADOW_REG_ADDRESS_5;
158 	.d_A_LOCAL_SHADOW_REG_ADDRESS_6 = A_LOCAL_SHADOW_REG_ADDRESS_6;
159 	.d_A_LOCAL_SHADOW_REG_ADDRESS_7 = A_LOCAL_SHADOW_REG_ADDRESS_7;
160 	.d_A_LOCAL_SHADOW_REG_ADDRESS_8 = A_LOCAL_SHADOW_REG_ADDRESS_8;
161 	.d_A_LOCAL_SHADOW_REG_ADDRESS_9 = A_LOCAL_SHADOW_REG_ADDRESS_9;
162 	.d_A_LOCAL_SHADOW_REG_ADDRESS_10 = A_LOCAL_SHADOW_REG_ADDRESS_10;
163 	.d_A_LOCAL_SHADOW_REG_ADDRESS_11 = A_LOCAL_SHADOW_REG_ADDRESS_11;
164 	.d_A_LOCAL_SHADOW_REG_ADDRESS_12 = A_LOCAL_SHADOW_REG_ADDRESS_12;
165 	.d_A_LOCAL_SHADOW_REG_ADDRESS_13 = A_LOCAL_SHADOW_REG_ADDRESS_13;
166 	.d_A_LOCAL_SHADOW_REG_ADDRESS_14 = A_LOCAL_SHADOW_REG_ADDRESS_14;
167 	.d_A_LOCAL_SHADOW_REG_ADDRESS_15 = A_LOCAL_SHADOW_REG_ADDRESS_15;
168 	.d_A_LOCAL_SHADOW_REG_ADDRESS_16 = A_LOCAL_SHADOW_REG_ADDRESS_16;
169 	.d_A_LOCAL_SHADOW_REG_ADDRESS_17 = A_LOCAL_SHADOW_REG_ADDRESS_17;
170 	.d_A_LOCAL_SHADOW_REG_ADDRESS_18 = A_LOCAL_SHADOW_REG_ADDRESS_18;
171 	.d_A_LOCAL_SHADOW_REG_ADDRESS_19 = A_LOCAL_SHADOW_REG_ADDRESS_19;
172 	.d_A_LOCAL_SHADOW_REG_ADDRESS_20 = A_LOCAL_SHADOW_REG_ADDRESS_20;
173 	.d_A_LOCAL_SHADOW_REG_ADDRESS_21 = A_LOCAL_SHADOW_REG_ADDRESS_21;
174 	.d_A_LOCAL_SHADOW_REG_ADDRESS_22 = A_LOCAL_SHADOW_REG_ADDRESS_22;
175 	.d_A_LOCAL_SHADOW_REG_ADDRESS_23 = A_LOCAL_SHADOW_REG_ADDRESS_23;
176 };
177 
178 struct hostdef_s *MY_HOST_SHADOW_REGS = &my_host_shadow_regs;
179 #else /* MY_HOST_SHADOW_REGS */
180 #endif /* MY_HOST_SHADOW_REGS */
181 #endif /* HOST_REG_INIT_H */
182