1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef _REGTABLE_IPCIE_H_ 18*5113495bSYour Name #define _REGTABLE_IPCIE_H_ 19*5113495bSYour Name 20*5113495bSYour Name #define MISSING 0 21*5113495bSYour Name 22*5113495bSYour Name #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \ 23*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK) 24*5113495bSYour Name #define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \ 25*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1) 26*5113495bSYour Name #define A_SOC_CORE_SPARE_1_REGISTER \ 27*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER) 28*5113495bSYour Name #define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \ 29*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1) 30*5113495bSYour Name #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \ 31*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1) 32*5113495bSYour Name #define A_SOC_PCIE_PCIE_SCRATCH_0 \ 33*5113495bSYour Name (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0) 34*5113495bSYour Name #define A_SOC_PCIE_PCIE_SCRATCH_1 \ 35*5113495bSYour Name (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1) 36*5113495bSYour Name #define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \ 37*5113495bSYour Name (scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA) 38*5113495bSYour Name #define A_SOC_PCIE_PCIE_SCRATCH_2 \ 39*5113495bSYour Name (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2) 40*5113495bSYour Name /* end Q6 iHelium emu registers */ 41*5113495bSYour Name 42*5113495bSYour Name #define PCIE_INTR_FIRMWARE_ROUTE_MASK \ 43*5113495bSYour Name (scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK) 44*5113495bSYour Name #define A_SOC_CORE_SPARE_0_REGISTER \ 45*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER) 46*5113495bSYour Name #define A_SOC_CORE_SCRATCH_0_ADDRESS \ 47*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS) 48*5113495bSYour Name #define A_SOC_CORE_SCRATCH_1_ADDRESS \ 49*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS) 50*5113495bSYour Name #define A_SOC_CORE_SCRATCH_2_ADDRESS \ 51*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS) 52*5113495bSYour Name #define A_SOC_CORE_SCRATCH_3_ADDRESS \ 53*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS) 54*5113495bSYour Name #define A_SOC_CORE_SCRATCH_4_ADDRESS \ 55*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS) 56*5113495bSYour Name #define A_SOC_CORE_SCRATCH_5_ADDRESS \ 57*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS) 58*5113495bSYour Name #define A_SOC_CORE_SCRATCH_6_ADDRESS \ 59*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS) 60*5113495bSYour Name #define A_SOC_CORE_SCRATCH_7_ADDRESS \ 61*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS) 62*5113495bSYour Name #define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 63*5113495bSYour Name #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 64*5113495bSYour Name #define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 65*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_OFFSET \ 66*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 67*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 68*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 69*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 70*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 71*5113495bSYour Name #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 72*5113495bSYour Name #define CLOCK_CONTROL_SI0_CLK_MASK \ 73*5113495bSYour Name (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 74*5113495bSYour Name #define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET) 75*5113495bSYour Name #define RESET_CONTROL_MBOX_RST_MASK \ 76*5113495bSYour Name (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 77*5113495bSYour Name #define RESET_CONTROL_SI0_RST_MASK \ 78*5113495bSYour Name (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 79*5113495bSYour Name #define WLAN_RESET_CONTROL_OFFSET \ 80*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 81*5113495bSYour Name #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 82*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 83*5113495bSYour Name #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 84*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 85*5113495bSYour Name #define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS) 86*5113495bSYour Name #define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET) 87*5113495bSYour Name #define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET) 88*5113495bSYour Name #define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 89*5113495bSYour Name #define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 90*5113495bSYour Name #define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0) 91*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 92*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 93*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 94*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 95*5113495bSYour Name #define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB) 96*5113495bSYour Name #define SI_CONFIG_I2C_MASK \ 97*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_I2C_MASK) 98*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_LSB \ 99*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 100*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_MASK \ 101*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 102*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_LSB \ 103*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 104*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_MASK \ 105*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 106*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_LSB \ 107*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 108*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_MASK \ 109*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 110*5113495bSYour Name #define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 111*5113495bSYour Name #define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 112*5113495bSYour Name #define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS) 113*5113495bSYour Name #define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET) 114*5113495bSYour Name #define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET) 115*5113495bSYour Name #define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET) 116*5113495bSYour Name #define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET) 117*5113495bSYour Name #define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET) 118*5113495bSYour Name #define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET) 119*5113495bSYour Name #define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 120*5113495bSYour Name #define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK) 121*5113495bSYour Name #define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB) 122*5113495bSYour Name #define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK) 123*5113495bSYour Name #define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB) 124*5113495bSYour Name #define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK) 125*5113495bSYour Name #define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB) 126*5113495bSYour Name #define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK) 127*5113495bSYour Name #define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ) 128*5113495bSYour Name #define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ) 129*5113495bSYour Name #define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS) 130*5113495bSYour Name #define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 131*5113495bSYour Name #define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET) 132*5113495bSYour Name #define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET) 133*5113495bSYour Name #define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET) 134*5113495bSYour Name #define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET) 135*5113495bSYour Name #define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET) 136*5113495bSYour Name #define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET) 137*5113495bSYour Name #define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET) 138*5113495bSYour Name #define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 139*5113495bSYour Name #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 140*5113495bSYour Name #define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 141*5113495bSYour Name #define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 142*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 143*5113495bSYour Name (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 144*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 145*5113495bSYour Name (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 146*5113495bSYour Name #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 147*5113495bSYour Name #define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 148*5113495bSYour Name #define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS) 149*5113495bSYour Name #define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS) 150*5113495bSYour Name #define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 151*5113495bSYour Name #define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS) 152*5113495bSYour Name #define CE_COUNT (scn->targetdef->d_CE_COUNT) 153*5113495bSYour Name #define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS) 154*5113495bSYour Name #define PCIE_INTR_CLR_ADDRESS (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS) 155*5113495bSYour Name #define PCIE_INTR_FIRMWARE_MASK (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK) 156*5113495bSYour Name #define PCIE_INTR_CE_MASK_ALL (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL) 157*5113495bSYour Name #define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 158*5113495bSYour Name #define PCIE_INTR_CAUSE_ADDRESS (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS) 159*5113495bSYour Name #define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 160*5113495bSYour Name #define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \ 161*5113495bSYour Name A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK) 162*5113495bSYour Name #define SOC_RESET_CONTROL_CE_RST_MASK \ 163*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK) 164*5113495bSYour Name #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ 165*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 166*5113495bSYour Name #define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS) 167*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 168*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 169*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 170*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 171*5113495bSYour Name #define SOC_LF_TIMER_STATUS0_ADDRESS \ 172*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS) 173*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \ 174*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 175*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \ 176*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 177*5113495bSYour Name 178*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \ 179*5113495bSYour Name (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \ 180*5113495bSYour Name SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 181*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \ 182*5113495bSYour Name (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \ 183*5113495bSYour Name SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 184*5113495bSYour Name 185*5113495bSYour Name /* hif_ipci.c */ 186*5113495bSYour Name #define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 187*5113495bSYour Name #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 188*5113495bSYour Name #define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 189*5113495bSYour Name #define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 190*5113495bSYour Name #define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 191*5113495bSYour Name #define CHIP_ID_REVISION_GET(x) \ 192*5113495bSYour Name (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 193*5113495bSYour Name #define CHIP_ID_VERSION_GET(x) \ 194*5113495bSYour Name (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 195*5113495bSYour Name /* hif_ipci.c end */ 196*5113495bSYour Name 197*5113495bSYour Name /* misc */ 198*5113495bSYour Name #define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 199*5113495bSYour Name #define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS) 200*5113495bSYour Name #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET) 201*5113495bSYour Name /* end */ 202*5113495bSYour Name 203*5113495bSYour Name /* copy_engine.c */ 204*5113495bSYour Name /* end */ 205*5113495bSYour Name /* PLL start */ 206*5113495bSYour Name #define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET) 207*5113495bSYour Name #define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 208*5113495bSYour Name #define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 209*5113495bSYour Name #define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 210*5113495bSYour Name #define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 211*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 212*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 213*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 214*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 215*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 216*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 217*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 218*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 219*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 220*5113495bSYour Name #define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 221*5113495bSYour Name #define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 222*5113495bSYour Name #define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 223*5113495bSYour Name #define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 224*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_MSB \ 225*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 226*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_LSB \ 227*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 228*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_MASK \ 229*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 230*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_MSB \ 231*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 232*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_LSB \ 233*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 234*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_MASK \ 235*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 236*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_RESET \ 237*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 238*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 239*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 240*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 241*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 242*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 243*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 244*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 245*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 246*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_MSB \ 247*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 248*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_LSB \ 249*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 250*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_MASK \ 251*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 252*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_RESET \ 253*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 254*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 255*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 256*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 257*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_RESET \ 258*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 259*5113495bSYour Name #define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 260*5113495bSYour Name #define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 261*5113495bSYour Name #define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 262*5113495bSYour Name #define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 263*5113495bSYour Name #define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 264*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 265*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 266*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_MASK \ 267*5113495bSYour Name (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 268*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 269*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 270*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 271*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 272*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 273*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 274*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 275*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 276*5113495bSYour Name #define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 277*5113495bSYour Name #define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 278*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_MSB \ 279*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 280*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_LSB \ 281*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 282*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_MASK \ 283*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 284*5113495bSYour Name /* PLL end */ 285*5113495bSYour Name 286*5113495bSYour Name #define FW_CPU_PLL_CONFIG \ 287*5113495bSYour Name (scn->targetdef->d_FW_CPU_PLL_CONFIG) 288*5113495bSYour Name 289*5113495bSYour Name #define WIFICMN_PCIE_BAR_REG_ADDRESS \ 290*5113495bSYour Name (sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS) 291*5113495bSYour Name 292*5113495bSYour Name /* htt tx */ 293*5113495bSYour Name #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \ 294*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK) 295*5113495bSYour Name #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \ 296*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK) 297*5113495bSYour Name #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \ 298*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK) 299*5113495bSYour Name #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \ 300*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK) 301*5113495bSYour Name #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB \ 302*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB) 303*5113495bSYour Name #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB \ 304*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB) 305*5113495bSYour Name #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB \ 306*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB) 307*5113495bSYour Name #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB \ 308*5113495bSYour Name (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB) 309*5113495bSYour Name 310*5113495bSYour Name #define CE_CMD_ADDRESS \ 311*5113495bSYour Name (scn->targetdef->d_CE_CMD_ADDRESS) 312*5113495bSYour Name #define CE_CMD_HALT_MASK \ 313*5113495bSYour Name (scn->targetdef->d_CE_CMD_HALT_MASK) 314*5113495bSYour Name #define CE_CMD_HALT_STATUS_MASK \ 315*5113495bSYour Name (scn->targetdef->d_CE_CMD_HALT_STATUS_MASK) 316*5113495bSYour Name #define CE_CMD_HALT_STATUS_LSB \ 317*5113495bSYour Name (scn->targetdef->d_CE_CMD_HALT_STATUS_LSB) 318*5113495bSYour Name 319*5113495bSYour Name #define SI_CONFIG_ERR_INT_MASK \ 320*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_ERR_INT_MASK) 321*5113495bSYour Name #define SI_CONFIG_ERR_INT_LSB \ 322*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_ERR_INT_LSB) 323*5113495bSYour Name #define GPIO_ENABLE_W1TS_LOW_ADDRESS \ 324*5113495bSYour Name (scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS) 325*5113495bSYour Name #define GPIO_PIN0_CONFIG_LSB \ 326*5113495bSYour Name (scn->targetdef->d_GPIO_PIN0_CONFIG_LSB) 327*5113495bSYour Name #define GPIO_PIN0_PAD_PULL_LSB \ 328*5113495bSYour Name (scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB) 329*5113495bSYour Name #define GPIO_PIN0_PAD_PULL_MASK \ 330*5113495bSYour Name (scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK) 331*5113495bSYour Name 332*5113495bSYour Name #define SOC_CHIP_ID_REVISION_MSB \ 333*5113495bSYour Name (scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB) 334*5113495bSYour Name 335*5113495bSYour Name #define FW_AXI_MSI_ADDR \ 336*5113495bSYour Name (scn->targetdef->d_FW_AXI_MSI_ADDR) 337*5113495bSYour Name #define FW_AXI_MSI_DATA \ 338*5113495bSYour Name (scn->targetdef->d_FW_AXI_MSI_DATA) 339*5113495bSYour Name #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \ 340*5113495bSYour Name (scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS) 341*5113495bSYour Name #define FPGA_VERSION_ADDRESS \ 342*5113495bSYour Name (scn->targetdef->d_FPGA_VERSION_ADDRESS) 343*5113495bSYour Name 344*5113495bSYour Name /* SET macros */ 345*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 346*5113495bSYour Name (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 347*5113495bSYour Name WLAN_SYSTEM_SLEEP_DISABLE_MASK) 348*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 349*5113495bSYour Name (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) 350*5113495bSYour Name #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 351*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_SET(x) \ 352*5113495bSYour Name (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) 353*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 354*5113495bSYour Name (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) 355*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 356*5113495bSYour Name (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) 357*5113495bSYour Name #define SI_CONFIG_DIVIDER_SET(x) \ 358*5113495bSYour Name (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 359*5113495bSYour Name #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 360*5113495bSYour Name #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 361*5113495bSYour Name #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 362*5113495bSYour Name #define LPO_CAL_ENABLE_SET(x) \ 363*5113495bSYour Name (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 364*5113495bSYour Name #define CPU_CLOCK_STANDARD_SET(x) \ 365*5113495bSYour Name (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 366*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 367*5113495bSYour Name (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 368*5113495bSYour Name /* copy_engine.c */ 369*5113495bSYour Name /* end */ 370*5113495bSYour Name /* PLL start */ 371*5113495bSYour Name #define EFUSE_XTAL_SEL_GET(x) \ 372*5113495bSYour Name (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 373*5113495bSYour Name #define EFUSE_XTAL_SEL_SET(x) \ 374*5113495bSYour Name (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 375*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 376*5113495bSYour Name (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 377*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 378*5113495bSYour Name (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 379*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_GET(x) \ 380*5113495bSYour Name (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 381*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_SET(x) \ 382*5113495bSYour Name (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 383*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_GET(x) \ 384*5113495bSYour Name (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 385*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_SET(x) \ 386*5113495bSYour Name (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 387*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 388*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) 389*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 390*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) 391*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 392*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) 393*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 394*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) 395*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 396*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB) 397*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 398*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK) 399*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 400*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) 401*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 402*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) 403*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_GET(x) \ 404*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) 405*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_SET(x) \ 406*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) 407*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 408*5113495bSYour Name (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB) 409*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 410*5113495bSYour Name (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK) 411*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 412*5113495bSYour Name (((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 413*5113495bSYour Name RTC_SYNC_STATUS_PLL_CHANGING_LSB) 414*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 415*5113495bSYour Name (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 416*5113495bSYour Name RTC_SYNC_STATUS_PLL_CHANGING_MASK) 417*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 418*5113495bSYour Name (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB) 419*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 420*5113495bSYour Name (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) 421*5113495bSYour Name /* PLL end */ 422*5113495bSYour Name #define WLAN_GPIO_PIN0_CONFIG_SET(x) \ 423*5113495bSYour Name (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) 424*5113495bSYour Name #define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \ 425*5113495bSYour Name (((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK) 426*5113495bSYour Name #define SI_CONFIG_ERR_INT_SET(x) \ 427*5113495bSYour Name (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) 428*5113495bSYour Name 429*5113495bSYour Name #ifdef QCA_WIFI_3_0_ADRASTEA 430*5113495bSYour Name #define Q6_ENABLE_REGISTER_0 \ 431*5113495bSYour Name (scn->targetdef->d_Q6_ENABLE_REGISTER_0) 432*5113495bSYour Name #define Q6_ENABLE_REGISTER_1 \ 433*5113495bSYour Name (scn->targetdef->d_Q6_ENABLE_REGISTER_1) 434*5113495bSYour Name #define Q6_CAUSE_REGISTER_0 \ 435*5113495bSYour Name (scn->targetdef->d_Q6_CAUSE_REGISTER_0) 436*5113495bSYour Name #define Q6_CAUSE_REGISTER_1 \ 437*5113495bSYour Name (scn->targetdef->d_Q6_CAUSE_REGISTER_1) 438*5113495bSYour Name #define Q6_CLEAR_REGISTER_0 \ 439*5113495bSYour Name (scn->targetdef->d_Q6_CLEAR_REGISTER_0) 440*5113495bSYour Name #define Q6_CLEAR_REGISTER_1 \ 441*5113495bSYour Name (scn->targetdef->d_Q6_CLEAR_REGISTER_1) 442*5113495bSYour Name #endif 443*5113495bSYour Name 444*5113495bSYour Name #ifdef CONFIG_BYPASS_QMI 445*5113495bSYour Name #define BYPASS_QMI_TEMP_REGISTER \ 446*5113495bSYour Name (scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER) 447*5113495bSYour Name #endif 448*5113495bSYour Name 449*5113495bSYour Name #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START) 450*5113495bSYour Name #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK) 451*5113495bSYour Name #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK) 452*5113495bSYour Name #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK) 453*5113495bSYour Name #define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT) 454*5113495bSYour Name #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI) 455*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_LSB \ 456*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 457*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_MASK \ 458*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 459*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 460*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 461*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_LSB \ 462*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 463*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_MASK \ 464*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 465*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 466*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 467*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 468*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 469*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 470*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 471*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 472*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 473*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \ 474*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 475*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 476*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 477*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 478*5113495bSYour Name (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 479*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 480*5113495bSYour Name (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 481*5113495bSYour Name #define INT_STATUS_ENABLE_ADDRESS \ 482*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 483*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 484*5113495bSYour Name (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 485*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 486*5113495bSYour Name (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 487*5113495bSYour Name #define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 488*5113495bSYour Name #define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 489*5113495bSYour Name #define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 490*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_MASK \ 491*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 492*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_LSB \ 493*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 494*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 495*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 496*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 497*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 498*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 499*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 500*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 501*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 502*5113495bSYour Name #define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS) 503*5113495bSYour Name #define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 504*5113495bSYour Name #define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 505*5113495bSYour Name #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 506*5113495bSYour Name #define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 507*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_MASK \ 508*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 509*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_LSB \ 510*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 511*5113495bSYour Name #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 512*5113495bSYour Name #define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS) 513*5113495bSYour Name #define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 514*5113495bSYour Name #define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 515*5113495bSYour Name #define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 516*5113495bSYour Name #define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS) 517*5113495bSYour Name #define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 518*5113495bSYour Name #define PCIE_LOCAL_BASE_ADDRESS (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS) 519*5113495bSYour Name #define PCIE_SOC_WAKE_RESET (scn->hostdef->d_PCIE_SOC_WAKE_RESET) 520*5113495bSYour Name #define PCIE_SOC_WAKE_ADDRESS (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS) 521*5113495bSYour Name #define PCIE_SOC_WAKE_V_MASK (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK) 522*5113495bSYour Name #define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK) 523*5113495bSYour Name #define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB) 524*5113495bSYour Name #define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING) 525*5113495bSYour Name #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED) 526*5113495bSYour Name #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER) 527*5113495bSYour Name #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON) 528*5113495bSYour Name 529*5113495bSYour Name #define FW_IND_HOST_READY (scn->hostdef->d_FW_IND_HOST_READY) 530*5113495bSYour Name 531*5113495bSYour Name #if defined(SDIO_3_0) 532*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_MASK \ 533*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 534*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_LSB \ 535*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 536*5113495bSYour Name #endif 537*5113495bSYour Name 538*5113495bSYour Name #if !defined(SOC_PCIE_BASE_ADDRESS) 539*5113495bSYour Name #define SOC_PCIE_BASE_ADDRESS 0 540*5113495bSYour Name #endif 541*5113495bSYour Name 542*5113495bSYour Name #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS) 543*5113495bSYour Name #define PCIE_SOC_RDY_STATUS_ADDRESS 0 544*5113495bSYour Name #define PCIE_SOC_RDY_STATUS_BAR_MASK 0 545*5113495bSYour Name #endif 546*5113495bSYour Name 547*5113495bSYour Name #if !defined(MSI_MAGIC_ADR_ADDRESS) 548*5113495bSYour Name #define MSI_MAGIC_ADR_ADDRESS 0 549*5113495bSYour Name #define MSI_MAGIC_ADDRESS 0 550*5113495bSYour Name #endif 551*5113495bSYour Name 552*5113495bSYour Name /* SET/GET macros */ 553*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_SET(x) \ 554*5113495bSYour Name (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) 555*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_SET(x) \ 556*5113495bSYour Name (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) 557*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 558*5113495bSYour Name (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 559*5113495bSYour Name INT_STATUS_ENABLE_COUNTER_MASK) 560*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 561*5113495bSYour Name (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 562*5113495bSYour Name INT_STATUS_ENABLE_MBOX_DATA_MASK) 563*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 564*5113495bSYour Name (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 565*5113495bSYour Name CPU_INT_STATUS_ENABLE_BIT_MASK) 566*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 567*5113495bSYour Name (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 568*5113495bSYour Name ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 569*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \ 570*5113495bSYour Name (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 571*5113495bSYour Name ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 572*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 573*5113495bSYour Name (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 574*5113495bSYour Name COUNTER_INT_STATUS_ENABLE_BIT_MASK) 575*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 576*5113495bSYour Name (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 577*5113495bSYour Name ERROR_INT_STATUS_WAKEUP_LSB) 578*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 579*5113495bSYour Name (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 580*5113495bSYour Name ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 581*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 582*5113495bSYour Name (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 583*5113495bSYour Name ERROR_INT_STATUS_TX_OVERFLOW_LSB) 584*5113495bSYour Name #define HOST_INT_STATUS_CPU_GET(x) \ 585*5113495bSYour Name (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) 586*5113495bSYour Name #define HOST_INT_STATUS_ERROR_GET(x) \ 587*5113495bSYour Name (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) 588*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_GET(x) \ 589*5113495bSYour Name (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) 590*5113495bSYour Name #define RTC_STATE_V_GET(x) \ 591*5113495bSYour Name (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 592*5113495bSYour Name #if defined(SDIO_3_0) 593*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 594*5113495bSYour Name (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 595*5113495bSYour Name HOST_INT_STATUS_MBOX_DATA_LSB) 596*5113495bSYour Name #endif 597*5113495bSYour Name 598*5113495bSYour Name #define INVALID_REG_LOC_DUMMY_DATA 0xAA 599*5113495bSYour Name 600*5113495bSYour Name #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 601*5113495bSYour Name #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 602*5113495bSYour Name #define AR6320_CPU_SPEED_ADDR 0x403fa4 603*5113495bSYour Name #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 604*5113495bSYour Name #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 605*5113495bSYour Name #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 606*5113495bSYour Name #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 607*5113495bSYour Name #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 608*5113495bSYour Name #define AR6320V3_CPU_SPEED_ADDR 0x404024 609*5113495bSYour Name 610*5113495bSYour Name enum a_refclk_speed_t { 611*5113495bSYour Name SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ 612*5113495bSYour Name SOC_REFCLK_48_MHZ = 0, 613*5113495bSYour Name SOC_REFCLK_19_2_MHZ = 1, 614*5113495bSYour Name SOC_REFCLK_24_MHZ = 2, 615*5113495bSYour Name SOC_REFCLK_26_MHZ = 3, 616*5113495bSYour Name SOC_REFCLK_37_4_MHZ = 4, 617*5113495bSYour Name SOC_REFCLK_38_4_MHZ = 5, 618*5113495bSYour Name SOC_REFCLK_40_MHZ = 6, 619*5113495bSYour Name SOC_REFCLK_52_MHZ = 7, 620*5113495bSYour Name }; 621*5113495bSYour Name 622*5113495bSYour Name #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 623*5113495bSYour Name #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 624*5113495bSYour Name #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 625*5113495bSYour Name #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 626*5113495bSYour Name #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 627*5113495bSYour Name #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 628*5113495bSYour Name #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 629*5113495bSYour Name #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 630*5113495bSYour Name #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 631*5113495bSYour Name 632*5113495bSYour Name #define TARGET_CPU_FREQ 176000000 633*5113495bSYour Name 634*5113495bSYour Name struct wlan_pll_s { 635*5113495bSYour Name uint32_t refdiv; 636*5113495bSYour Name uint32_t div; 637*5113495bSYour Name uint32_t rnfrac; 638*5113495bSYour Name uint32_t outdiv; 639*5113495bSYour Name }; 640*5113495bSYour Name 641*5113495bSYour Name struct cmnos_clock_s { 642*5113495bSYour Name enum a_refclk_speed_t refclk_speed; 643*5113495bSYour Name uint32_t refclk_hz; 644*5113495bSYour Name uint32_t pll_settling_time; /* 50us */ 645*5113495bSYour Name struct wlan_pll_s wlan_pll; 646*5113495bSYour Name }; 647*5113495bSYour Name 648*5113495bSYour Name struct tgt_reg_section { 649*5113495bSYour Name uint32_t start_addr; 650*5113495bSYour Name uint32_t end_addr; 651*5113495bSYour Name }; 652*5113495bSYour Name 653*5113495bSYour Name struct tgt_reg_table { 654*5113495bSYour Name const struct tgt_reg_section *section; 655*5113495bSYour Name uint32_t section_size; 656*5113495bSYour Name }; 657*5113495bSYour Name 658*5113495bSYour Name struct hif_softc; 659*5113495bSYour Name void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type); 660*5113495bSYour Name void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type); 661*5113495bSYour Name 662*5113495bSYour Name #endif /* _REGTABLE_IPCIE_H_ */ 663