xref: /wlan-driver/qca-wifi-host-cmn/hif/inc/regtable_ipcie.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7 
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _REGTABLE_IPCIE_H_
18 #define _REGTABLE_IPCIE_H_
19 
20 #define MISSING  0
21 
22 #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \
23 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
24 #define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \
25 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1)
26 #define A_SOC_CORE_SPARE_1_REGISTER \
27 	(scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER)
28 #define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \
29 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1)
30 #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \
31 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1)
32 #define A_SOC_PCIE_PCIE_SCRATCH_0 \
33 	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0)
34 #define A_SOC_PCIE_PCIE_SCRATCH_1 \
35 	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1)
36 #define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \
37 	(scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA)
38 #define A_SOC_PCIE_PCIE_SCRATCH_2 \
39 	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2)
40 /* end Q6 iHelium emu registers */
41 
42 #define PCIE_INTR_FIRMWARE_ROUTE_MASK \
43 	(scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK)
44 #define A_SOC_CORE_SPARE_0_REGISTER \
45 	(scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
46 #define A_SOC_CORE_SCRATCH_0_ADDRESS  \
47 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
48 #define A_SOC_CORE_SCRATCH_1_ADDRESS  \
49 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
50 #define A_SOC_CORE_SCRATCH_2_ADDRESS  \
51 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
52 #define A_SOC_CORE_SCRATCH_3_ADDRESS  \
53 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
54 #define A_SOC_CORE_SCRATCH_4_ADDRESS  \
55 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
56 #define A_SOC_CORE_SCRATCH_5_ADDRESS  \
57 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
58 #define A_SOC_CORE_SCRATCH_6_ADDRESS  \
59 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
60 #define A_SOC_CORE_SCRATCH_7_ADDRESS  \
61 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
62 #define RTC_SOC_BASE_ADDRESS  (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
63 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
64 #define SYSTEM_SLEEP_OFFSET   (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
65 #define WLAN_SYSTEM_SLEEP_OFFSET \
66 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
67 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \
68 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
69 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \
70 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
71 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
72 #define CLOCK_CONTROL_SI0_CLK_MASK \
73 	(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
74 #define RESET_CONTROL_OFFSET    (scn->targetdef->d_RESET_CONTROL_OFFSET)
75 #define RESET_CONTROL_MBOX_RST_MASK \
76 	(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
77 #define RESET_CONTROL_SI0_RST_MASK \
78 	(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
79 #define WLAN_RESET_CONTROL_OFFSET \
80 	(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
81 #define WLAN_RESET_CONTROL_COLD_RST_MASK \
82 	(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
83 #define WLAN_RESET_CONTROL_WARM_RST_MASK \
84 	(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
85 #define GPIO_BASE_ADDRESS       (scn->targetdef->d_GPIO_BASE_ADDRESS)
86 #define GPIO_PIN0_OFFSET        (scn->targetdef->d_GPIO_PIN0_OFFSET)
87 #define GPIO_PIN1_OFFSET        (scn->targetdef->d_GPIO_PIN1_OFFSET)
88 #define GPIO_PIN0_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
89 #define GPIO_PIN1_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
90 #define A_SOC_CORE_SCRATCH_0    (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
91 #define SI_CONFIG_BIDIR_OD_DATA_LSB \
92 	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
93 #define SI_CONFIG_BIDIR_OD_DATA_MASK \
94 	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
95 #define SI_CONFIG_I2C_LSB       (scn->targetdef->d_SI_CONFIG_I2C_LSB)
96 #define SI_CONFIG_I2C_MASK \
97 	(scn->targetdef->d_SI_CONFIG_I2C_MASK)
98 #define SI_CONFIG_POS_SAMPLE_LSB \
99 	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
100 #define SI_CONFIG_POS_SAMPLE_MASK \
101 	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
102 #define SI_CONFIG_INACTIVE_CLK_LSB \
103 	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
104 #define SI_CONFIG_INACTIVE_CLK_MASK \
105 	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
106 #define SI_CONFIG_INACTIVE_DATA_LSB \
107 	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
108 #define SI_CONFIG_INACTIVE_DATA_MASK \
109 	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
110 #define SI_CONFIG_DIVIDER_LSB   (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
111 #define SI_CONFIG_DIVIDER_MASK  (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
112 #define SI_BASE_ADDRESS         (scn->targetdef->d_SI_BASE_ADDRESS)
113 #define SI_CONFIG_OFFSET        (scn->targetdef->d_SI_CONFIG_OFFSET)
114 #define SI_TX_DATA0_OFFSET      (scn->targetdef->d_SI_TX_DATA0_OFFSET)
115 #define SI_TX_DATA1_OFFSET      (scn->targetdef->d_SI_TX_DATA1_OFFSET)
116 #define SI_RX_DATA0_OFFSET      (scn->targetdef->d_SI_RX_DATA0_OFFSET)
117 #define SI_RX_DATA1_OFFSET      (scn->targetdef->d_SI_RX_DATA1_OFFSET)
118 #define SI_CS_OFFSET            (scn->targetdef->d_SI_CS_OFFSET)
119 #define SI_CS_DONE_ERR_MASK     (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
120 #define SI_CS_DONE_INT_MASK     (scn->targetdef->d_SI_CS_DONE_INT_MASK)
121 #define SI_CS_START_LSB         (scn->targetdef->d_SI_CS_START_LSB)
122 #define SI_CS_START_MASK        (scn->targetdef->d_SI_CS_START_MASK)
123 #define SI_CS_RX_CNT_LSB        (scn->targetdef->d_SI_CS_RX_CNT_LSB)
124 #define SI_CS_RX_CNT_MASK       (scn->targetdef->d_SI_CS_RX_CNT_MASK)
125 #define SI_CS_TX_CNT_LSB        (scn->targetdef->d_SI_CS_TX_CNT_LSB)
126 #define SI_CS_TX_CNT_MASK       (scn->targetdef->d_SI_CS_TX_CNT_MASK)
127 #define EEPROM_SZ               (scn->targetdef->d_BOARD_DATA_SZ)
128 #define EEPROM_EXT_SZ           (scn->targetdef->d_BOARD_EXT_DATA_SZ)
129 #define MBOX_BASE_ADDRESS       (scn->targetdef->d_MBOX_BASE_ADDRESS)
130 #define LOCAL_SCRATCH_OFFSET    (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
131 #define CPU_CLOCK_OFFSET        (scn->targetdef->d_CPU_CLOCK_OFFSET)
132 #define LPO_CAL_OFFSET          (scn->targetdef->d_LPO_CAL_OFFSET)
133 #define GPIO_PIN10_OFFSET       (scn->targetdef->d_GPIO_PIN10_OFFSET)
134 #define GPIO_PIN11_OFFSET       (scn->targetdef->d_GPIO_PIN11_OFFSET)
135 #define GPIO_PIN12_OFFSET       (scn->targetdef->d_GPIO_PIN12_OFFSET)
136 #define GPIO_PIN13_OFFSET       (scn->targetdef->d_GPIO_PIN13_OFFSET)
137 #define CLOCK_GPIO_OFFSET       (scn->targetdef->d_CLOCK_GPIO_OFFSET)
138 #define CPU_CLOCK_STANDARD_LSB  (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
139 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
140 #define LPO_CAL_ENABLE_LSB      (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
141 #define LPO_CAL_ENABLE_MASK     (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
142 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \
143 	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
144 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \
145 	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
146 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
147 #define WLAN_MAC_BASE_ADDRESS    (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
148 #define FW_INDICATOR_ADDRESS     (scn->targetdef->d_FW_INDICATOR_ADDRESS)
149 #define DRAM_BASE_ADDRESS        (scn->targetdef->d_DRAM_BASE_ADDRESS)
150 #define SOC_CORE_BASE_ADDRESS    (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
151 #define CORE_CTRL_ADDRESS        (scn->targetdef->d_CORE_CTRL_ADDRESS)
152 #define CE_COUNT                 (scn->targetdef->d_CE_COUNT)
153 #define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
154 #define PCIE_INTR_CLR_ADDRESS    (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
155 #define PCIE_INTR_FIRMWARE_MASK  (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
156 #define PCIE_INTR_CE_MASK_ALL    (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
157 #define CORE_CTRL_CPU_INTR_MASK  (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
158 #define PCIE_INTR_CAUSE_ADDRESS  (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
159 #define SOC_RESET_CONTROL_ADDRESS  (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
160 #define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \
161 	A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
162 #define SOC_RESET_CONTROL_CE_RST_MASK \
163 	(scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
164 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \
165 	(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
166 #define CPU_INTR_ADDRESS        (scn->targetdef->d_CPU_INTR_ADDRESS)
167 #define SOC_LF_TIMER_CONTROL0_ADDRESS \
168 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
169 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
170 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
171 #define SOC_LF_TIMER_STATUS0_ADDRESS \
172 	(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
173 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
174 	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
175 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \
176 	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
177 
178 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \
179 	(((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \
180 	 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
181 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \
182 	(((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \
183 		SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
184 
185 /* hif_ipci.c */
186 #define CHIP_ID_ADDRESS           (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
187 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
188 #define SOC_CHIP_ID_REVISION_LSB  (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
189 #define SOC_CHIP_ID_VERSION_MASK  (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
190 #define SOC_CHIP_ID_VERSION_LSB   (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
191 #define CHIP_ID_REVISION_GET(x) \
192 	(((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB)
193 #define CHIP_ID_VERSION_GET(x) \
194 	(((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB)
195 /* hif_ipci.c end */
196 
197 /* misc */
198 #define SR_WR_INDEX_ADDRESS     (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
199 #define DST_WATERMARK_ADDRESS   (scn->targetdef->d_DST_WATERMARK_ADDRESS)
200 #define SOC_POWER_REG_OFFSET    (scn->targetdef->d_SOC_POWER_REG_OFFSET)
201 /* end */
202 
203 /* copy_engine.c */
204 /* end */
205 /* PLL start */
206 #define EFUSE_OFFSET              (scn->targetdef->d_EFUSE_OFFSET)
207 #define EFUSE_XTAL_SEL_MSB        (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
208 #define EFUSE_XTAL_SEL_LSB        (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
209 #define EFUSE_XTAL_SEL_MASK       (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
210 #define BB_PLL_CONFIG_OFFSET      (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
211 #define BB_PLL_CONFIG_OUTDIV_MSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
212 #define BB_PLL_CONFIG_OUTDIV_LSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
213 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
214 #define BB_PLL_CONFIG_FRAC_MSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
215 #define BB_PLL_CONFIG_FRAC_LSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
216 #define BB_PLL_CONFIG_FRAC_MASK   (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
217 #define WLAN_PLL_SETTLE_TIME_MSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
218 #define WLAN_PLL_SETTLE_TIME_LSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
219 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
220 #define WLAN_PLL_SETTLE_OFFSET    (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
221 #define WLAN_PLL_SETTLE_SW_MASK   (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
222 #define WLAN_PLL_SETTLE_RSTMASK   (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
223 #define WLAN_PLL_SETTLE_RESET     (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
224 #define WLAN_PLL_CONTROL_NOPWD_MSB  \
225 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
226 #define WLAN_PLL_CONTROL_NOPWD_LSB  \
227 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
228 #define WLAN_PLL_CONTROL_NOPWD_MASK \
229 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
230 #define WLAN_PLL_CONTROL_BYPASS_MSB \
231 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
232 #define WLAN_PLL_CONTROL_BYPASS_LSB \
233 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
234 #define WLAN_PLL_CONTROL_BYPASS_MASK \
235 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
236 #define WLAN_PLL_CONTROL_BYPASS_RESET \
237 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
238 #define WLAN_PLL_CONTROL_CLK_SEL_MSB \
239 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
240 #define WLAN_PLL_CONTROL_CLK_SEL_LSB \
241 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
242 #define WLAN_PLL_CONTROL_CLK_SEL_MASK \
243 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
244 #define WLAN_PLL_CONTROL_CLK_SEL_RESET \
245 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
246 #define WLAN_PLL_CONTROL_REFDIV_MSB \
247 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
248 #define WLAN_PLL_CONTROL_REFDIV_LSB \
249 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
250 #define WLAN_PLL_CONTROL_REFDIV_MASK \
251 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
252 #define WLAN_PLL_CONTROL_REFDIV_RESET \
253 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
254 #define WLAN_PLL_CONTROL_DIV_MSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
255 #define WLAN_PLL_CONTROL_DIV_LSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
256 #define WLAN_PLL_CONTROL_DIV_MASK  (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
257 #define WLAN_PLL_CONTROL_DIV_RESET \
258 	(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
259 #define WLAN_PLL_CONTROL_OFFSET    (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
260 #define WLAN_PLL_CONTROL_SW_MASK   (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
261 #define WLAN_PLL_CONTROL_RSTMASK   (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
262 #define WLAN_PLL_CONTROL_RESET     (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
263 #define SOC_CORE_CLK_CTRL_OFFSET   (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
264 #define SOC_CORE_CLK_CTRL_DIV_MSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
265 #define SOC_CORE_CLK_CTRL_DIV_LSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
266 #define SOC_CORE_CLK_CTRL_DIV_MASK \
267 	(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
268 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \
269 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
270 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \
271 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
272 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \
273 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
274 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \
275 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
276 #define RTC_SYNC_STATUS_OFFSET      (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
277 #define SOC_CPU_CLOCK_OFFSET        (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
278 #define SOC_CPU_CLOCK_STANDARD_MSB \
279 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
280 #define SOC_CPU_CLOCK_STANDARD_LSB \
281 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
282 #define SOC_CPU_CLOCK_STANDARD_MASK \
283 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
284 /* PLL end */
285 
286 #define FW_CPU_PLL_CONFIG \
287 	(scn->targetdef->d_FW_CPU_PLL_CONFIG)
288 
289 #define WIFICMN_PCIE_BAR_REG_ADDRESS \
290 	(sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS)
291 
292     /* htt tx */
293 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \
294 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK)
295 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \
296 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK)
297 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \
298 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK)
299 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \
300 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK)
301 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB  \
302 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB)
303 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB  \
304 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB)
305 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB  \
306 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB)
307 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB  \
308 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB)
309 
310 #define CE_CMD_ADDRESS            \
311 	(scn->targetdef->d_CE_CMD_ADDRESS)
312 #define CE_CMD_HALT_MASK          \
313 	(scn->targetdef->d_CE_CMD_HALT_MASK)
314 #define CE_CMD_HALT_STATUS_MASK   \
315 	(scn->targetdef->d_CE_CMD_HALT_STATUS_MASK)
316 #define CE_CMD_HALT_STATUS_LSB    \
317 	(scn->targetdef->d_CE_CMD_HALT_STATUS_LSB)
318 
319 #define SI_CONFIG_ERR_INT_MASK       \
320 	(scn->targetdef->d_SI_CONFIG_ERR_INT_MASK)
321 #define SI_CONFIG_ERR_INT_LSB        \
322 	(scn->targetdef->d_SI_CONFIG_ERR_INT_LSB)
323 #define GPIO_ENABLE_W1TS_LOW_ADDRESS \
324 	(scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS)
325 #define GPIO_PIN0_CONFIG_LSB         \
326 	(scn->targetdef->d_GPIO_PIN0_CONFIG_LSB)
327 #define GPIO_PIN0_PAD_PULL_LSB       \
328 	(scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB)
329 #define GPIO_PIN0_PAD_PULL_MASK      \
330 	(scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK)
331 
332 #define SOC_CHIP_ID_REVISION_MSB \
333 	(scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB)
334 
335 #define FW_AXI_MSI_ADDR                \
336 	(scn->targetdef->d_FW_AXI_MSI_ADDR)
337 #define FW_AXI_MSI_DATA                \
338 	(scn->targetdef->d_FW_AXI_MSI_DATA)
339 #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \
340 	(scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS)
341 #define FPGA_VERSION_ADDRESS           \
342 	(scn->targetdef->d_FPGA_VERSION_ADDRESS)
343 
344 /* SET macros */
345 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \
346 	(((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
347 	    WLAN_SYSTEM_SLEEP_DISABLE_MASK)
348 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \
349 	(((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
350 #define SI_CONFIG_I2C_SET(x)  (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
351 #define SI_CONFIG_POS_SAMPLE_SET(x) \
352 	(((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
353 #define SI_CONFIG_INACTIVE_CLK_SET(x) \
354 	(((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
355 #define SI_CONFIG_INACTIVE_DATA_SET(x) \
356 	(((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
357 #define SI_CONFIG_DIVIDER_SET(x) \
358 	(((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
359 #define SI_CS_START_SET(x)  (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
360 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
361 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
362 #define LPO_CAL_ENABLE_SET(x) \
363 	(((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
364 #define CPU_CLOCK_STANDARD_SET(x) \
365 	(((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
366 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \
367 	(((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
368 /* copy_engine.c */
369 /* end */
370 /* PLL start */
371 #define EFUSE_XTAL_SEL_GET(x) \
372 	(((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB)
373 #define EFUSE_XTAL_SEL_SET(x) \
374 	(((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK)
375 #define BB_PLL_CONFIG_OUTDIV_GET(x) \
376 	(((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB)
377 #define BB_PLL_CONFIG_OUTDIV_SET(x) \
378 	(((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK)
379 #define BB_PLL_CONFIG_FRAC_GET(x) \
380 	(((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
381 #define BB_PLL_CONFIG_FRAC_SET(x) \
382 	(((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
383 #define WLAN_PLL_SETTLE_TIME_GET(x) \
384 	(((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
385 #define WLAN_PLL_SETTLE_TIME_SET(x) \
386 	(((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
387 #define WLAN_PLL_CONTROL_NOPWD_GET(x) \
388 	(((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
389 #define WLAN_PLL_CONTROL_NOPWD_SET(x) \
390 	(((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
391 #define WLAN_PLL_CONTROL_BYPASS_GET(x) \
392 	(((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
393 #define WLAN_PLL_CONTROL_BYPASS_SET(x) \
394 	(((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
395 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \
396 	(((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB)
397 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \
398 	(((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK)
399 #define WLAN_PLL_CONTROL_REFDIV_GET(x) \
400 	(((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
401 #define WLAN_PLL_CONTROL_REFDIV_SET(x) \
402 	(((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
403 #define WLAN_PLL_CONTROL_DIV_GET(x) \
404 	(((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
405 #define WLAN_PLL_CONTROL_DIV_SET(x) \
406 	(((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
407 #define SOC_CORE_CLK_CTRL_DIV_GET(x) \
408 	(((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
409 #define SOC_CORE_CLK_CTRL_DIV_SET(x) \
410 	(((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
411 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \
412 	(((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \
413 		RTC_SYNC_STATUS_PLL_CHANGING_LSB)
414 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \
415 	(((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \
416 		RTC_SYNC_STATUS_PLL_CHANGING_MASK)
417 #define SOC_CPU_CLOCK_STANDARD_GET(x) \
418 	(((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
419 #define SOC_CPU_CLOCK_STANDARD_SET(x) \
420 	(((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
421 /* PLL end */
422 #define WLAN_GPIO_PIN0_CONFIG_SET(x)   \
423 	(((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
424 #define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \
425 	(((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK)
426 #define SI_CONFIG_ERR_INT_SET(x)       \
427 	(((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
428 
429 #ifdef QCA_WIFI_3_0_ADRASTEA
430 #define Q6_ENABLE_REGISTER_0 \
431 	(scn->targetdef->d_Q6_ENABLE_REGISTER_0)
432 #define Q6_ENABLE_REGISTER_1 \
433 	(scn->targetdef->d_Q6_ENABLE_REGISTER_1)
434 #define Q6_CAUSE_REGISTER_0 \
435 	(scn->targetdef->d_Q6_CAUSE_REGISTER_0)
436 #define Q6_CAUSE_REGISTER_1 \
437 	(scn->targetdef->d_Q6_CAUSE_REGISTER_1)
438 #define Q6_CLEAR_REGISTER_0 \
439 	(scn->targetdef->d_Q6_CLEAR_REGISTER_0)
440 #define Q6_CLEAR_REGISTER_1 \
441 	(scn->targetdef->d_Q6_CLEAR_REGISTER_1)
442 #endif
443 
444 #ifdef CONFIG_BYPASS_QMI
445 #define BYPASS_QMI_TEMP_REGISTER \
446 	(scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER)
447 #endif
448 
449 #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
450 #define DESC_DATA_FLAG_MASK        (scn->hostdef->d_DESC_DATA_FLAG_MASK)
451 #define MUX_ID_MASK                (scn->hostdef->d_MUX_ID_MASK)
452 #define TRANSACTION_ID_MASK        (scn->hostdef->d_TRANSACTION_ID_MASK)
453 #define HOST_CE_COUNT              (scn->hostdef->d_HOST_CE_COUNT)
454 #define ENABLE_MSI                 (scn->hostdef->d_ENABLE_MSI)
455 #define INT_STATUS_ENABLE_ERROR_LSB \
456 	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
457 #define INT_STATUS_ENABLE_ERROR_MASK \
458 	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
459 #define INT_STATUS_ENABLE_CPU_LSB  (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
460 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
461 #define INT_STATUS_ENABLE_COUNTER_LSB \
462 	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
463 #define INT_STATUS_ENABLE_COUNTER_MASK \
464 	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
465 #define INT_STATUS_ENABLE_MBOX_DATA_LSB \
466 	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
467 #define INT_STATUS_ENABLE_MBOX_DATA_MASK \
468 	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
469 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \
470 	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
471 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \
472 	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
473 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \
474 	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
475 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \
476 	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
477 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \
478 	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
479 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \
480 	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
481 #define INT_STATUS_ENABLE_ADDRESS \
482 	(scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
483 #define CPU_INT_STATUS_ENABLE_BIT_LSB \
484 	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
485 #define CPU_INT_STATUS_ENABLE_BIT_MASK \
486 	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
487 #define HOST_INT_STATUS_ADDRESS     (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
488 #define CPU_INT_STATUS_ADDRESS      (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
489 #define ERROR_INT_STATUS_ADDRESS    (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
490 #define ERROR_INT_STATUS_WAKEUP_MASK \
491 	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
492 #define ERROR_INT_STATUS_WAKEUP_LSB \
493 	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
494 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \
495 	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
496 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \
497 	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
498 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \
499 	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
500 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \
501 	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
502 #define COUNT_DEC_ADDRESS          (scn->hostdef->d_COUNT_DEC_ADDRESS)
503 #define HOST_INT_STATUS_CPU_MASK   (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
504 #define HOST_INT_STATUS_CPU_LSB    (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
505 #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
506 #define HOST_INT_STATUS_ERROR_LSB  (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
507 #define HOST_INT_STATUS_COUNTER_MASK \
508 	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
509 #define HOST_INT_STATUS_COUNTER_LSB \
510 	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
511 #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
512 #define WINDOW_DATA_ADDRESS        (scn->hostdef->d_WINDOW_DATA_ADDRESS)
513 #define WINDOW_READ_ADDR_ADDRESS   (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
514 #define WINDOW_WRITE_ADDR_ADDRESS  (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
515 #define SOC_GLOBAL_RESET_ADDRESS   (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
516 #define RTC_STATE_ADDRESS          (scn->hostdef->d_RTC_STATE_ADDRESS)
517 #define RTC_STATE_COLD_RESET_MASK  (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
518 #define PCIE_LOCAL_BASE_ADDRESS    (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
519 #define PCIE_SOC_WAKE_RESET        (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
520 #define PCIE_SOC_WAKE_ADDRESS      (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
521 #define PCIE_SOC_WAKE_V_MASK       (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
522 #define RTC_STATE_V_MASK           (scn->hostdef->d_RTC_STATE_V_MASK)
523 #define RTC_STATE_V_LSB            (scn->hostdef->d_RTC_STATE_V_LSB)
524 #define FW_IND_EVENT_PENDING       (scn->hostdef->d_FW_IND_EVENT_PENDING)
525 #define FW_IND_INITIALIZED         (scn->hostdef->d_FW_IND_INITIALIZED)
526 #define FW_IND_HELPER              (scn->hostdef->d_FW_IND_HELPER)
527 #define RTC_STATE_V_ON             (scn->hostdef->d_RTC_STATE_V_ON)
528 
529 #define FW_IND_HOST_READY          (scn->hostdef->d_FW_IND_HOST_READY)
530 
531 #if defined(SDIO_3_0)
532 #define HOST_INT_STATUS_MBOX_DATA_MASK \
533 	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
534 #define HOST_INT_STATUS_MBOX_DATA_LSB \
535 	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
536 #endif
537 
538 #if !defined(SOC_PCIE_BASE_ADDRESS)
539 #define SOC_PCIE_BASE_ADDRESS 0
540 #endif
541 
542 #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS)
543 #define PCIE_SOC_RDY_STATUS_ADDRESS 0
544 #define PCIE_SOC_RDY_STATUS_BAR_MASK 0
545 #endif
546 
547 #if !defined(MSI_MAGIC_ADR_ADDRESS)
548 #define MSI_MAGIC_ADR_ADDRESS 0
549 #define MSI_MAGIC_ADDRESS 0
550 #endif
551 
552 /* SET/GET macros */
553 #define INT_STATUS_ENABLE_ERROR_SET(x) \
554 	(((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
555 #define INT_STATUS_ENABLE_CPU_SET(x) \
556 	(((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
557 #define INT_STATUS_ENABLE_COUNTER_SET(x) \
558 	(((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \
559 		INT_STATUS_ENABLE_COUNTER_MASK)
560 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \
561 	(((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \
562 	 INT_STATUS_ENABLE_MBOX_DATA_MASK)
563 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \
564 	(((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \
565 		CPU_INT_STATUS_ENABLE_BIT_MASK)
566 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \
567 	(((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \
568 		ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
569 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \
570 	(((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \
571 		ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
572 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \
573 	(((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \
574 		COUNTER_INT_STATUS_ENABLE_BIT_MASK)
575 #define ERROR_INT_STATUS_WAKEUP_GET(x) \
576 	(((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \
577 		ERROR_INT_STATUS_WAKEUP_LSB)
578 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \
579 	(((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \
580 		ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
581 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \
582 	(((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \
583 		ERROR_INT_STATUS_TX_OVERFLOW_LSB)
584 #define HOST_INT_STATUS_CPU_GET(x) \
585 	(((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
586 #define HOST_INT_STATUS_ERROR_GET(x) \
587 	(((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
588 #define HOST_INT_STATUS_COUNTER_GET(x) \
589 	(((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
590 #define RTC_STATE_V_GET(x) \
591 	(((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
592 #if defined(SDIO_3_0)
593 #define HOST_INT_STATUS_MBOX_DATA_GET(x) \
594 	(((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \
595 		HOST_INT_STATUS_MBOX_DATA_LSB)
596 #endif
597 
598 #define INVALID_REG_LOC_DUMMY_DATA 0xAA
599 
600 #define AR6320_CORE_CLK_DIV_ADDR        0x403fa8
601 #define AR6320_CPU_PLL_INIT_DONE_ADDR   0x403fd0
602 #define AR6320_CPU_SPEED_ADDR           0x403fa4
603 #define AR6320V2_CORE_CLK_DIV_ADDR      0x403fd8
604 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0
605 #define AR6320V2_CPU_SPEED_ADDR         0x403fd4
606 #define AR6320V3_CORE_CLK_DIV_ADDR      0x404028
607 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020
608 #define AR6320V3_CPU_SPEED_ADDR         0x404024
609 
610 enum a_refclk_speed_t {
611 	SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
612 	SOC_REFCLK_48_MHZ = 0,
613 	SOC_REFCLK_19_2_MHZ = 1,
614 	SOC_REFCLK_24_MHZ = 2,
615 	SOC_REFCLK_26_MHZ = 3,
616 	SOC_REFCLK_37_4_MHZ = 4,
617 	SOC_REFCLK_38_4_MHZ = 5,
618 	SOC_REFCLK_40_MHZ = 6,
619 	SOC_REFCLK_52_MHZ = 7,
620 };
621 
622 #define A_REFCLK_UNKNOWN    SOC_REFCLK_UNKNOWN
623 #define A_REFCLK_48_MHZ     SOC_REFCLK_48_MHZ
624 #define A_REFCLK_19_2_MHZ   SOC_REFCLK_19_2_MHZ
625 #define A_REFCLK_24_MHZ     SOC_REFCLK_24_MHZ
626 #define A_REFCLK_26_MHZ     SOC_REFCLK_26_MHZ
627 #define A_REFCLK_37_4_MHZ   SOC_REFCLK_37_4_MHZ
628 #define A_REFCLK_38_4_MHZ   SOC_REFCLK_38_4_MHZ
629 #define A_REFCLK_40_MHZ     SOC_REFCLK_40_MHZ
630 #define A_REFCLK_52_MHZ     SOC_REFCLK_52_MHZ
631 
632 #define TARGET_CPU_FREQ 176000000
633 
634 struct wlan_pll_s {
635 	uint32_t refdiv;
636 	uint32_t div;
637 	uint32_t rnfrac;
638 	uint32_t outdiv;
639 };
640 
641 struct cmnos_clock_s {
642 	enum a_refclk_speed_t refclk_speed;
643 	uint32_t refclk_hz;
644 	uint32_t pll_settling_time;     /* 50us */
645 	struct wlan_pll_s wlan_pll;
646 };
647 
648 struct tgt_reg_section {
649 	uint32_t start_addr;
650 	uint32_t end_addr;
651 };
652 
653 struct tgt_reg_table {
654 	const struct tgt_reg_section *section;
655 	uint32_t section_size;
656 };
657 
658 struct hif_softc;
659 void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type);
660 void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type);
661 
662 #endif /* _REGTABLE_IPCIE_H_ */
663