1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name #ifndef TARGET_REG_INIT_H 21*5113495bSYour Name #define TARGET_REG_INIT_H 22*5113495bSYour Name #include "reg_struct.h" 23*5113495bSYour Name #include "targaddrs.h" 24*5113495bSYour Name /*** WARNING : Add to the end of the TABLE! do not change the order ****/ 25*5113495bSYour Name struct targetdef_s; 26*5113495bSYour Name 27*5113495bSYour Name 28*5113495bSYour Name 29*5113495bSYour Name #define ATH_UNSUPPORTED_REG_OFFSET UNSUPPORTED_REGISTER_OFFSET 30*5113495bSYour Name #define ATH_SUPPORTED_BY_TARGET(reg_offset) \ 31*5113495bSYour Name ((reg_offset) != ATH_UNSUPPORTED_REG_OFFSET) 32*5113495bSYour Name 33*5113495bSYour Name #if defined(MY_TARGET_DEF) 34*5113495bSYour Name 35*5113495bSYour Name /* Cross-platform compatibility */ 36*5113495bSYour Name #if !defined(SOC_RESET_CONTROL_OFFSET) && defined(RESET_CONTROL_OFFSET) 37*5113495bSYour Name #define SOC_RESET_CONTROL_OFFSET RESET_CONTROL_OFFSET 38*5113495bSYour Name #endif 39*5113495bSYour Name 40*5113495bSYour Name #if !defined(CLOCK_GPIO_OFFSET) 41*5113495bSYour Name #define CLOCK_GPIO_OFFSET ATH_UNSUPPORTED_REG_OFFSET 42*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 43*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 44*5113495bSYour Name #endif 45*5113495bSYour Name 46*5113495bSYour Name #if !defined(WLAN_MAC_BASE_ADDRESS) 47*5113495bSYour Name #define WLAN_MAC_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 48*5113495bSYour Name #endif 49*5113495bSYour Name 50*5113495bSYour Name #if !defined(CE0_BASE_ADDRESS) 51*5113495bSYour Name #define CE0_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 52*5113495bSYour Name #define CE1_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 53*5113495bSYour Name #define CE_COUNT 0 54*5113495bSYour Name #endif 55*5113495bSYour Name 56*5113495bSYour Name #if !defined(MSI_NUM_REQUEST) 57*5113495bSYour Name #define MSI_NUM_REQUEST 0 58*5113495bSYour Name #define MSI_ASSIGN_FW 0 59*5113495bSYour Name #define MSI_ASSIGN_CE_INITIAL 0 60*5113495bSYour Name #endif 61*5113495bSYour Name 62*5113495bSYour Name #if !defined(FW_INDICATOR_ADDRESS) 63*5113495bSYour Name #define FW_INDICATOR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 64*5113495bSYour Name #endif 65*5113495bSYour Name 66*5113495bSYour Name #if !defined(FW_CPU_PLL_CONFIG) 67*5113495bSYour Name #define FW_CPU_PLL_CONFIG ATH_UNSUPPORTED_REG_OFFSET 68*5113495bSYour Name #endif 69*5113495bSYour Name 70*5113495bSYour Name #if !defined(DRAM_BASE_ADDRESS) 71*5113495bSYour Name #define DRAM_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 72*5113495bSYour Name #endif 73*5113495bSYour Name 74*5113495bSYour Name #if !defined(SOC_CORE_BASE_ADDRESS) 75*5113495bSYour Name #define SOC_CORE_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 76*5113495bSYour Name #endif 77*5113495bSYour Name 78*5113495bSYour Name #if !defined(CPU_INTR_ADDRESS) 79*5113495bSYour Name #define CPU_INTR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 80*5113495bSYour Name #endif 81*5113495bSYour Name 82*5113495bSYour Name #if !defined(SOC_LF_TIMER_CONTROL0_ADDRESS) 83*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 84*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK ATH_UNSUPPORTED_REG_OFFSET 85*5113495bSYour Name #endif 86*5113495bSYour Name 87*5113495bSYour Name #if !defined(SOC_LF_TIMER_STATUS0_ADDRESS) 88*5113495bSYour Name #define SOC_LF_TIMER_STATUS0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 89*5113495bSYour Name #endif 90*5113495bSYour Name 91*5113495bSYour Name #if !defined(SOC_RESET_CONTROL_ADDRESS) 92*5113495bSYour Name #define SOC_RESET_CONTROL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 93*5113495bSYour Name #define SOC_RESET_CONTROL_CE_RST_MASK ATH_UNSUPPORTED_REG_OFFSET 94*5113495bSYour Name #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK ATH_UNSUPPORTED_REG_OFFSET 95*5113495bSYour Name #endif 96*5113495bSYour Name 97*5113495bSYour Name #if !defined(CORE_CTRL_ADDRESS) 98*5113495bSYour Name #define CORE_CTRL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 99*5113495bSYour Name #define CORE_CTRL_CPU_INTR_MASK 0 100*5113495bSYour Name #endif 101*5113495bSYour Name 102*5113495bSYour Name #if !defined(PCIE_INTR_ENABLE_ADDRESS) 103*5113495bSYour Name #define PCIE_INTR_ENABLE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 104*5113495bSYour Name #define PCIE_INTR_CLR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 105*5113495bSYour Name #define PCIE_INTR_FIRMWARE_MASK ATH_UNSUPPORTED_REG_OFFSET 106*5113495bSYour Name #define PCIE_INTR_CE_MASK_ALL ATH_UNSUPPORTED_REG_OFFSET 107*5113495bSYour Name #define PCIE_INTR_CAUSE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 108*5113495bSYour Name #endif 109*5113495bSYour Name 110*5113495bSYour Name #if !defined(WIFICMN_PCIE_BAR_REG_ADDRESS) 111*5113495bSYour Name #define WIFICMN_PCIE_BAR_REG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 112*5113495bSYour Name #endif 113*5113495bSYour Name 114*5113495bSYour Name #if !defined(WIFICMN_INT_STATUS_ADDRESS) 115*5113495bSYour Name #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 116*5113495bSYour Name #endif 117*5113495bSYour Name 118*5113495bSYour Name #if !defined(FW_AXI_MSI_ADDR) 119*5113495bSYour Name #define FW_AXI_MSI_ADDR ATH_UNSUPPORTED_REG_OFFSET 120*5113495bSYour Name #endif 121*5113495bSYour Name 122*5113495bSYour Name #if !defined(FW_AXI_MSI_DATA) 123*5113495bSYour Name #define FW_AXI_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET 124*5113495bSYour Name #endif 125*5113495bSYour Name 126*5113495bSYour Name #if !defined(WLAN_SUBSYSTEM_CORE_ID_ADDRESS) 127*5113495bSYour Name #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 128*5113495bSYour Name #endif 129*5113495bSYour Name 130*5113495bSYour Name #if !defined(FPGA_VERSION_ADDRESS) 131*5113495bSYour Name #define FPGA_VERSION_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 132*5113495bSYour Name #endif 133*5113495bSYour Name 134*5113495bSYour Name #if !defined(SI_CONFIG_ADDRESS) 135*5113495bSYour Name #define SI_CONFIG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 136*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_LSB 0 137*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_MASK 0 138*5113495bSYour Name #define SI_CONFIG_I2C_LSB 0 139*5113495bSYour Name #define SI_CONFIG_I2C_MASK 0 140*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_LSB 0 141*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_MASK 0 142*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_LSB 0 143*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_MASK 0 144*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_LSB 0 145*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_MASK 0 146*5113495bSYour Name #define SI_CONFIG_DIVIDER_LSB 0 147*5113495bSYour Name #define SI_CONFIG_DIVIDER_MASK 0 148*5113495bSYour Name #define SI_CONFIG_OFFSET 0 149*5113495bSYour Name #define SI_TX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET 150*5113495bSYour Name #define SI_TX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET 151*5113495bSYour Name #define SI_RX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET 152*5113495bSYour Name #define SI_RX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET 153*5113495bSYour Name #define SI_CS_OFFSET ATH_UNSUPPORTED_REG_OFFSET 154*5113495bSYour Name #define SI_CS_DONE_ERR_MASK 0 155*5113495bSYour Name #define SI_CS_DONE_INT_MASK 0 156*5113495bSYour Name #define SI_CS_START_LSB 0 157*5113495bSYour Name #define SI_CS_START_MASK 0 158*5113495bSYour Name #define SI_CS_RX_CNT_LSB 0 159*5113495bSYour Name #define SI_CS_RX_CNT_MASK 0 160*5113495bSYour Name #define SI_CS_TX_CNT_LSB 0 161*5113495bSYour Name #define SI_CS_TX_CNT_MASK 0 162*5113495bSYour Name #endif 163*5113495bSYour Name 164*5113495bSYour Name #ifndef SI_BASE_ADDRESS 165*5113495bSYour Name #define SI_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 166*5113495bSYour Name #endif 167*5113495bSYour Name 168*5113495bSYour Name #ifndef WLAN_GPIO_PIN10_ADDRESS 169*5113495bSYour Name #define WLAN_GPIO_PIN10_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 170*5113495bSYour Name #endif 171*5113495bSYour Name 172*5113495bSYour Name #ifndef WLAN_GPIO_PIN11_ADDRESS 173*5113495bSYour Name #define WLAN_GPIO_PIN11_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 174*5113495bSYour Name #endif 175*5113495bSYour Name 176*5113495bSYour Name #ifndef WLAN_GPIO_PIN12_ADDRESS 177*5113495bSYour Name #define WLAN_GPIO_PIN12_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 178*5113495bSYour Name #endif 179*5113495bSYour Name 180*5113495bSYour Name #ifndef WLAN_GPIO_PIN13_ADDRESS 181*5113495bSYour Name #define WLAN_GPIO_PIN13_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 182*5113495bSYour Name #endif 183*5113495bSYour Name 184*5113495bSYour Name #ifndef WIFICMN_INT_STATUS_ADDRESS 185*5113495bSYour Name #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 186*5113495bSYour Name #endif 187*5113495bSYour Name 188*5113495bSYour Name static struct targetdef_s my_target_def = { 189*5113495bSYour Name .d_RTC_SOC_BASE_ADDRESS = RTC_SOC_BASE_ADDRESS, 190*5113495bSYour Name .d_RTC_WMAC_BASE_ADDRESS = RTC_WMAC_BASE_ADDRESS, 191*5113495bSYour Name .d_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, 192*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, 193*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = WLAN_SYSTEM_SLEEP_DISABLE_LSB, 194*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = WLAN_SYSTEM_SLEEP_DISABLE_MASK, 195*5113495bSYour Name .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET, 196*5113495bSYour Name .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK, 197*5113495bSYour Name .d_RESET_CONTROL_OFFSET = SOC_RESET_CONTROL_OFFSET, 198*5113495bSYour Name .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK, 199*5113495bSYour Name .d_WLAN_RESET_CONTROL_OFFSET = WLAN_RESET_CONTROL_OFFSET, 200*5113495bSYour Name .d_WLAN_RESET_CONTROL_COLD_RST_MASK = WLAN_RESET_CONTROL_COLD_RST_MASK, 201*5113495bSYour Name .d_WLAN_RESET_CONTROL_WARM_RST_MASK = WLAN_RESET_CONTROL_WARM_RST_MASK, 202*5113495bSYour Name .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS, 203*5113495bSYour Name .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET, 204*5113495bSYour Name .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET, 205*5113495bSYour Name .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK, 206*5113495bSYour Name .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK, 207*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB, 208*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK, 209*5113495bSYour Name .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB, 210*5113495bSYour Name .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK, 211*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB, 212*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK, 213*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB, 214*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK, 215*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB, 216*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK, 217*5113495bSYour Name .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB, 218*5113495bSYour Name .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK, 219*5113495bSYour Name .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS, 220*5113495bSYour Name .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET, 221*5113495bSYour Name .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET, 222*5113495bSYour Name .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET, 223*5113495bSYour Name .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET, 224*5113495bSYour Name .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET, 225*5113495bSYour Name .d_SI_CS_OFFSET = SI_CS_OFFSET, 226*5113495bSYour Name .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK, 227*5113495bSYour Name .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK, 228*5113495bSYour Name .d_SI_CS_START_LSB = SI_CS_START_LSB, 229*5113495bSYour Name .d_SI_CS_START_MASK = SI_CS_START_MASK, 230*5113495bSYour Name .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB, 231*5113495bSYour Name .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK, 232*5113495bSYour Name .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB, 233*5113495bSYour Name .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK, 234*5113495bSYour Name .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ, 235*5113495bSYour Name .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ, 236*5113495bSYour Name .d_MBOX_BASE_ADDRESS = MBOX_BASE_ADDRESS, 237*5113495bSYour Name .d_LOCAL_SCRATCH_OFFSET = LOCAL_SCRATCH_OFFSET, 238*5113495bSYour Name .d_CPU_CLOCK_OFFSET = CPU_CLOCK_OFFSET, 239*5113495bSYour Name .d_GPIO_PIN10_OFFSET = GPIO_PIN10_OFFSET, 240*5113495bSYour Name .d_GPIO_PIN11_OFFSET = GPIO_PIN11_OFFSET, 241*5113495bSYour Name .d_GPIO_PIN12_OFFSET = GPIO_PIN12_OFFSET, 242*5113495bSYour Name .d_GPIO_PIN13_OFFSET = GPIO_PIN13_OFFSET, 243*5113495bSYour Name .d_CLOCK_GPIO_OFFSET = CLOCK_GPIO_OFFSET, 244*5113495bSYour Name .d_CPU_CLOCK_STANDARD_LSB = CPU_CLOCK_STANDARD_LSB, 245*5113495bSYour Name .d_CPU_CLOCK_STANDARD_MASK = CPU_CLOCK_STANDARD_MASK, 246*5113495bSYour Name .d_LPO_CAL_ENABLE_LSB = LPO_CAL_ENABLE_LSB, 247*5113495bSYour Name .d_LPO_CAL_ENABLE_MASK = LPO_CAL_ENABLE_MASK, 248*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = CLOCK_GPIO_BT_CLK_OUT_EN_LSB, 249*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = CLOCK_GPIO_BT_CLK_OUT_EN_MASK, 250*5113495bSYour Name .d_ANALOG_INTF_BASE_ADDRESS = ANALOG_INTF_BASE_ADDRESS, 251*5113495bSYour Name .d_WLAN_MAC_BASE_ADDRESS = WLAN_MAC_BASE_ADDRESS, 252*5113495bSYour Name .d_FW_INDICATOR_ADDRESS = FW_INDICATOR_ADDRESS, 253*5113495bSYour Name .d_FW_CPU_PLL_CONFIG = FW_CPU_PLL_CONFIG, 254*5113495bSYour Name .d_DRAM_BASE_ADDRESS = DRAM_BASE_ADDRESS, 255*5113495bSYour Name .d_SOC_CORE_BASE_ADDRESS = SOC_CORE_BASE_ADDRESS, 256*5113495bSYour Name .d_CORE_CTRL_ADDRESS = CORE_CTRL_ADDRESS, 257*5113495bSYour Name .d_CE_COUNT = CE_COUNT, 258*5113495bSYour Name .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, 259*5113495bSYour Name .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, 260*5113495bSYour Name .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, 261*5113495bSYour Name .d_PCIE_INTR_ENABLE_ADDRESS = PCIE_INTR_ENABLE_ADDRESS, 262*5113495bSYour Name .d_PCIE_INTR_CLR_ADDRESS = PCIE_INTR_CLR_ADDRESS, 263*5113495bSYour Name .d_PCIE_INTR_FIRMWARE_MASK = PCIE_INTR_FIRMWARE_MASK, 264*5113495bSYour Name .d_PCIE_INTR_CE_MASK_ALL = PCIE_INTR_CE_MASK_ALL, 265*5113495bSYour Name .d_CORE_CTRL_CPU_INTR_MASK = CORE_CTRL_CPU_INTR_MASK, 266*5113495bSYour Name .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, 267*5113495bSYour Name /* htt_rx.c */ 268*5113495bSYour Name /* htt tx */ 269*5113495bSYour Name .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 270*5113495bSYour Name = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK, 271*5113495bSYour Name .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 272*5113495bSYour Name = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK, 273*5113495bSYour Name .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 274*5113495bSYour Name = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK, 275*5113495bSYour Name .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 276*5113495bSYour Name = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK, 277*5113495bSYour Name .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 278*5113495bSYour Name = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB, 279*5113495bSYour Name .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 280*5113495bSYour Name = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB, 281*5113495bSYour Name .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 282*5113495bSYour Name = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB, 283*5113495bSYour Name .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 284*5113495bSYour Name = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB, 285*5113495bSYour Name /* copy_engine.c */ 286*5113495bSYour Name .d_SR_WR_INDEX_ADDRESS = SR_WR_INDEX_ADDRESS, 287*5113495bSYour Name .d_DST_WATERMARK_ADDRESS = DST_WATERMARK_ADDRESS, 288*5113495bSYour Name 289*5113495bSYour Name .d_PCIE_INTR_CAUSE_ADDRESS = PCIE_INTR_CAUSE_ADDRESS, 290*5113495bSYour Name .d_SOC_RESET_CONTROL_ADDRESS = SOC_RESET_CONTROL_ADDRESS, 291*5113495bSYour Name .d_SOC_RESET_CONTROL_CE_RST_MASK = SOC_RESET_CONTROL_CE_RST_MASK, 292*5113495bSYour Name .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 293*5113495bSYour Name = SOC_RESET_CONTROL_CPU_WARM_RST_MASK, 294*5113495bSYour Name .d_CPU_INTR_ADDRESS = CPU_INTR_ADDRESS, 295*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ADDRESS = SOC_LF_TIMER_CONTROL0_ADDRESS, 296*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 297*5113495bSYour Name = SOC_LF_TIMER_CONTROL0_ENABLE_MASK, 298*5113495bSYour Name .d_SOC_LF_TIMER_STATUS0_ADDRESS = SOC_LF_TIMER_STATUS0_ADDRESS, 299*5113495bSYour Name .d_SI_CONFIG_ERR_INT_MASK = SI_CONFIG_ERR_INT_MASK, 300*5113495bSYour Name .d_SI_CONFIG_ERR_INT_LSB = SI_CONFIG_ERR_INT_LSB, 301*5113495bSYour Name .d_GPIO_ENABLE_W1TS_LOW_ADDRESS = GPIO_ENABLE_W1TS_LOW_ADDRESS, 302*5113495bSYour Name .d_GPIO_PIN0_CONFIG_LSB = GPIO_PIN0_CONFIG_LSB, 303*5113495bSYour Name .d_GPIO_PIN0_PAD_PULL_LSB = GPIO_PIN0_PAD_PULL_LSB, 304*5113495bSYour Name .d_GPIO_PIN0_PAD_PULL_MASK = GPIO_PIN0_PAD_PULL_MASK, 305*5113495bSYour Name .d_SOC_CHIP_ID_ADDRESS = SOC_CHIP_ID_ADDRESS, 306*5113495bSYour Name .d_SOC_CHIP_ID_REVISION_MASK = SOC_CHIP_ID_REVISION_MASK, 307*5113495bSYour Name .d_SOC_CHIP_ID_REVISION_LSB = SOC_CHIP_ID_REVISION_LSB, 308*5113495bSYour Name .d_SOC_CHIP_ID_REVISION_MSB = SOC_CHIP_ID_REVISION_MSB, 309*5113495bSYour Name .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, 310*5113495bSYour Name .d_FW_AXI_MSI_ADDR = FW_AXI_MSI_ADDR, 311*5113495bSYour Name .d_FW_AXI_MSI_DATA = FW_AXI_MSI_DATA, 312*5113495bSYour Name .d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS = WLAN_SUBSYSTEM_CORE_ID_ADDRESS, 313*5113495bSYour Name .d_WIFICMN_INT_STATUS_ADDRESS = WIFICMN_INT_STATUS_ADDRESS, 314*5113495bSYour Name }; 315*5113495bSYour Name 316*5113495bSYour Name struct targetdef_s *MY_TARGET_DEF = &my_target_def; 317*5113495bSYour Name #else 318*5113495bSYour Name #endif 319*5113495bSYour Name 320*5113495bSYour Name #if defined(MY_CEREG_DEF) 321*5113495bSYour Name 322*5113495bSYour Name #if !defined(CE_DDR_ADDRESS_FOR_RRI_LOW) 323*5113495bSYour Name #define CE_DDR_ADDRESS_FOR_RRI_LOW ATH_UNSUPPORTED_REG_OFFSET 324*5113495bSYour Name #endif 325*5113495bSYour Name #if !defined(CE_DDR_ADDRESS_FOR_RRI_HIGH) 326*5113495bSYour Name #define CE_DDR_ADDRESS_FOR_RRI_HIGH ATH_UNSUPPORTED_REG_OFFSET 327*5113495bSYour Name #endif 328*5113495bSYour Name #if !defined(SR_BA_ADDRESS_HIGH) 329*5113495bSYour Name #define SR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 330*5113495bSYour Name #endif 331*5113495bSYour Name #if !defined(DR_BA_ADDRESS_HIGH) 332*5113495bSYour Name #define DR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 333*5113495bSYour Name #endif 334*5113495bSYour Name #if !defined(CE_CMD_REGISTER) 335*5113495bSYour Name #define CE_CMD_REGISTER ATH_UNSUPPORTED_REG_OFFSET 336*5113495bSYour Name #endif 337*5113495bSYour Name #if !defined(CE_MSI_ADDRESS) 338*5113495bSYour Name #define CE_MSI_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 339*5113495bSYour Name #endif 340*5113495bSYour Name #if !defined(CE_MSI_ADDRESS_HIGH) 341*5113495bSYour Name #define CE_MSI_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 342*5113495bSYour Name #endif 343*5113495bSYour Name #if !defined(CE_MSI_DATA) 344*5113495bSYour Name #define CE_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET 345*5113495bSYour Name #endif 346*5113495bSYour Name #if !defined(CE_MSI_ENABLE_BIT) 347*5113495bSYour Name #define CE_MSI_ENABLE_BIT ATH_UNSUPPORTED_REG_OFFSET 348*5113495bSYour Name #endif 349*5113495bSYour Name #if !defined(CE_CTRL1_IDX_UPD_EN_MASK) 350*5113495bSYour Name #define CE_CTRL1_IDX_UPD_EN_MASK ATH_UNSUPPORTED_REG_OFFSET 351*5113495bSYour Name #endif 352*5113495bSYour Name #if !defined(CE_WRAPPER_DEBUG_OFFSET) 353*5113495bSYour Name #define CE_WRAPPER_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET 354*5113495bSYour Name #endif 355*5113495bSYour Name #if !defined(CE_DEBUG_OFFSET) 356*5113495bSYour Name #define CE_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET 357*5113495bSYour Name #endif 358*5113495bSYour Name #if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES) 359*5113495bSYour Name #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES ATH_UNSUPPORTED_REG_OFFSET 360*5113495bSYour Name #endif 361*5113495bSYour Name #if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS) 362*5113495bSYour Name #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS ATH_UNSUPPORTED_REG_OFFSET 363*5113495bSYour Name #endif 364*5113495bSYour Name #if !defined(HOST_IE_ADDRESS_2) 365*5113495bSYour Name #define HOST_IE_ADDRESS_2 ATH_UNSUPPORTED_REG_OFFSET 366*5113495bSYour Name #endif 367*5113495bSYour Name #if !defined(HOST_IE_ADDRESS_3) 368*5113495bSYour Name #define HOST_IE_ADDRESS_3 ATH_UNSUPPORTED_REG_OFFSET 369*5113495bSYour Name #endif 370*5113495bSYour Name #if !defined(HOST_IE_REG1_CE_LSB) 371*5113495bSYour Name #define HOST_IE_REG1_CE_LSB 0 372*5113495bSYour Name #endif 373*5113495bSYour Name #if !defined(HOST_IE_REG2_CE_LSB) 374*5113495bSYour Name #define HOST_IE_REG2_CE_LSB 0 375*5113495bSYour Name #endif 376*5113495bSYour Name #if !defined(HOST_IE_REG3_CE_LSB) 377*5113495bSYour Name #define HOST_IE_REG3_CE_LSB 0 378*5113495bSYour Name #endif 379*5113495bSYour Name #if !defined(HOST_CE_ADDRESS) 380*5113495bSYour Name #define HOST_CE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 381*5113495bSYour Name #endif 382*5113495bSYour Name #if !defined(HOST_CMEM_ADDRESS) 383*5113495bSYour Name #define HOST_CMEM_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 384*5113495bSYour Name #endif 385*5113495bSYour Name #if !defined(PMM_SCRATCH_BASE) 386*5113495bSYour Name #define PMM_SCRATCH_BASE ATH_UNSUPPORTED_REG_OFFSET 387*5113495bSYour Name #endif 388*5113495bSYour Name 389*5113495bSYour Name 390*5113495bSYour Name 391*5113495bSYour Name static struct ce_reg_def my_ce_reg_def = { 392*5113495bSYour Name /* copy_engine.c */ 393*5113495bSYour Name .d_DST_WR_INDEX_ADDRESS = DST_WR_INDEX_ADDRESS, 394*5113495bSYour Name .d_SRC_WATERMARK_ADDRESS = SRC_WATERMARK_ADDRESS, 395*5113495bSYour Name .d_SRC_WATERMARK_LOW_MASK = SRC_WATERMARK_LOW_MASK, 396*5113495bSYour Name .d_SRC_WATERMARK_HIGH_MASK = SRC_WATERMARK_HIGH_MASK, 397*5113495bSYour Name .d_DST_WATERMARK_LOW_MASK = DST_WATERMARK_LOW_MASK, 398*5113495bSYour Name .d_DST_WATERMARK_HIGH_MASK = DST_WATERMARK_HIGH_MASK, 399*5113495bSYour Name .d_CURRENT_SRRI_ADDRESS = CURRENT_SRRI_ADDRESS, 400*5113495bSYour Name .d_CURRENT_DRRI_ADDRESS = CURRENT_DRRI_ADDRESS, 401*5113495bSYour Name .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 402*5113495bSYour Name = HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 403*5113495bSYour Name .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 404*5113495bSYour Name = HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 405*5113495bSYour Name .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 406*5113495bSYour Name = HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 407*5113495bSYour Name .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK 408*5113495bSYour Name = HOST_IS_DST_RING_LOW_WATERMARK_MASK, 409*5113495bSYour Name .d_HOST_IS_ADDRESS = HOST_IS_ADDRESS, 410*5113495bSYour Name .d_MISC_IS_ADDRESS = MISC_IS_ADDRESS, 411*5113495bSYour Name .d_HOST_IS_COPY_COMPLETE_MASK = HOST_IS_COPY_COMPLETE_MASK, 412*5113495bSYour Name .d_CE_WRAPPER_BASE_ADDRESS = CE_WRAPPER_BASE_ADDRESS, 413*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 414*5113495bSYour Name = CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, 415*5113495bSYour Name .d_CE_DDR_ADDRESS_FOR_RRI_LOW = CE_DDR_ADDRESS_FOR_RRI_LOW, 416*5113495bSYour Name .d_CE_DDR_ADDRESS_FOR_RRI_HIGH = CE_DDR_ADDRESS_FOR_RRI_HIGH, 417*5113495bSYour Name .d_HOST_IE_ADDRESS = HOST_IE_ADDRESS, 418*5113495bSYour Name .d_HOST_IE_REG1_CE_LSB = HOST_IE_REG1_CE_LSB, 419*5113495bSYour Name .d_HOST_IE_ADDRESS_2 = HOST_IE_ADDRESS_2, 420*5113495bSYour Name .d_HOST_IE_REG2_CE_LSB = HOST_IE_REG2_CE_LSB, 421*5113495bSYour Name .d_HOST_IE_ADDRESS_3 = HOST_IE_ADDRESS_3, 422*5113495bSYour Name .d_HOST_IE_REG3_CE_LSB = HOST_IE_REG3_CE_LSB, 423*5113495bSYour Name .d_HOST_IE_COPY_COMPLETE_MASK = HOST_IE_COPY_COMPLETE_MASK, 424*5113495bSYour Name .d_SR_BA_ADDRESS = SR_BA_ADDRESS, 425*5113495bSYour Name .d_SR_BA_ADDRESS_HIGH = SR_BA_ADDRESS_HIGH, 426*5113495bSYour Name .d_SR_SIZE_ADDRESS = SR_SIZE_ADDRESS, 427*5113495bSYour Name .d_CE_CTRL1_ADDRESS = CE_CTRL1_ADDRESS, 428*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_MASK = CE_CTRL1_DMAX_LENGTH_MASK, 429*5113495bSYour Name .d_DR_BA_ADDRESS = DR_BA_ADDRESS, 430*5113495bSYour Name .d_DR_BA_ADDRESS_HIGH = DR_BA_ADDRESS_HIGH, 431*5113495bSYour Name .d_DR_SIZE_ADDRESS = DR_SIZE_ADDRESS, 432*5113495bSYour Name .d_CE_CMD_REGISTER = CE_CMD_REGISTER, 433*5113495bSYour Name .d_CE_MSI_ADDRESS = CE_MSI_ADDRESS, 434*5113495bSYour Name .d_CE_MSI_ADDRESS_HIGH = CE_MSI_ADDRESS_HIGH, 435*5113495bSYour Name .d_CE_MSI_DATA = CE_MSI_DATA, 436*5113495bSYour Name .d_CE_MSI_ENABLE_BIT = CE_MSI_ENABLE_BIT, 437*5113495bSYour Name .d_MISC_IE_ADDRESS = MISC_IE_ADDRESS, 438*5113495bSYour Name .d_MISC_IS_AXI_ERR_MASK = MISC_IS_AXI_ERR_MASK, 439*5113495bSYour Name .d_MISC_IS_DST_ADDR_ERR_MASK = MISC_IS_DST_ADDR_ERR_MASK, 440*5113495bSYour Name .d_MISC_IS_SRC_LEN_ERR_MASK = MISC_IS_SRC_LEN_ERR_MASK, 441*5113495bSYour Name .d_MISC_IS_DST_MAX_LEN_VIO_MASK = MISC_IS_DST_MAX_LEN_VIO_MASK, 442*5113495bSYour Name .d_MISC_IS_DST_RING_OVERFLOW_MASK = MISC_IS_DST_RING_OVERFLOW_MASK, 443*5113495bSYour Name .d_MISC_IS_SRC_RING_OVERFLOW_MASK = MISC_IS_SRC_RING_OVERFLOW_MASK, 444*5113495bSYour Name .d_SRC_WATERMARK_LOW_LSB = SRC_WATERMARK_LOW_LSB, 445*5113495bSYour Name .d_SRC_WATERMARK_HIGH_LSB = SRC_WATERMARK_HIGH_LSB, 446*5113495bSYour Name .d_DST_WATERMARK_LOW_LSB = DST_WATERMARK_LOW_LSB, 447*5113495bSYour Name .d_DST_WATERMARK_HIGH_LSB = DST_WATERMARK_HIGH_LSB, 448*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 449*5113495bSYour Name = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 450*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 451*5113495bSYour Name = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 452*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_LSB = CE_CTRL1_DMAX_LENGTH_LSB, 453*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 454*5113495bSYour Name = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 455*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 456*5113495bSYour Name = CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 457*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 458*5113495bSYour Name = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 459*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 460*5113495bSYour Name = CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 461*5113495bSYour Name .d_CE_CTRL1_IDX_UPD_EN_MASK = CE_CTRL1_IDX_UPD_EN_MASK, 462*5113495bSYour Name .d_CE_WRAPPER_DEBUG_OFFSET = CE_WRAPPER_DEBUG_OFFSET, 463*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_MSB = CE_WRAPPER_DEBUG_SEL_MSB, 464*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_LSB = CE_WRAPPER_DEBUG_SEL_LSB, 465*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_MASK = CE_WRAPPER_DEBUG_SEL_MASK, 466*5113495bSYour Name .d_CE_DEBUG_OFFSET = CE_DEBUG_OFFSET, 467*5113495bSYour Name .d_CE_DEBUG_SEL_MSB = CE_DEBUG_SEL_MSB, 468*5113495bSYour Name .d_CE_DEBUG_SEL_LSB = CE_DEBUG_SEL_LSB, 469*5113495bSYour Name .d_CE_DEBUG_SEL_MASK = CE_DEBUG_SEL_MASK, 470*5113495bSYour Name .d_CE0_BASE_ADDRESS = CE0_BASE_ADDRESS, 471*5113495bSYour Name .d_CE1_BASE_ADDRESS = CE1_BASE_ADDRESS, 472*5113495bSYour Name .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES 473*5113495bSYour Name = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES, 474*5113495bSYour Name .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS 475*5113495bSYour Name = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS, 476*5113495bSYour Name .d_HOST_CE_ADDRESS = HOST_CE_ADDRESS, 477*5113495bSYour Name .d_HOST_CMEM_ADDRESS = HOST_CMEM_ADDRESS, 478*5113495bSYour Name .d_PMM_SCRATCH_BASE = PMM_SCRATCH_BASE 479*5113495bSYour Name }; 480*5113495bSYour Name 481*5113495bSYour Name struct ce_reg_def *MY_CEREG_DEF = &my_ce_reg_def; 482*5113495bSYour Name 483*5113495bSYour Name #else 484*5113495bSYour Name #endif 485*5113495bSYour Name #endif 486