1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _AR6320DEF_H_ 20*5113495bSYour Name #define _AR6320DEF_H_ 21*5113495bSYour Name 22*5113495bSYour Name /* Base Addresses */ 23*5113495bSYour Name #define AR6320_RTC_SOC_BASE_ADDRESS 0x00000000 24*5113495bSYour Name #define AR6320_RTC_WMAC_BASE_ADDRESS 0x00001000 25*5113495bSYour Name #define AR6320_MAC_COEX_BASE_ADDRESS 0x0000f000 26*5113495bSYour Name #define AR6320_BT_COEX_BASE_ADDRESS 0x00002000 27*5113495bSYour Name #define AR6320_SOC_CORE_BASE_ADDRESS 0x0003a000 28*5113495bSYour Name #define AR6320_WLAN_UART_BASE_ADDRESS 0x0000c000 29*5113495bSYour Name #define AR6320_WLAN_SI_BASE_ADDRESS 0x00010000 30*5113495bSYour Name #define AR6320_WLAN_GPIO_BASE_ADDRESS 0x00005000 31*5113495bSYour Name #define AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS 0x00006000 32*5113495bSYour Name #define AR6320_WLAN_MAC_BASE_ADDRESS 0x00010000 33*5113495bSYour Name #define AR6320_EFUSE_BASE_ADDRESS 0x00024000 34*5113495bSYour Name #define AR6320_FPGA_REG_BASE_ADDRESS 0x00039000 35*5113495bSYour Name #define AR6320_WLAN_UART2_BASE_ADDRESS 0x00054c00 36*5113495bSYour Name #define AR6320_DBI_BASE_ADDRESS 0x0003c000 37*5113495bSYour Name 38*5113495bSYour Name #define AR6320_SCRATCH_3_ADDRESS 0x0028 39*5113495bSYour Name #define AR6320_TARG_DRAM_START 0x00400000 40*5113495bSYour Name #define AR6320_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0 41*5113495bSYour Name #define AR6320_SOC_RESET_CONTROL_OFFSET 0x00000000 42*5113495bSYour Name #define AR6320_SOC_CLOCK_CONTROL_OFFSET 0x00000028 43*5113495bSYour Name #define AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 44*5113495bSYour Name #define AR6320_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000000 45*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN0_ADDRESS 0x00000068 46*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN1_ADDRESS 0x0000006c 47*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 48*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 49*5113495bSYour Name #define AR6320_SOC_CPU_CLOCK_OFFSET 0x00000020 50*5113495bSYour Name #define AR6320_SOC_LPO_CAL_OFFSET 0x000000e0 51*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN10_ADDRESS 0x00000090 52*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN11_ADDRESS 0x00000094 53*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN12_ADDRESS 0x00000098 54*5113495bSYour Name #define AR6320_WLAN_GPIO_PIN13_ADDRESS 0x0000009c 55*5113495bSYour Name #define AR6320_SOC_CPU_CLOCK_STANDARD_LSB 0 56*5113495bSYour Name #define AR6320_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 57*5113495bSYour Name #define AR6320_SOC_LPO_CAL_ENABLE_LSB 20 58*5113495bSYour Name #define AR6320_SOC_LPO_CAL_ENABLE_MASK 0x00100000 59*5113495bSYour Name 60*5113495bSYour Name #define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 61*5113495bSYour Name #define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 62*5113495bSYour Name #define AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 63*5113495bSYour Name #define AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 64*5113495bSYour Name #define AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB 18 65*5113495bSYour Name #define AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 66*5113495bSYour Name #define AR6320_SI_CONFIG_I2C_LSB 16 67*5113495bSYour Name #define AR6320_SI_CONFIG_I2C_MASK 0x00010000 68*5113495bSYour Name #define AR6320_SI_CONFIG_POS_SAMPLE_LSB 7 69*5113495bSYour Name #define AR6320_SI_CONFIG_POS_SAMPLE_MASK 0x00000080 70*5113495bSYour Name #define AR6320_SI_CONFIG_INACTIVE_CLK_LSB 4 71*5113495bSYour Name #define AR6320_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 72*5113495bSYour Name #define AR6320_SI_CONFIG_INACTIVE_DATA_LSB 5 73*5113495bSYour Name #define AR6320_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 74*5113495bSYour Name #define AR6320_SI_CONFIG_DIVIDER_LSB 0 75*5113495bSYour Name #define AR6320_SI_CONFIG_DIVIDER_MASK 0x0000000f 76*5113495bSYour Name #define AR6320_SI_CONFIG_OFFSET 0x00000000 77*5113495bSYour Name #define AR6320_SI_TX_DATA0_OFFSET 0x00000008 78*5113495bSYour Name #define AR6320_SI_TX_DATA1_OFFSET 0x0000000c 79*5113495bSYour Name #define AR6320_SI_RX_DATA0_OFFSET 0x00000010 80*5113495bSYour Name #define AR6320_SI_RX_DATA1_OFFSET 0x00000014 81*5113495bSYour Name #define AR6320_SI_CS_OFFSET 0x00000004 82*5113495bSYour Name #define AR6320_SI_CS_DONE_ERR_MASK 0x00000400 83*5113495bSYour Name #define AR6320_SI_CS_DONE_INT_MASK 0x00000200 84*5113495bSYour Name #define AR6320_SI_CS_START_LSB 8 85*5113495bSYour Name #define AR6320_SI_CS_START_MASK 0x00000100 86*5113495bSYour Name #define AR6320_SI_CS_RX_CNT_LSB 4 87*5113495bSYour Name #define AR6320_SI_CS_RX_CNT_MASK 0x000000f0 88*5113495bSYour Name #define AR6320_SI_CS_TX_CNT_LSB 0 89*5113495bSYour Name #define AR6320_SI_CS_TX_CNT_MASK 0x0000000f 90*5113495bSYour Name #define AR6320_SR_WR_INDEX_ADDRESS 0x003c 91*5113495bSYour Name #define AR6320_DST_WATERMARK_ADDRESS 0x0050 92*5113495bSYour Name #define AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB 14 93*5113495bSYour Name #define AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000 94*5113495bSYour Name #define AR6320_RX_MPDU_START_0_RETRY_LSB 14 95*5113495bSYour Name #define AR6320_RX_MPDU_START_0_RETRY_MASK 0x00004000 96*5113495bSYour Name #define AR6320_RX_MPDU_START_0_SEQ_NUM_LSB 16 97*5113495bSYour Name #define AR6320_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000 98*5113495bSYour Name #define AR6320_RX_MPDU_START_2_TID_LSB 28 99*5113495bSYour Name #define AR6320_RX_MPDU_START_2_TID_MASK 0xf0000000 100*5113495bSYour Name #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 101*5113495bSYour Name defined(HIF_IPCI)) 102*5113495bSYour Name #define AR6320_SOC_PCIE_BASE_ADDRESS 0x00038000 103*5113495bSYour Name #define AR6320_CE_WRAPPER_BASE_ADDRESS 0x00034000 104*5113495bSYour Name #define AR6320_CE0_BASE_ADDRESS 0x00034400 105*5113495bSYour Name #define AR6320_CE1_BASE_ADDRESS 0x00034800 106*5113495bSYour Name #define AR6320_CE2_BASE_ADDRESS 0x00034c00 107*5113495bSYour Name #define AR6320_CE3_BASE_ADDRESS 0x00035000 108*5113495bSYour Name #define AR6320_CE4_BASE_ADDRESS 0x00035400 109*5113495bSYour Name #define AR6320_CE5_BASE_ADDRESS 0x00035800 110*5113495bSYour Name #define AR6320_CE6_BASE_ADDRESS 0x00035c00 111*5113495bSYour Name #define AR6320_CE7_BASE_ADDRESS 0x00036000 112*5113495bSYour Name #define AR6320_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800 113*5113495bSYour Name #define AR6320_CE_COUNT 8 114*5113495bSYour Name #define AR6320_CE_CTRL1_ADDRESS 0x0010 115*5113495bSYour Name #define AR6320_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 116*5113495bSYour Name #define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 117*5113495bSYour Name #define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00 118*5113495bSYour Name #define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8 119*5113495bSYour Name #define AR6320_CE_CTRL1_DMAX_LENGTH_LSB 0 120*5113495bSYour Name #define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 121*5113495bSYour Name #define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 122*5113495bSYour Name #define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 123*5113495bSYour Name #define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 124*5113495bSYour Name #define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020 125*5113495bSYour Name #define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5 126*5113495bSYour Name #define AR6320_PCIE_SOC_WAKE_RESET 0x00000000 127*5113495bSYour Name #define AR6320_PCIE_SOC_WAKE_ADDRESS 0x0004 128*5113495bSYour Name #define AR6320_PCIE_SOC_WAKE_V_MASK 0x00000001 129*5113495bSYour Name #define AR6320_MUX_ID_MASK 0x0000 130*5113495bSYour Name #define AR6320_TRANSACTION_ID_MASK 0x3fff 131*5113495bSYour Name #define AR6320_PCIE_LOCAL_BASE_ADDRESS 0x80000 132*5113495bSYour Name #define AR6320_FW_IND_HELPER 4 133*5113495bSYour Name #define AR6320_PCIE_INTR_ENABLE_ADDRESS 0x0008 134*5113495bSYour Name #define AR6320_PCIE_INTR_CLR_ADDRESS 0x0014 135*5113495bSYour Name #define AR6320_PCIE_INTR_FIRMWARE_MASK 0x00000400 136*5113495bSYour Name #define AR6320_PCIE_INTR_CE0_MASK 0x00000800 137*5113495bSYour Name #define AR6320_PCIE_INTR_CE_MASK_ALL 0x0007f800 138*5113495bSYour Name #define AR6320_PCIE_INTR_CAUSE_ADDRESS 0x000c 139*5113495bSYour Name #define AR6320_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001 140*5113495bSYour Name #endif 141*5113495bSYour Name #define AR6320_RX_MPDU_START_2_PN_47_32_LSB 0 142*5113495bSYour Name #define AR6320_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff 143*5113495bSYour Name #define AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK 0x000000ff 144*5113495bSYour Name #define AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB 0 145*5113495bSYour Name #define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16 146*5113495bSYour Name #define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000 147*5113495bSYour Name #define AR6320_RX_MSDU_END_4_LAST_MSDU_LSB 15 148*5113495bSYour Name #define AR6320_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000 149*5113495bSYour Name #define AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB 2 150*5113495bSYour Name #define AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004 151*5113495bSYour Name #define AR6320_RX_ATTENTION_0_FRAGMENT_LSB 13 152*5113495bSYour Name #define AR6320_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000 153*5113495bSYour Name #define AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000 154*5113495bSYour Name #define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16 155*5113495bSYour Name #define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000 156*5113495bSYour Name #define AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB 0 157*5113495bSYour Name #define AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff 158*5113495bSYour Name #define AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 159*5113495bSYour Name #define AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB 8 160*5113495bSYour Name #define AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 161*5113495bSYour Name #define AR6320_RX_MPDU_START_0_ENCRYPTED_LSB 13 162*5113495bSYour Name #define AR6320_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000 163*5113495bSYour Name #define AR6320_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400 164*5113495bSYour Name #define AR6320_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000 165*5113495bSYour Name #define AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 166*5113495bSYour Name #define AR6320_DST_WR_INDEX_ADDRESS 0x0040 167*5113495bSYour Name #define AR6320_SRC_WATERMARK_ADDRESS 0x004c 168*5113495bSYour Name #define AR6320_SRC_WATERMARK_LOW_MASK 0xffff0000 169*5113495bSYour Name #define AR6320_SRC_WATERMARK_HIGH_MASK 0x0000ffff 170*5113495bSYour Name #define AR6320_DST_WATERMARK_LOW_MASK 0xffff0000 171*5113495bSYour Name #define AR6320_DST_WATERMARK_HIGH_MASK 0x0000ffff 172*5113495bSYour Name #define AR6320_CURRENT_SRRI_ADDRESS 0x0044 173*5113495bSYour Name #define AR6320_CURRENT_DRRI_ADDRESS 0x0048 174*5113495bSYour Name #define AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 175*5113495bSYour Name #define AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 176*5113495bSYour Name #define AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 177*5113495bSYour Name #define AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 178*5113495bSYour Name #define AR6320_HOST_IS_ADDRESS 0x0030 179*5113495bSYour Name #define AR6320_HOST_IS_COPY_COMPLETE_MASK 0x00000001 180*5113495bSYour Name #define AR6320_HOST_IE_ADDRESS 0x002c 181*5113495bSYour Name #define AR6320_HOST_IE_COPY_COMPLETE_MASK 0x00000001 182*5113495bSYour Name #define AR6320_SR_BA_ADDRESS 0x0000 183*5113495bSYour Name #define AR6320_SR_SIZE_ADDRESS 0x0004 184*5113495bSYour Name #define AR6320_DR_BA_ADDRESS 0x0008 185*5113495bSYour Name #define AR6320_DR_SIZE_ADDRESS 0x000c 186*5113495bSYour Name #define AR6320_MISC_IE_ADDRESS 0x0034 187*5113495bSYour Name #define AR6320_MISC_IS_AXI_ERR_MASK 0x00000400 188*5113495bSYour Name #define AR6320_MISC_IS_DST_ADDR_ERR_MASK 0x00000200 189*5113495bSYour Name #define AR6320_MISC_IS_SRC_LEN_ERR_MASK 0x00000100 190*5113495bSYour Name #define AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 191*5113495bSYour Name #define AR6320_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 192*5113495bSYour Name #define AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 193*5113495bSYour Name #define AR6320_SRC_WATERMARK_LOW_LSB 16 194*5113495bSYour Name #define AR6320_SRC_WATERMARK_HIGH_LSB 0 195*5113495bSYour Name #define AR6320_DST_WATERMARK_LOW_LSB 16 196*5113495bSYour Name #define AR6320_DST_WATERMARK_HIGH_LSB 0 197*5113495bSYour Name #define AR6320_SOC_GLOBAL_RESET_ADDRESS 0x0008 198*5113495bSYour Name #define AR6320_RTC_STATE_ADDRESS 0x0000 199*5113495bSYour Name #define AR6320_RTC_STATE_COLD_RESET_MASK 0x00002000 200*5113495bSYour Name #define AR6320_RTC_STATE_V_MASK 0x00000007 201*5113495bSYour Name #define AR6320_RTC_STATE_V_LSB 0 202*5113495bSYour Name #define AR6320_RTC_STATE_V_ON 3 203*5113495bSYour Name #define AR6320_FW_IND_EVENT_PENDING 1 204*5113495bSYour Name #define AR6320_FW_IND_INITIALIZED 2 205*5113495bSYour Name #define AR6320_CPU_INTR_ADDRESS 0x0010 206*5113495bSYour Name #define AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 207*5113495bSYour Name #define AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 208*5113495bSYour Name #define AR6320_SOC_LF_TIMER_STATUS0_ADDRESS 0x00000054 209*5113495bSYour Name #define AR6320_SOC_RESET_CONTROL_ADDRESS 0x00000000 210*5113495bSYour Name #define AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 211*5113495bSYour Name #define AR6320_CORE_CTRL_ADDRESS 0x0000 212*5113495bSYour Name #define AR6320_CORE_CTRL_CPU_INTR_MASK 0x00002000 213*5113495bSYour Name #define AR6320_LOCAL_SCRATCH_OFFSET 0x000000c0 214*5113495bSYour Name #define AR6320_CLOCK_GPIO_OFFSET 0xffffffff 215*5113495bSYour Name #define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 216*5113495bSYour Name #define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 217*5113495bSYour Name #define AR6320_SOC_CHIP_ID_ADDRESS 0x000000f0 218*5113495bSYour Name #define AR6320_SOC_CHIP_ID_VERSION_MASK 0xfffc0000 219*5113495bSYour Name #define AR6320_SOC_CHIP_ID_VERSION_LSB 18 220*5113495bSYour Name #define AR6320_SOC_CHIP_ID_REVISION_MASK 0x00000f00 221*5113495bSYour Name #define AR6320_SOC_CHIP_ID_REVISION_LSB 8 222*5113495bSYour Name #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 223*5113495bSYour Name defined(HIF_IPCI)) 224*5113495bSYour Name #define AR6320_SOC_POWER_REG_OFFSET 0x0000010c 225*5113495bSYour Name /* Copy Engine Debug */ 226*5113495bSYour Name #define AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c 227*5113495bSYour Name #define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 228*5113495bSYour Name #define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 229*5113495bSYour Name #define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f 230*5113495bSYour Name #define AR6320_WLAN_DEBUG_CONTROL_OFFSET 0x00000108 231*5113495bSYour Name #define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB 0 232*5113495bSYour Name #define AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB 0 233*5113495bSYour Name #define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 234*5113495bSYour Name #define AR6320_WLAN_DEBUG_OUT_OFFSET 0x00000110 235*5113495bSYour Name #define AR6320_WLAN_DEBUG_OUT_DATA_MSB 19 236*5113495bSYour Name #define AR6320_WLAN_DEBUG_OUT_DATA_LSB 0 237*5113495bSYour Name #define AR6320_WLAN_DEBUG_OUT_DATA_MASK 0x000fffff 238*5113495bSYour Name #define AR6320_AMBA_DEBUG_BUS_OFFSET 0x0000011c 239*5113495bSYour Name #define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB 13 240*5113495bSYour Name #define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB 8 241*5113495bSYour Name #define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK 0x00003f00 242*5113495bSYour Name #define AR6320_AMBA_DEBUG_BUS_SEL_MSB 4 243*5113495bSYour Name #define AR6320_AMBA_DEBUG_BUS_SEL_LSB 0 244*5113495bSYour Name #define AR6320_AMBA_DEBUG_BUS_SEL_MASK 0x0000001f 245*5113495bSYour Name #define AR6320_CE_WRAPPER_DEBUG_OFFSET 0x0008 246*5113495bSYour Name #define AR6320_CE_WRAPPER_DEBUG_SEL_MSB 5 247*5113495bSYour Name #define AR6320_CE_WRAPPER_DEBUG_SEL_LSB 0 248*5113495bSYour Name #define AR6320_CE_WRAPPER_DEBUG_SEL_MASK 0x0000003f 249*5113495bSYour Name #define AR6320_CE_DEBUG_OFFSET 0x0054 250*5113495bSYour Name #define AR6320_CE_DEBUG_SEL_MSB 5 251*5113495bSYour Name #define AR6320_CE_DEBUG_SEL_LSB 0 252*5113495bSYour Name #define AR6320_CE_DEBUG_SEL_MASK 0x0000003f 253*5113495bSYour Name /* End */ 254*5113495bSYour Name 255*5113495bSYour Name /* PLL start */ 256*5113495bSYour Name #define AR6320_EFUSE_OFFSET 0x0000032c 257*5113495bSYour Name #define AR6320_EFUSE_XTAL_SEL_MSB 10 258*5113495bSYour Name #define AR6320_EFUSE_XTAL_SEL_LSB 8 259*5113495bSYour Name #define AR6320_EFUSE_XTAL_SEL_MASK 0x00000700 260*5113495bSYour Name #define AR6320_BB_PLL_CONFIG_OFFSET 0x000002f4 261*5113495bSYour Name #define AR6320_BB_PLL_CONFIG_OUTDIV_MSB 20 262*5113495bSYour Name #define AR6320_BB_PLL_CONFIG_OUTDIV_LSB 18 263*5113495bSYour Name #define AR6320_BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 264*5113495bSYour Name #define AR6320_BB_PLL_CONFIG_FRAC_MSB 17 265*5113495bSYour Name #define AR6320_BB_PLL_CONFIG_FRAC_LSB 0 266*5113495bSYour Name #define AR6320_BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 267*5113495bSYour Name #define AR6320_WLAN_PLL_SETTLE_TIME_MSB 10 268*5113495bSYour Name #define AR6320_WLAN_PLL_SETTLE_TIME_LSB 0 269*5113495bSYour Name #define AR6320_WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 270*5113495bSYour Name #define AR6320_WLAN_PLL_SETTLE_OFFSET 0x0018 271*5113495bSYour Name #define AR6320_WLAN_PLL_SETTLE_SW_MASK 0x000007ff 272*5113495bSYour Name #define AR6320_WLAN_PLL_SETTLE_RSTMASK 0xffffffff 273*5113495bSYour Name #define AR6320_WLAN_PLL_SETTLE_RESET 0x00000400 274*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_NOPWD_MSB 18 275*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_NOPWD_LSB 18 276*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 277*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_BYPASS_MSB 16 278*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_BYPASS_LSB 16 279*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 280*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_BYPASS_RESET 0x1 281*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB 15 282*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB 14 283*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK 0x0000c000 284*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET 0x0 285*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_REFDIV_MSB 13 286*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_REFDIV_LSB 10 287*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 288*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_REFDIV_RESET 0x0 289*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_DIV_MSB 9 290*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_DIV_LSB 0 291*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 292*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_DIV_RESET 0x11 293*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_OFFSET 0x0014 294*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_SW_MASK 0x001fffff 295*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_RSTMASK 0xffffffff 296*5113495bSYour Name #define AR6320_WLAN_PLL_CONTROL_RESET 0x00010011 297*5113495bSYour Name #define AR6320_SOC_CORE_CLK_CTRL_OFFSET 0x00000114 298*5113495bSYour Name #define AR6320_SOC_CORE_CLK_CTRL_DIV_MSB 2 299*5113495bSYour Name #define AR6320_SOC_CORE_CLK_CTRL_DIV_LSB 0 300*5113495bSYour Name #define AR6320_SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 301*5113495bSYour Name #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB 5 302*5113495bSYour Name #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 303*5113495bSYour Name #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 304*5113495bSYour Name #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET 0x0 305*5113495bSYour Name #define AR6320_RTC_SYNC_STATUS_OFFSET 0x0244 306*5113495bSYour Name #define AR6320_SOC_CPU_CLOCK_OFFSET 0x00000020 307*5113495bSYour Name #define AR6320_SOC_CPU_CLOCK_STANDARD_MSB 1 308*5113495bSYour Name #define AR6320_SOC_CPU_CLOCK_STANDARD_LSB 0 309*5113495bSYour Name #define AR6320_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 310*5113495bSYour Name /* PLL end */ 311*5113495bSYour Name #define AR6320_PCIE_INTR_CE_MASK(n) \ 312*5113495bSYour Name (AR6320_PCIE_INTR_CE0_MASK << (n)) 313*5113495bSYour Name #endif 314*5113495bSYour Name #define AR6320_DRAM_BASE_ADDRESS AR6320_TARG_DRAM_START 315*5113495bSYour Name #define AR6320_FW_INDICATOR_ADDRESS \ 316*5113495bSYour Name (AR6320_SOC_CORE_BASE_ADDRESS + AR6320_SCRATCH_3_ADDRESS) 317*5113495bSYour Name #define AR6320_SYSTEM_SLEEP_OFFSET AR6320_SOC_SYSTEM_SLEEP_OFFSET 318*5113495bSYour Name #define AR6320_WLAN_SYSTEM_SLEEP_OFFSET 0x002c 319*5113495bSYour Name #define AR6320_WLAN_RESET_CONTROL_OFFSET AR6320_SOC_RESET_CONTROL_OFFSET 320*5113495bSYour Name #define AR6320_CLOCK_CONTROL_OFFSET AR6320_SOC_CLOCK_CONTROL_OFFSET 321*5113495bSYour Name #define AR6320_CLOCK_CONTROL_SI0_CLK_MASK AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK 322*5113495bSYour Name #define AR6320_RESET_CONTROL_MBOX_RST_MASK 0x00000004 323*5113495bSYour Name #define AR6320_RESET_CONTROL_SI0_RST_MASK AR6320_SOC_RESET_CONTROL_SI0_RST_MASK 324*5113495bSYour Name #define AR6320_GPIO_BASE_ADDRESS AR6320_WLAN_GPIO_BASE_ADDRESS 325*5113495bSYour Name #define AR6320_GPIO_PIN0_OFFSET AR6320_WLAN_GPIO_PIN0_ADDRESS 326*5113495bSYour Name #define AR6320_GPIO_PIN1_OFFSET AR6320_WLAN_GPIO_PIN1_ADDRESS 327*5113495bSYour Name #define AR6320_GPIO_PIN0_CONFIG_MASK AR6320_WLAN_GPIO_PIN0_CONFIG_MASK 328*5113495bSYour Name #define AR6320_GPIO_PIN1_CONFIG_MASK AR6320_WLAN_GPIO_PIN1_CONFIG_MASK 329*5113495bSYour Name #define AR6320_SI_BASE_ADDRESS 0x00050000 330*5113495bSYour Name #define AR6320_CPU_CLOCK_OFFSET AR6320_SOC_CPU_CLOCK_OFFSET 331*5113495bSYour Name #define AR6320_LPO_CAL_OFFSET AR6320_SOC_LPO_CAL_OFFSET 332*5113495bSYour Name #define AR6320_GPIO_PIN10_OFFSET AR6320_WLAN_GPIO_PIN10_ADDRESS 333*5113495bSYour Name #define AR6320_GPIO_PIN11_OFFSET AR6320_WLAN_GPIO_PIN11_ADDRESS 334*5113495bSYour Name #define AR6320_GPIO_PIN12_OFFSET AR6320_WLAN_GPIO_PIN12_ADDRESS 335*5113495bSYour Name #define AR6320_GPIO_PIN13_OFFSET AR6320_WLAN_GPIO_PIN13_ADDRESS 336*5113495bSYour Name #define AR6320_CPU_CLOCK_STANDARD_LSB AR6320_SOC_CPU_CLOCK_STANDARD_LSB 337*5113495bSYour Name #define AR6320_CPU_CLOCK_STANDARD_MASK AR6320_SOC_CPU_CLOCK_STANDARD_MASK 338*5113495bSYour Name #define AR6320_LPO_CAL_ENABLE_LSB AR6320_SOC_LPO_CAL_ENABLE_LSB 339*5113495bSYour Name #define AR6320_LPO_CAL_ENABLE_MASK AR6320_SOC_LPO_CAL_ENABLE_MASK 340*5113495bSYour Name #define AR6320_ANALOG_INTF_BASE_ADDRESS AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS 341*5113495bSYour Name #define AR6320_MBOX_BASE_ADDRESS 0x00008000 342*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_ERROR_LSB 7 343*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 344*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_CPU_LSB 6 345*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_CPU_MASK 0x00000040 346*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_COUNTER_LSB 4 347*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 348*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 349*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 350*5113495bSYour Name #define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 17 351*5113495bSYour Name #define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00020000 352*5113495bSYour Name #define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 16 353*5113495bSYour Name #define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00010000 354*5113495bSYour Name #define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB 24 355*5113495bSYour Name #define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0xff000000 356*5113495bSYour Name #define AR6320_INT_STATUS_ENABLE_ADDRESS 0x0828 357*5113495bSYour Name #define AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB 8 358*5113495bSYour Name #define AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK 0x0000ff00 359*5113495bSYour Name #define AR6320_HOST_INT_STATUS_ADDRESS 0x0800 360*5113495bSYour Name #define AR6320_CPU_INT_STATUS_ADDRESS 0x0801 361*5113495bSYour Name #define AR6320_ERROR_INT_STATUS_ADDRESS 0x0802 362*5113495bSYour Name #define AR6320_ERROR_INT_STATUS_WAKEUP_MASK 0x00040000 363*5113495bSYour Name #define AR6320_ERROR_INT_STATUS_WAKEUP_LSB 18 364*5113495bSYour Name #define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00020000 365*5113495bSYour Name #define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 17 366*5113495bSYour Name #define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00010000 367*5113495bSYour Name #define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB 16 368*5113495bSYour Name #define AR6320_COUNT_DEC_ADDRESS 0x0840 369*5113495bSYour Name #define AR6320_HOST_INT_STATUS_CPU_MASK 0x00000040 370*5113495bSYour Name #define AR6320_HOST_INT_STATUS_CPU_LSB 6 371*5113495bSYour Name #define AR6320_HOST_INT_STATUS_ERROR_MASK 0x00000080 372*5113495bSYour Name #define AR6320_HOST_INT_STATUS_ERROR_LSB 7 373*5113495bSYour Name #define AR6320_HOST_INT_STATUS_COUNTER_MASK 0x00000010 374*5113495bSYour Name #define AR6320_HOST_INT_STATUS_COUNTER_LSB 4 375*5113495bSYour Name #define AR6320_RX_LOOKAHEAD_VALID_ADDRESS 0x0805 376*5113495bSYour Name #define AR6320_WINDOW_DATA_ADDRESS 0x0874 377*5113495bSYour Name #define AR6320_WINDOW_READ_ADDR_ADDRESS 0x087c 378*5113495bSYour Name #define AR6320_WINDOW_WRITE_ADDR_ADDRESS 0x0878 379*5113495bSYour Name #define AR6320_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f 380*5113495bSYour Name #define AR6320_HOST_INT_STATUS_MBOX_DATA_LSB 0 381*5113495bSYour Name 382*5113495bSYour Name struct targetdef_s ar6320_targetdef = { 383*5113495bSYour Name .d_RTC_SOC_BASE_ADDRESS = AR6320_RTC_SOC_BASE_ADDRESS, 384*5113495bSYour Name .d_RTC_WMAC_BASE_ADDRESS = AR6320_RTC_WMAC_BASE_ADDRESS, 385*5113495bSYour Name .d_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET, 386*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET, 387*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = 388*5113495bSYour Name AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB, 389*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = 390*5113495bSYour Name AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK, 391*5113495bSYour Name .d_CLOCK_CONTROL_OFFSET = AR6320_CLOCK_CONTROL_OFFSET, 392*5113495bSYour Name .d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320_CLOCK_CONTROL_SI0_CLK_MASK, 393*5113495bSYour Name .d_RESET_CONTROL_OFFSET = AR6320_SOC_RESET_CONTROL_OFFSET, 394*5113495bSYour Name .d_RESET_CONTROL_MBOX_RST_MASK = AR6320_RESET_CONTROL_MBOX_RST_MASK, 395*5113495bSYour Name .d_RESET_CONTROL_SI0_RST_MASK = AR6320_RESET_CONTROL_SI0_RST_MASK, 396*5113495bSYour Name .d_WLAN_RESET_CONTROL_OFFSET = AR6320_WLAN_RESET_CONTROL_OFFSET, 397*5113495bSYour Name .d_WLAN_RESET_CONTROL_COLD_RST_MASK = 398*5113495bSYour Name AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK, 399*5113495bSYour Name .d_WLAN_RESET_CONTROL_WARM_RST_MASK = 400*5113495bSYour Name AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK, 401*5113495bSYour Name .d_GPIO_BASE_ADDRESS = AR6320_GPIO_BASE_ADDRESS, 402*5113495bSYour Name .d_GPIO_PIN0_OFFSET = AR6320_GPIO_PIN0_OFFSET, 403*5113495bSYour Name .d_GPIO_PIN1_OFFSET = AR6320_GPIO_PIN1_OFFSET, 404*5113495bSYour Name .d_GPIO_PIN0_CONFIG_MASK = AR6320_GPIO_PIN0_CONFIG_MASK, 405*5113495bSYour Name .d_GPIO_PIN1_CONFIG_MASK = AR6320_GPIO_PIN1_CONFIG_MASK, 406*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB, 407*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK, 408*5113495bSYour Name .d_SI_CONFIG_I2C_LSB = AR6320_SI_CONFIG_I2C_LSB, 409*5113495bSYour Name .d_SI_CONFIG_I2C_MASK = AR6320_SI_CONFIG_I2C_MASK, 410*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_LSB = AR6320_SI_CONFIG_POS_SAMPLE_LSB, 411*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_MASK = AR6320_SI_CONFIG_POS_SAMPLE_MASK, 412*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320_SI_CONFIG_INACTIVE_CLK_LSB, 413*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320_SI_CONFIG_INACTIVE_CLK_MASK, 414*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320_SI_CONFIG_INACTIVE_DATA_LSB, 415*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_MASK = AR6320_SI_CONFIG_INACTIVE_DATA_MASK, 416*5113495bSYour Name .d_SI_CONFIG_DIVIDER_LSB = AR6320_SI_CONFIG_DIVIDER_LSB, 417*5113495bSYour Name .d_SI_CONFIG_DIVIDER_MASK = AR6320_SI_CONFIG_DIVIDER_MASK, 418*5113495bSYour Name .d_SI_BASE_ADDRESS = AR6320_SI_BASE_ADDRESS, 419*5113495bSYour Name .d_SI_CONFIG_OFFSET = AR6320_SI_CONFIG_OFFSET, 420*5113495bSYour Name .d_SI_TX_DATA0_OFFSET = AR6320_SI_TX_DATA0_OFFSET, 421*5113495bSYour Name .d_SI_TX_DATA1_OFFSET = AR6320_SI_TX_DATA1_OFFSET, 422*5113495bSYour Name .d_SI_RX_DATA0_OFFSET = AR6320_SI_RX_DATA0_OFFSET, 423*5113495bSYour Name .d_SI_RX_DATA1_OFFSET = AR6320_SI_RX_DATA1_OFFSET, 424*5113495bSYour Name .d_SI_CS_OFFSET = AR6320_SI_CS_OFFSET, 425*5113495bSYour Name .d_SI_CS_DONE_ERR_MASK = AR6320_SI_CS_DONE_ERR_MASK, 426*5113495bSYour Name .d_SI_CS_DONE_INT_MASK = AR6320_SI_CS_DONE_INT_MASK, 427*5113495bSYour Name .d_SI_CS_START_LSB = AR6320_SI_CS_START_LSB, 428*5113495bSYour Name .d_SI_CS_START_MASK = AR6320_SI_CS_START_MASK, 429*5113495bSYour Name .d_SI_CS_RX_CNT_LSB = AR6320_SI_CS_RX_CNT_LSB, 430*5113495bSYour Name .d_SI_CS_RX_CNT_MASK = AR6320_SI_CS_RX_CNT_MASK, 431*5113495bSYour Name .d_SI_CS_TX_CNT_LSB = AR6320_SI_CS_TX_CNT_LSB, 432*5113495bSYour Name .d_SI_CS_TX_CNT_MASK = AR6320_SI_CS_TX_CNT_MASK, 433*5113495bSYour Name .d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ, 434*5113495bSYour Name .d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ, 435*5113495bSYour Name .d_MBOX_BASE_ADDRESS = AR6320_MBOX_BASE_ADDRESS, 436*5113495bSYour Name .d_LOCAL_SCRATCH_OFFSET = AR6320_LOCAL_SCRATCH_OFFSET, 437*5113495bSYour Name .d_CPU_CLOCK_OFFSET = AR6320_CPU_CLOCK_OFFSET, 438*5113495bSYour Name .d_LPO_CAL_OFFSET = AR6320_LPO_CAL_OFFSET, 439*5113495bSYour Name .d_GPIO_PIN10_OFFSET = AR6320_GPIO_PIN10_OFFSET, 440*5113495bSYour Name .d_GPIO_PIN11_OFFSET = AR6320_GPIO_PIN11_OFFSET, 441*5113495bSYour Name .d_GPIO_PIN12_OFFSET = AR6320_GPIO_PIN12_OFFSET, 442*5113495bSYour Name .d_GPIO_PIN13_OFFSET = AR6320_GPIO_PIN13_OFFSET, 443*5113495bSYour Name .d_CLOCK_GPIO_OFFSET = AR6320_CLOCK_GPIO_OFFSET, 444*5113495bSYour Name .d_CPU_CLOCK_STANDARD_LSB = AR6320_CPU_CLOCK_STANDARD_LSB, 445*5113495bSYour Name .d_CPU_CLOCK_STANDARD_MASK = AR6320_CPU_CLOCK_STANDARD_MASK, 446*5113495bSYour Name .d_LPO_CAL_ENABLE_LSB = AR6320_LPO_CAL_ENABLE_LSB, 447*5113495bSYour Name .d_LPO_CAL_ENABLE_MASK = AR6320_LPO_CAL_ENABLE_MASK, 448*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB, 449*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = 450*5113495bSYour Name AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK, 451*5113495bSYour Name .d_ANALOG_INTF_BASE_ADDRESS = AR6320_ANALOG_INTF_BASE_ADDRESS, 452*5113495bSYour Name .d_WLAN_MAC_BASE_ADDRESS = AR6320_WLAN_MAC_BASE_ADDRESS, 453*5113495bSYour Name .d_FW_INDICATOR_ADDRESS = AR6320_FW_INDICATOR_ADDRESS, 454*5113495bSYour Name .d_DRAM_BASE_ADDRESS = AR6320_DRAM_BASE_ADDRESS, 455*5113495bSYour Name .d_SOC_CORE_BASE_ADDRESS = AR6320_SOC_CORE_BASE_ADDRESS, 456*5113495bSYour Name .d_CORE_CTRL_ADDRESS = AR6320_CORE_CTRL_ADDRESS, 457*5113495bSYour Name #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 458*5113495bSYour Name defined(HIF_IPCI)) 459*5113495bSYour Name .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, 460*5113495bSYour Name .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, 461*5113495bSYour Name #endif 462*5113495bSYour Name .d_CORE_CTRL_CPU_INTR_MASK = AR6320_CORE_CTRL_CPU_INTR_MASK, 463*5113495bSYour Name .d_SR_WR_INDEX_ADDRESS = AR6320_SR_WR_INDEX_ADDRESS, 464*5113495bSYour Name .d_DST_WATERMARK_ADDRESS = AR6320_DST_WATERMARK_ADDRESS, 465*5113495bSYour Name /* htt_rx.c */ 466*5113495bSYour Name .d_RX_MSDU_END_4_FIRST_MSDU_MASK = 467*5113495bSYour Name AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK, 468*5113495bSYour Name .d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB, 469*5113495bSYour Name .d_RX_MPDU_START_0_RETRY_LSB = AR6320_RX_MPDU_START_0_RETRY_LSB, 470*5113495bSYour Name .d_RX_MPDU_START_0_RETRY_MASK = AR6320_RX_MPDU_START_0_RETRY_MASK, 471*5113495bSYour Name .d_RX_MPDU_START_0_SEQ_NUM_MASK = AR6320_RX_MPDU_START_0_SEQ_NUM_MASK, 472*5113495bSYour Name .d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320_RX_MPDU_START_0_SEQ_NUM_LSB, 473*5113495bSYour Name .d_RX_MPDU_START_2_PN_47_32_LSB = AR6320_RX_MPDU_START_2_PN_47_32_LSB, 474*5113495bSYour Name .d_RX_MPDU_START_2_PN_47_32_MASK = 475*5113495bSYour Name AR6320_RX_MPDU_START_2_PN_47_32_MASK, 476*5113495bSYour Name .d_RX_MPDU_START_2_TID_LSB = AR6320_RX_MPDU_START_2_TID_LSB, 477*5113495bSYour Name .d_RX_MPDU_START_2_TID_MASK = AR6320_RX_MPDU_START_2_TID_MASK, 478*5113495bSYour Name .d_RX_MSDU_END_1_KEY_ID_OCT_MASK = 479*5113495bSYour Name AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK, 480*5113495bSYour Name .d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB, 481*5113495bSYour Name .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK = 482*5113495bSYour Name AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK, 483*5113495bSYour Name .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB = 484*5113495bSYour Name AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB, 485*5113495bSYour Name .d_RX_MSDU_END_4_LAST_MSDU_MASK = AR6320_RX_MSDU_END_4_LAST_MSDU_MASK, 486*5113495bSYour Name .d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320_RX_MSDU_END_4_LAST_MSDU_LSB, 487*5113495bSYour Name .d_RX_ATTENTION_0_MCAST_BCAST_MASK = 488*5113495bSYour Name AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK, 489*5113495bSYour Name .d_RX_ATTENTION_0_MCAST_BCAST_LSB = 490*5113495bSYour Name AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB, 491*5113495bSYour Name .d_RX_ATTENTION_0_FRAGMENT_MASK = AR6320_RX_ATTENTION_0_FRAGMENT_MASK, 492*5113495bSYour Name .d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320_RX_ATTENTION_0_FRAGMENT_LSB, 493*5113495bSYour Name .d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK = 494*5113495bSYour Name AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK, 495*5113495bSYour Name .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK = 496*5113495bSYour Name AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK, 497*5113495bSYour Name .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB = 498*5113495bSYour Name AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB, 499*5113495bSYour Name .d_RX_MSDU_START_0_MSDU_LENGTH_MASK = 500*5113495bSYour Name AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK, 501*5113495bSYour Name .d_RX_MSDU_START_0_MSDU_LENGTH_LSB = 502*5113495bSYour Name AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB, 503*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET = 504*5113495bSYour Name AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET, 505*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_MASK = 506*5113495bSYour Name AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK, 507*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_LSB = 508*5113495bSYour Name AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB, 509*5113495bSYour Name .d_RX_MPDU_START_0_ENCRYPTED_MASK = 510*5113495bSYour Name AR6320_RX_MPDU_START_0_ENCRYPTED_MASK, 511*5113495bSYour Name .d_RX_MPDU_START_0_ENCRYPTED_LSB = 512*5113495bSYour Name AR6320_RX_MPDU_START_0_ENCRYPTED_LSB, 513*5113495bSYour Name .d_RX_ATTENTION_0_MORE_DATA_MASK = 514*5113495bSYour Name AR6320_RX_ATTENTION_0_MORE_DATA_MASK, 515*5113495bSYour Name .d_RX_ATTENTION_0_MSDU_DONE_MASK = 516*5113495bSYour Name AR6320_RX_ATTENTION_0_MSDU_DONE_MASK, 517*5113495bSYour Name .d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK = 518*5113495bSYour Name AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK, 519*5113495bSYour Name #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 520*5113495bSYour Name defined(HIF_IPCI)) 521*5113495bSYour Name .d_CE_COUNT = AR6320_CE_COUNT, 522*5113495bSYour Name .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, 523*5113495bSYour Name .d_PCIE_INTR_ENABLE_ADDRESS = AR6320_PCIE_INTR_ENABLE_ADDRESS, 524*5113495bSYour Name .d_PCIE_INTR_CLR_ADDRESS = AR6320_PCIE_INTR_CLR_ADDRESS, 525*5113495bSYour Name .d_PCIE_INTR_FIRMWARE_MASK = AR6320_PCIE_INTR_FIRMWARE_MASK, 526*5113495bSYour Name .d_PCIE_INTR_CE_MASK_ALL = AR6320_PCIE_INTR_CE_MASK_ALL, 527*5113495bSYour Name /* PLL start */ 528*5113495bSYour Name .d_EFUSE_OFFSET = AR6320_EFUSE_OFFSET, 529*5113495bSYour Name .d_EFUSE_XTAL_SEL_MSB = AR6320_EFUSE_XTAL_SEL_MSB, 530*5113495bSYour Name .d_EFUSE_XTAL_SEL_LSB = AR6320_EFUSE_XTAL_SEL_LSB, 531*5113495bSYour Name .d_EFUSE_XTAL_SEL_MASK = AR6320_EFUSE_XTAL_SEL_MASK, 532*5113495bSYour Name .d_BB_PLL_CONFIG_OFFSET = AR6320_BB_PLL_CONFIG_OFFSET, 533*5113495bSYour Name .d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320_BB_PLL_CONFIG_OUTDIV_MSB, 534*5113495bSYour Name .d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320_BB_PLL_CONFIG_OUTDIV_LSB, 535*5113495bSYour Name .d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320_BB_PLL_CONFIG_OUTDIV_MASK, 536*5113495bSYour Name .d_BB_PLL_CONFIG_FRAC_MSB = AR6320_BB_PLL_CONFIG_FRAC_MSB, 537*5113495bSYour Name .d_BB_PLL_CONFIG_FRAC_LSB = AR6320_BB_PLL_CONFIG_FRAC_LSB, 538*5113495bSYour Name .d_BB_PLL_CONFIG_FRAC_MASK = AR6320_BB_PLL_CONFIG_FRAC_MASK, 539*5113495bSYour Name .d_WLAN_PLL_SETTLE_TIME_MSB = AR6320_WLAN_PLL_SETTLE_TIME_MSB, 540*5113495bSYour Name .d_WLAN_PLL_SETTLE_TIME_LSB = AR6320_WLAN_PLL_SETTLE_TIME_LSB, 541*5113495bSYour Name .d_WLAN_PLL_SETTLE_TIME_MASK = AR6320_WLAN_PLL_SETTLE_TIME_MASK, 542*5113495bSYour Name .d_WLAN_PLL_SETTLE_OFFSET = AR6320_WLAN_PLL_SETTLE_OFFSET, 543*5113495bSYour Name .d_WLAN_PLL_SETTLE_SW_MASK = AR6320_WLAN_PLL_SETTLE_SW_MASK, 544*5113495bSYour Name .d_WLAN_PLL_SETTLE_RSTMASK = AR6320_WLAN_PLL_SETTLE_RSTMASK, 545*5113495bSYour Name .d_WLAN_PLL_SETTLE_RESET = AR6320_WLAN_PLL_SETTLE_RESET, 546*5113495bSYour Name .d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320_WLAN_PLL_CONTROL_NOPWD_MSB, 547*5113495bSYour Name .d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320_WLAN_PLL_CONTROL_NOPWD_LSB, 548*5113495bSYour Name .d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320_WLAN_PLL_CONTROL_NOPWD_MASK, 549*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320_WLAN_PLL_CONTROL_BYPASS_MSB, 550*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320_WLAN_PLL_CONTROL_BYPASS_LSB, 551*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_MASK = AR6320_WLAN_PLL_CONTROL_BYPASS_MASK, 552*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_RESET = 553*5113495bSYour Name AR6320_WLAN_PLL_CONTROL_BYPASS_RESET, 554*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_MSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB, 555*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_LSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB, 556*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_MASK = 557*5113495bSYour Name AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK, 558*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_RESET = 559*5113495bSYour Name AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET, 560*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320_WLAN_PLL_CONTROL_REFDIV_MSB, 561*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320_WLAN_PLL_CONTROL_REFDIV_LSB, 562*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_MASK = AR6320_WLAN_PLL_CONTROL_REFDIV_MASK, 563*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_RESET = 564*5113495bSYour Name AR6320_WLAN_PLL_CONTROL_REFDIV_RESET, 565*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_MSB = AR6320_WLAN_PLL_CONTROL_DIV_MSB, 566*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_LSB = AR6320_WLAN_PLL_CONTROL_DIV_LSB, 567*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_MASK = AR6320_WLAN_PLL_CONTROL_DIV_MASK, 568*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_RESET = AR6320_WLAN_PLL_CONTROL_DIV_RESET, 569*5113495bSYour Name .d_WLAN_PLL_CONTROL_OFFSET = AR6320_WLAN_PLL_CONTROL_OFFSET, 570*5113495bSYour Name .d_WLAN_PLL_CONTROL_SW_MASK = AR6320_WLAN_PLL_CONTROL_SW_MASK, 571*5113495bSYour Name .d_WLAN_PLL_CONTROL_RSTMASK = AR6320_WLAN_PLL_CONTROL_RSTMASK, 572*5113495bSYour Name .d_WLAN_PLL_CONTROL_RESET = AR6320_WLAN_PLL_CONTROL_RESET, 573*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_OFFSET = AR6320_SOC_CORE_CLK_CTRL_OFFSET, 574*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320_SOC_CORE_CLK_CTRL_DIV_MSB, 575*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320_SOC_CORE_CLK_CTRL_DIV_LSB, 576*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320_SOC_CORE_CLK_CTRL_DIV_MASK, 577*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_MSB = 578*5113495bSYour Name AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB, 579*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_LSB = 580*5113495bSYour Name AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB, 581*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_MASK = 582*5113495bSYour Name AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK, 583*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_RESET = 584*5113495bSYour Name AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET, 585*5113495bSYour Name .d_RTC_SYNC_STATUS_OFFSET = AR6320_RTC_SYNC_STATUS_OFFSET, 586*5113495bSYour Name .d_SOC_CPU_CLOCK_OFFSET = AR6320_SOC_CPU_CLOCK_OFFSET, 587*5113495bSYour Name .d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320_SOC_CPU_CLOCK_STANDARD_MSB, 588*5113495bSYour Name .d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320_SOC_CPU_CLOCK_STANDARD_LSB, 589*5113495bSYour Name .d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320_SOC_CPU_CLOCK_STANDARD_MASK, 590*5113495bSYour Name /* PLL end */ 591*5113495bSYour Name .d_SOC_POWER_REG_OFFSET = AR6320_SOC_POWER_REG_OFFSET, 592*5113495bSYour Name .d_PCIE_INTR_CAUSE_ADDRESS = AR6320_PCIE_INTR_CAUSE_ADDRESS, 593*5113495bSYour Name .d_SOC_RESET_CONTROL_ADDRESS = AR6320_SOC_RESET_CONTROL_ADDRESS, 594*5113495bSYour Name .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = 595*5113495bSYour Name AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK, 596*5113495bSYour Name .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB = 597*5113495bSYour Name AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB, 598*5113495bSYour Name .d_SOC_RESET_CONTROL_CE_RST_MASK = 599*5113495bSYour Name AR6320_SOC_RESET_CONTROL_CE_RST_MASK, 600*5113495bSYour Name .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK = 601*5113495bSYour Name AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK, 602*5113495bSYour Name .d_CPU_INTR_ADDRESS = AR6320_CPU_INTR_ADDRESS, 603*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ADDRESS = 604*5113495bSYour Name AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS, 605*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK = 606*5113495bSYour Name AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK, 607*5113495bSYour Name .d_SOC_LF_TIMER_STATUS0_ADDRESS = 608*5113495bSYour Name AR6320_SOC_LF_TIMER_STATUS0_ADDRESS, 609*5113495bSYour Name 610*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET, 611*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB, 612*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB, 613*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_SRC_MASK = 614*5113495bSYour Name AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK, 615*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_OFFSET = AR6320_WLAN_DEBUG_CONTROL_OFFSET, 616*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_ENABLE_MSB = 617*5113495bSYour Name AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB, 618*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_ENABLE_LSB = 619*5113495bSYour Name AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB, 620*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_ENABLE_MASK = 621*5113495bSYour Name AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK, 622*5113495bSYour Name .d_WLAN_DEBUG_OUT_OFFSET = AR6320_WLAN_DEBUG_OUT_OFFSET, 623*5113495bSYour Name .d_WLAN_DEBUG_OUT_DATA_MSB = AR6320_WLAN_DEBUG_OUT_DATA_MSB, 624*5113495bSYour Name .d_WLAN_DEBUG_OUT_DATA_LSB = AR6320_WLAN_DEBUG_OUT_DATA_LSB, 625*5113495bSYour Name .d_WLAN_DEBUG_OUT_DATA_MASK = AR6320_WLAN_DEBUG_OUT_DATA_MASK, 626*5113495bSYour Name .d_AMBA_DEBUG_BUS_OFFSET = AR6320_AMBA_DEBUG_BUS_OFFSET, 627*5113495bSYour Name .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB = 628*5113495bSYour Name AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB, 629*5113495bSYour Name .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB = 630*5113495bSYour Name AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB, 631*5113495bSYour Name .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK = 632*5113495bSYour Name AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK, 633*5113495bSYour Name .d_AMBA_DEBUG_BUS_SEL_MSB = AR6320_AMBA_DEBUG_BUS_SEL_MSB, 634*5113495bSYour Name .d_AMBA_DEBUG_BUS_SEL_LSB = AR6320_AMBA_DEBUG_BUS_SEL_LSB, 635*5113495bSYour Name .d_AMBA_DEBUG_BUS_SEL_MASK = AR6320_AMBA_DEBUG_BUS_SEL_MASK, 636*5113495bSYour Name #endif 637*5113495bSYour Name /* chip id start */ 638*5113495bSYour Name .d_SOC_CHIP_ID_ADDRESS = AR6320_SOC_CHIP_ID_ADDRESS, 639*5113495bSYour Name .d_SOC_CHIP_ID_VERSION_MASK = AR6320_SOC_CHIP_ID_VERSION_MASK, 640*5113495bSYour Name .d_SOC_CHIP_ID_VERSION_LSB = AR6320_SOC_CHIP_ID_VERSION_LSB, 641*5113495bSYour Name .d_SOC_CHIP_ID_REVISION_MASK = AR6320_SOC_CHIP_ID_REVISION_MASK, 642*5113495bSYour Name .d_SOC_CHIP_ID_REVISION_LSB = AR6320_SOC_CHIP_ID_REVISION_LSB, 643*5113495bSYour Name /* chip id end */ 644*5113495bSYour Name }; 645*5113495bSYour Name 646*5113495bSYour Name struct hostdef_s ar6320_hostdef = { 647*5113495bSYour Name .d_INT_STATUS_ENABLE_ERROR_LSB = AR6320_INT_STATUS_ENABLE_ERROR_LSB, 648*5113495bSYour Name .d_INT_STATUS_ENABLE_ERROR_MASK = AR6320_INT_STATUS_ENABLE_ERROR_MASK, 649*5113495bSYour Name .d_INT_STATUS_ENABLE_CPU_LSB = AR6320_INT_STATUS_ENABLE_CPU_LSB, 650*5113495bSYour Name .d_INT_STATUS_ENABLE_CPU_MASK = AR6320_INT_STATUS_ENABLE_CPU_MASK, 651*5113495bSYour Name .d_INT_STATUS_ENABLE_COUNTER_LSB = 652*5113495bSYour Name AR6320_INT_STATUS_ENABLE_COUNTER_LSB, 653*5113495bSYour Name .d_INT_STATUS_ENABLE_COUNTER_MASK = 654*5113495bSYour Name AR6320_INT_STATUS_ENABLE_COUNTER_MASK, 655*5113495bSYour Name .d_INT_STATUS_ENABLE_MBOX_DATA_LSB = 656*5113495bSYour Name AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB, 657*5113495bSYour Name .d_INT_STATUS_ENABLE_MBOX_DATA_MASK = 658*5113495bSYour Name AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK, 659*5113495bSYour Name .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB = 660*5113495bSYour Name AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB, 661*5113495bSYour Name .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK = 662*5113495bSYour Name AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 663*5113495bSYour Name .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB = 664*5113495bSYour Name AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB, 665*5113495bSYour Name .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK = 666*5113495bSYour Name AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 667*5113495bSYour Name .d_COUNTER_INT_STATUS_ENABLE_BIT_LSB = 668*5113495bSYour Name AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB, 669*5113495bSYour Name .d_COUNTER_INT_STATUS_ENABLE_BIT_MASK = 670*5113495bSYour Name AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK, 671*5113495bSYour Name .d_INT_STATUS_ENABLE_ADDRESS = AR6320_INT_STATUS_ENABLE_ADDRESS, 672*5113495bSYour Name .d_CPU_INT_STATUS_ENABLE_BIT_LSB = 673*5113495bSYour Name AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB, 674*5113495bSYour Name .d_CPU_INT_STATUS_ENABLE_BIT_MASK = 675*5113495bSYour Name AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK, 676*5113495bSYour Name .d_HOST_INT_STATUS_ADDRESS = AR6320_HOST_INT_STATUS_ADDRESS, 677*5113495bSYour Name .d_CPU_INT_STATUS_ADDRESS = AR6320_CPU_INT_STATUS_ADDRESS, 678*5113495bSYour Name .d_ERROR_INT_STATUS_ADDRESS = AR6320_ERROR_INT_STATUS_ADDRESS, 679*5113495bSYour Name .d_ERROR_INT_STATUS_WAKEUP_MASK = AR6320_ERROR_INT_STATUS_WAKEUP_MASK, 680*5113495bSYour Name .d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320_ERROR_INT_STATUS_WAKEUP_LSB, 681*5113495bSYour Name .d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK = 682*5113495bSYour Name AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK, 683*5113495bSYour Name .d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB = 684*5113495bSYour Name AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB, 685*5113495bSYour Name .d_ERROR_INT_STATUS_TX_OVERFLOW_MASK = 686*5113495bSYour Name AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK, 687*5113495bSYour Name .d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = 688*5113495bSYour Name AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB, 689*5113495bSYour Name .d_COUNT_DEC_ADDRESS = AR6320_COUNT_DEC_ADDRESS, 690*5113495bSYour Name .d_HOST_INT_STATUS_CPU_MASK = AR6320_HOST_INT_STATUS_CPU_MASK, 691*5113495bSYour Name .d_HOST_INT_STATUS_CPU_LSB = AR6320_HOST_INT_STATUS_CPU_LSB, 692*5113495bSYour Name .d_HOST_INT_STATUS_ERROR_MASK = AR6320_HOST_INT_STATUS_ERROR_MASK, 693*5113495bSYour Name .d_HOST_INT_STATUS_ERROR_LSB = AR6320_HOST_INT_STATUS_ERROR_LSB, 694*5113495bSYour Name .d_HOST_INT_STATUS_COUNTER_MASK = AR6320_HOST_INT_STATUS_COUNTER_MASK, 695*5113495bSYour Name .d_HOST_INT_STATUS_COUNTER_LSB = AR6320_HOST_INT_STATUS_COUNTER_LSB, 696*5113495bSYour Name .d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320_RX_LOOKAHEAD_VALID_ADDRESS, 697*5113495bSYour Name .d_WINDOW_DATA_ADDRESS = AR6320_WINDOW_DATA_ADDRESS, 698*5113495bSYour Name .d_WINDOW_READ_ADDR_ADDRESS = AR6320_WINDOW_READ_ADDR_ADDRESS, 699*5113495bSYour Name .d_WINDOW_WRITE_ADDR_ADDRESS = AR6320_WINDOW_WRITE_ADDR_ADDRESS, 700*5113495bSYour Name .d_SOC_GLOBAL_RESET_ADDRESS = AR6320_SOC_GLOBAL_RESET_ADDRESS, 701*5113495bSYour Name .d_RTC_STATE_ADDRESS = AR6320_RTC_STATE_ADDRESS, 702*5113495bSYour Name .d_RTC_STATE_COLD_RESET_MASK = AR6320_RTC_STATE_COLD_RESET_MASK, 703*5113495bSYour Name #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 704*5113495bSYour Name defined(HIF_IPCI)) 705*5113495bSYour Name .d_PCIE_LOCAL_BASE_ADDRESS = AR6320_PCIE_LOCAL_BASE_ADDRESS, 706*5113495bSYour Name .d_PCIE_SOC_WAKE_RESET = AR6320_PCIE_SOC_WAKE_RESET, 707*5113495bSYour Name .d_PCIE_SOC_WAKE_ADDRESS = AR6320_PCIE_SOC_WAKE_ADDRESS, 708*5113495bSYour Name .d_PCIE_SOC_WAKE_V_MASK = AR6320_PCIE_SOC_WAKE_V_MASK, 709*5113495bSYour Name .d_MUX_ID_MASK = AR6320_MUX_ID_MASK, 710*5113495bSYour Name .d_TRANSACTION_ID_MASK = AR6320_TRANSACTION_ID_MASK, 711*5113495bSYour Name .d_FW_IND_HELPER = AR6320_FW_IND_HELPER, 712*5113495bSYour Name .d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS, 713*5113495bSYour Name .d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK, 714*5113495bSYour Name .d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS, 715*5113495bSYour Name .d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS, 716*5113495bSYour Name .d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS, 717*5113495bSYour Name .d_HOST_CE_COUNT = 8, 718*5113495bSYour Name .d_ENABLE_MSI = 0, 719*5113495bSYour Name #endif 720*5113495bSYour Name .d_RTC_STATE_V_MASK = AR6320_RTC_STATE_V_MASK, 721*5113495bSYour Name .d_RTC_STATE_V_LSB = AR6320_RTC_STATE_V_LSB, 722*5113495bSYour Name .d_FW_IND_EVENT_PENDING = AR6320_FW_IND_EVENT_PENDING, 723*5113495bSYour Name .d_FW_IND_INITIALIZED = AR6320_FW_IND_INITIALIZED, 724*5113495bSYour Name .d_RTC_STATE_V_ON = AR6320_RTC_STATE_V_ON, 725*5113495bSYour Name #if defined(SDIO_3_0) 726*5113495bSYour Name .d_HOST_INT_STATUS_MBOX_DATA_MASK = 727*5113495bSYour Name AR6320_HOST_INT_STATUS_MBOX_DATA_MASK, 728*5113495bSYour Name .d_HOST_INT_STATUS_MBOX_DATA_LSB = 729*5113495bSYour Name AR6320_HOST_INT_STATUS_MBOX_DATA_LSB, 730*5113495bSYour Name #endif 731*5113495bSYour Name }; 732*5113495bSYour Name 733*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 734*5113495bSYour Name defined(HIF_IPCI) 735*5113495bSYour Name struct ce_reg_def ar6320_ce_targetdef = { 736*5113495bSYour Name /* copy_engine.c */ 737*5113495bSYour Name .d_DST_WR_INDEX_ADDRESS = AR6320_DST_WR_INDEX_ADDRESS, 738*5113495bSYour Name .d_SRC_WATERMARK_ADDRESS = AR6320_SRC_WATERMARK_ADDRESS, 739*5113495bSYour Name .d_SRC_WATERMARK_LOW_MASK = AR6320_SRC_WATERMARK_LOW_MASK, 740*5113495bSYour Name .d_SRC_WATERMARK_HIGH_MASK = AR6320_SRC_WATERMARK_HIGH_MASK, 741*5113495bSYour Name .d_DST_WATERMARK_LOW_MASK = AR6320_DST_WATERMARK_LOW_MASK, 742*5113495bSYour Name .d_DST_WATERMARK_HIGH_MASK = AR6320_DST_WATERMARK_HIGH_MASK, 743*5113495bSYour Name .d_CURRENT_SRRI_ADDRESS = AR6320_CURRENT_SRRI_ADDRESS, 744*5113495bSYour Name .d_CURRENT_DRRI_ADDRESS = AR6320_CURRENT_DRRI_ADDRESS, 745*5113495bSYour Name .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = 746*5113495bSYour Name AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 747*5113495bSYour Name .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = 748*5113495bSYour Name AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 749*5113495bSYour Name .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = 750*5113495bSYour Name AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 751*5113495bSYour Name .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = 752*5113495bSYour Name AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK, 753*5113495bSYour Name .d_HOST_IS_ADDRESS = AR6320_HOST_IS_ADDRESS, 754*5113495bSYour Name .d_HOST_IS_COPY_COMPLETE_MASK = AR6320_HOST_IS_COPY_COMPLETE_MASK, 755*5113495bSYour Name .d_CE_WRAPPER_BASE_ADDRESS = AR6320_CE_WRAPPER_BASE_ADDRESS, 756*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = 757*5113495bSYour Name AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, 758*5113495bSYour Name .d_HOST_IE_ADDRESS = AR6320_HOST_IE_ADDRESS, 759*5113495bSYour Name .d_HOST_IE_COPY_COMPLETE_MASK = AR6320_HOST_IE_COPY_COMPLETE_MASK, 760*5113495bSYour Name .d_SR_BA_ADDRESS = AR6320_SR_BA_ADDRESS, 761*5113495bSYour Name .d_SR_SIZE_ADDRESS = AR6320_SR_SIZE_ADDRESS, 762*5113495bSYour Name .d_CE_CTRL1_ADDRESS = AR6320_CE_CTRL1_ADDRESS, 763*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320_CE_CTRL1_DMAX_LENGTH_MASK, 764*5113495bSYour Name .d_DR_BA_ADDRESS = AR6320_DR_BA_ADDRESS, 765*5113495bSYour Name .d_DR_SIZE_ADDRESS = AR6320_DR_SIZE_ADDRESS, 766*5113495bSYour Name .d_MISC_IE_ADDRESS = AR6320_MISC_IE_ADDRESS, 767*5113495bSYour Name .d_MISC_IS_AXI_ERR_MASK = AR6320_MISC_IS_AXI_ERR_MASK, 768*5113495bSYour Name .d_MISC_IS_DST_ADDR_ERR_MASK = AR6320_MISC_IS_DST_ADDR_ERR_MASK, 769*5113495bSYour Name .d_MISC_IS_SRC_LEN_ERR_MASK = AR6320_MISC_IS_SRC_LEN_ERR_MASK, 770*5113495bSYour Name .d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK, 771*5113495bSYour Name .d_MISC_IS_DST_RING_OVERFLOW_MASK = 772*5113495bSYour Name AR6320_MISC_IS_DST_RING_OVERFLOW_MASK, 773*5113495bSYour Name .d_MISC_IS_SRC_RING_OVERFLOW_MASK = 774*5113495bSYour Name AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK, 775*5113495bSYour Name .d_SRC_WATERMARK_LOW_LSB = AR6320_SRC_WATERMARK_LOW_LSB, 776*5113495bSYour Name .d_SRC_WATERMARK_HIGH_LSB = AR6320_SRC_WATERMARK_HIGH_LSB, 777*5113495bSYour Name .d_DST_WATERMARK_LOW_LSB = AR6320_DST_WATERMARK_LOW_LSB, 778*5113495bSYour Name .d_DST_WATERMARK_HIGH_LSB = AR6320_DST_WATERMARK_HIGH_LSB, 779*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = 780*5113495bSYour Name AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 781*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = 782*5113495bSYour Name AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 783*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320_CE_CTRL1_DMAX_LENGTH_LSB, 784*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = 785*5113495bSYour Name AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 786*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = 787*5113495bSYour Name AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 788*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = 789*5113495bSYour Name AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 790*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = 791*5113495bSYour Name AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 792*5113495bSYour Name .d_CE_WRAPPER_DEBUG_OFFSET = AR6320_CE_WRAPPER_DEBUG_OFFSET, 793*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320_CE_WRAPPER_DEBUG_SEL_MSB, 794*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320_CE_WRAPPER_DEBUG_SEL_LSB, 795*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320_CE_WRAPPER_DEBUG_SEL_MASK, 796*5113495bSYour Name .d_CE_DEBUG_OFFSET = AR6320_CE_DEBUG_OFFSET, 797*5113495bSYour Name .d_CE_DEBUG_SEL_MSB = AR6320_CE_DEBUG_SEL_MSB, 798*5113495bSYour Name .d_CE_DEBUG_SEL_LSB = AR6320_CE_DEBUG_SEL_LSB, 799*5113495bSYour Name .d_CE_DEBUG_SEL_MASK = AR6320_CE_DEBUG_SEL_MASK, 800*5113495bSYour Name .d_CE0_BASE_ADDRESS = AR6320_CE0_BASE_ADDRESS, 801*5113495bSYour Name .d_CE1_BASE_ADDRESS = AR6320_CE1_BASE_ADDRESS, 802*5113495bSYour Name 803*5113495bSYour Name }; 804*5113495bSYour Name #endif 805*5113495bSYour Name #endif 806