xref: /wlan-driver/qca-wifi-host-cmn/hif/src/ar6320def.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef _AR6320DEF_H_
20 #define  _AR6320DEF_H_
21 
22 /* Base Addresses */
23 #define AR6320_RTC_SOC_BASE_ADDRESS                     0x00000000
24 #define AR6320_RTC_WMAC_BASE_ADDRESS                    0x00001000
25 #define AR6320_MAC_COEX_BASE_ADDRESS                    0x0000f000
26 #define AR6320_BT_COEX_BASE_ADDRESS                     0x00002000
27 #define AR6320_SOC_CORE_BASE_ADDRESS                    0x0003a000
28 #define AR6320_WLAN_UART_BASE_ADDRESS                   0x0000c000
29 #define AR6320_WLAN_SI_BASE_ADDRESS                     0x00010000
30 #define AR6320_WLAN_GPIO_BASE_ADDRESS                   0x00005000
31 #define AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS            0x00006000
32 #define AR6320_WLAN_MAC_BASE_ADDRESS                    0x00010000
33 #define AR6320_EFUSE_BASE_ADDRESS                       0x00024000
34 #define AR6320_FPGA_REG_BASE_ADDRESS                    0x00039000
35 #define AR6320_WLAN_UART2_BASE_ADDRESS                  0x00054c00
36 #define AR6320_DBI_BASE_ADDRESS                         0x0003c000
37 
38 #define AR6320_SCRATCH_3_ADDRESS                        0x0028
39 #define AR6320_TARG_DRAM_START                          0x00400000
40 #define AR6320_SOC_SYSTEM_SLEEP_OFFSET                  0x000000c0
41 #define AR6320_SOC_RESET_CONTROL_OFFSET                 0x00000000
42 #define AR6320_SOC_CLOCK_CONTROL_OFFSET                 0x00000028
43 #define AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
44 #define AR6320_SOC_RESET_CONTROL_SI0_RST_MASK           0x00000000
45 #define AR6320_WLAN_GPIO_PIN0_ADDRESS                   0x00000068
46 #define AR6320_WLAN_GPIO_PIN1_ADDRESS                   0x0000006c
47 #define AR6320_WLAN_GPIO_PIN0_CONFIG_MASK               0x00007800
48 #define AR6320_WLAN_GPIO_PIN1_CONFIG_MASK               0x00007800
49 #define AR6320_SOC_CPU_CLOCK_OFFSET                     0x00000020
50 #define AR6320_SOC_LPO_CAL_OFFSET                       0x000000e0
51 #define AR6320_WLAN_GPIO_PIN10_ADDRESS                  0x00000090
52 #define AR6320_WLAN_GPIO_PIN11_ADDRESS                  0x00000094
53 #define AR6320_WLAN_GPIO_PIN12_ADDRESS                  0x00000098
54 #define AR6320_WLAN_GPIO_PIN13_ADDRESS                  0x0000009c
55 #define AR6320_SOC_CPU_CLOCK_STANDARD_LSB               0
56 #define AR6320_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
57 #define AR6320_SOC_LPO_CAL_ENABLE_LSB                   20
58 #define AR6320_SOC_LPO_CAL_ENABLE_MASK                  0x00100000
59 
60 #define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
61 #define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
62 #define AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000008
63 #define AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000004
64 #define AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB              18
65 #define AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
66 #define AR6320_SI_CONFIG_I2C_LSB                        16
67 #define AR6320_SI_CONFIG_I2C_MASK                       0x00010000
68 #define AR6320_SI_CONFIG_POS_SAMPLE_LSB                 7
69 #define AR6320_SI_CONFIG_POS_SAMPLE_MASK                0x00000080
70 #define AR6320_SI_CONFIG_INACTIVE_CLK_LSB               4
71 #define AR6320_SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
72 #define AR6320_SI_CONFIG_INACTIVE_DATA_LSB              5
73 #define AR6320_SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
74 #define AR6320_SI_CONFIG_DIVIDER_LSB                    0
75 #define AR6320_SI_CONFIG_DIVIDER_MASK                   0x0000000f
76 #define AR6320_SI_CONFIG_OFFSET                         0x00000000
77 #define AR6320_SI_TX_DATA0_OFFSET                       0x00000008
78 #define AR6320_SI_TX_DATA1_OFFSET                       0x0000000c
79 #define AR6320_SI_RX_DATA0_OFFSET                       0x00000010
80 #define AR6320_SI_RX_DATA1_OFFSET                       0x00000014
81 #define AR6320_SI_CS_OFFSET                             0x00000004
82 #define AR6320_SI_CS_DONE_ERR_MASK                      0x00000400
83 #define AR6320_SI_CS_DONE_INT_MASK                      0x00000200
84 #define AR6320_SI_CS_START_LSB                          8
85 #define AR6320_SI_CS_START_MASK                         0x00000100
86 #define AR6320_SI_CS_RX_CNT_LSB                         4
87 #define AR6320_SI_CS_RX_CNT_MASK                        0x000000f0
88 #define AR6320_SI_CS_TX_CNT_LSB                         0
89 #define AR6320_SI_CS_TX_CNT_MASK                        0x0000000f
90 #define AR6320_SR_WR_INDEX_ADDRESS                      0x003c
91 #define AR6320_DST_WATERMARK_ADDRESS                    0x0050
92 #define AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB             14
93 #define AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK            0x00004000
94 #define AR6320_RX_MPDU_START_0_RETRY_LSB                14
95 #define AR6320_RX_MPDU_START_0_RETRY_MASK               0x00004000
96 #define AR6320_RX_MPDU_START_0_SEQ_NUM_LSB              16
97 #define AR6320_RX_MPDU_START_0_SEQ_NUM_MASK             0x0fff0000
98 #define AR6320_RX_MPDU_START_2_TID_LSB                  28
99 #define AR6320_RX_MPDU_START_2_TID_MASK                 0xf0000000
100 #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
101      defined(HIF_IPCI))
102 #define AR6320_SOC_PCIE_BASE_ADDRESS                    0x00038000
103 #define AR6320_CE_WRAPPER_BASE_ADDRESS                  0x00034000
104 #define AR6320_CE0_BASE_ADDRESS                         0x00034400
105 #define AR6320_CE1_BASE_ADDRESS                         0x00034800
106 #define AR6320_CE2_BASE_ADDRESS                         0x00034c00
107 #define AR6320_CE3_BASE_ADDRESS                         0x00035000
108 #define AR6320_CE4_BASE_ADDRESS                         0x00035400
109 #define AR6320_CE5_BASE_ADDRESS                         0x00035800
110 #define AR6320_CE6_BASE_ADDRESS                         0x00035c00
111 #define AR6320_CE7_BASE_ADDRESS                         0x00036000
112 #define AR6320_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS       0x00007800
113 #define AR6320_CE_COUNT                                 8
114 #define AR6320_CE_CTRL1_ADDRESS                         0x0010
115 #define AR6320_CE_CTRL1_DMAX_LENGTH_MASK                0x0000ffff
116 #define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS     0x0000
117 #define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
118 #define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  8
119 #define AR6320_CE_CTRL1_DMAX_LENGTH_LSB                 0
120 #define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK      0x00010000
121 #define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK      0x00020000
122 #define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB       16
123 #define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB       17
124 #define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
125 #define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB  5
126 #define AR6320_PCIE_SOC_WAKE_RESET                      0x00000000
127 #define AR6320_PCIE_SOC_WAKE_ADDRESS                    0x0004
128 #define AR6320_PCIE_SOC_WAKE_V_MASK                     0x00000001
129 #define AR6320_MUX_ID_MASK                              0x0000
130 #define AR6320_TRANSACTION_ID_MASK                      0x3fff
131 #define AR6320_PCIE_LOCAL_BASE_ADDRESS                  0x80000
132 #define AR6320_FW_IND_HELPER                            4
133 #define AR6320_PCIE_INTR_ENABLE_ADDRESS                 0x0008
134 #define AR6320_PCIE_INTR_CLR_ADDRESS                    0x0014
135 #define AR6320_PCIE_INTR_FIRMWARE_MASK                  0x00000400
136 #define AR6320_PCIE_INTR_CE0_MASK                       0x00000800
137 #define AR6320_PCIE_INTR_CE_MASK_ALL                    0x0007f800
138 #define AR6320_PCIE_INTR_CAUSE_ADDRESS                  0x000c
139 #define AR6320_SOC_RESET_CONTROL_CE_RST_MASK            0x00000001
140 #endif
141 #define AR6320_RX_MPDU_START_2_PN_47_32_LSB             0
142 #define AR6320_RX_MPDU_START_2_PN_47_32_MASK            0x0000ffff
143 #define AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK            0x000000ff
144 #define AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB             0
145 #define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB      16
146 #define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK     0xffff0000
147 #define AR6320_RX_MSDU_END_4_LAST_MSDU_LSB              15
148 #define AR6320_RX_MSDU_END_4_LAST_MSDU_MASK             0x00008000
149 #define AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB           2
150 #define AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK          0x00000004
151 #define AR6320_RX_ATTENTION_0_FRAGMENT_LSB              13
152 #define AR6320_RX_ATTENTION_0_FRAGMENT_MASK             0x00002000
153 #define AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK      0x08000000
154 #define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB      16
155 #define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK     0x00ff0000
156 #define AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB          0
157 #define AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK         0x00003fff
158 #define AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET      0x00000008
159 #define AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB         8
160 #define AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK        0x00000300
161 #define AR6320_RX_MPDU_START_0_ENCRYPTED_LSB            13
162 #define AR6320_RX_MPDU_START_0_ENCRYPTED_MASK           0x00002000
163 #define AR6320_RX_ATTENTION_0_MORE_DATA_MASK            0x00000400
164 #define AR6320_RX_ATTENTION_0_MSDU_DONE_MASK            0x80000000
165 #define AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK  0x00040000
166 #define AR6320_DST_WR_INDEX_ADDRESS                     0x0040
167 #define AR6320_SRC_WATERMARK_ADDRESS                    0x004c
168 #define AR6320_SRC_WATERMARK_LOW_MASK                   0xffff0000
169 #define AR6320_SRC_WATERMARK_HIGH_MASK                  0x0000ffff
170 #define AR6320_DST_WATERMARK_LOW_MASK                   0xffff0000
171 #define AR6320_DST_WATERMARK_HIGH_MASK                  0x0000ffff
172 #define AR6320_CURRENT_SRRI_ADDRESS                     0x0044
173 #define AR6320_CURRENT_DRRI_ADDRESS                     0x0048
174 #define AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK     0x00000002
175 #define AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK      0x00000004
176 #define AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK     0x00000008
177 #define AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK      0x00000010
178 #define AR6320_HOST_IS_ADDRESS                          0x0030
179 #define AR6320_HOST_IS_COPY_COMPLETE_MASK               0x00000001
180 #define AR6320_HOST_IE_ADDRESS                          0x002c
181 #define AR6320_HOST_IE_COPY_COMPLETE_MASK               0x00000001
182 #define AR6320_SR_BA_ADDRESS                            0x0000
183 #define AR6320_SR_SIZE_ADDRESS                          0x0004
184 #define AR6320_DR_BA_ADDRESS                            0x0008
185 #define AR6320_DR_SIZE_ADDRESS                          0x000c
186 #define AR6320_MISC_IE_ADDRESS                          0x0034
187 #define AR6320_MISC_IS_AXI_ERR_MASK                     0x00000400
188 #define AR6320_MISC_IS_DST_ADDR_ERR_MASK                0x00000200
189 #define AR6320_MISC_IS_SRC_LEN_ERR_MASK                 0x00000100
190 #define AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK             0x00000080
191 #define AR6320_MISC_IS_DST_RING_OVERFLOW_MASK           0x00000040
192 #define AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK           0x00000020
193 #define AR6320_SRC_WATERMARK_LOW_LSB                    16
194 #define AR6320_SRC_WATERMARK_HIGH_LSB                   0
195 #define AR6320_DST_WATERMARK_LOW_LSB                    16
196 #define AR6320_DST_WATERMARK_HIGH_LSB                   0
197 #define AR6320_SOC_GLOBAL_RESET_ADDRESS                 0x0008
198 #define AR6320_RTC_STATE_ADDRESS                        0x0000
199 #define AR6320_RTC_STATE_COLD_RESET_MASK                0x00002000
200 #define AR6320_RTC_STATE_V_MASK                         0x00000007
201 #define AR6320_RTC_STATE_V_LSB                          0
202 #define AR6320_RTC_STATE_V_ON                           3
203 #define AR6320_FW_IND_EVENT_PENDING                     1
204 #define AR6320_FW_IND_INITIALIZED                       2
205 #define AR6320_CPU_INTR_ADDRESS                         0x0010
206 #define AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
207 #define AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
208 #define AR6320_SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
209 #define AR6320_SOC_RESET_CONTROL_ADDRESS                0x00000000
210 #define AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
211 #define AR6320_CORE_CTRL_ADDRESS                        0x0000
212 #define AR6320_CORE_CTRL_CPU_INTR_MASK                  0x00002000
213 #define AR6320_LOCAL_SCRATCH_OFFSET                     0x000000c0
214 #define AR6320_CLOCK_GPIO_OFFSET                        0xffffffff
215 #define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
216 #define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
217 #define AR6320_SOC_CHIP_ID_ADDRESS                      0x000000f0
218 #define AR6320_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
219 #define AR6320_SOC_CHIP_ID_VERSION_LSB                  18
220 #define AR6320_SOC_CHIP_ID_REVISION_MASK                0x00000f00
221 #define AR6320_SOC_CHIP_ID_REVISION_LSB                 8
222 #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
223      defined(HIF_IPCI))
224 #define AR6320_SOC_POWER_REG_OFFSET                     0x0000010c
225 /* Copy Engine Debug */
226 #define AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
227 #define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
228 #define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
229 #define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
230 #define AR6320_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
231 #define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
232 #define AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
233 #define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
234 #define AR6320_WLAN_DEBUG_OUT_OFFSET                    0x00000110
235 #define AR6320_WLAN_DEBUG_OUT_DATA_MSB                  19
236 #define AR6320_WLAN_DEBUG_OUT_DATA_LSB                  0
237 #define AR6320_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
238 #define AR6320_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
239 #define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
240 #define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
241 #define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
242 #define AR6320_AMBA_DEBUG_BUS_SEL_MSB                   4
243 #define AR6320_AMBA_DEBUG_BUS_SEL_LSB                   0
244 #define AR6320_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
245 #define AR6320_CE_WRAPPER_DEBUG_OFFSET                  0x0008
246 #define AR6320_CE_WRAPPER_DEBUG_SEL_MSB                 5
247 #define AR6320_CE_WRAPPER_DEBUG_SEL_LSB                 0
248 #define AR6320_CE_WRAPPER_DEBUG_SEL_MASK                0x0000003f
249 #define AR6320_CE_DEBUG_OFFSET                          0x0054
250 #define AR6320_CE_DEBUG_SEL_MSB                         5
251 #define AR6320_CE_DEBUG_SEL_LSB                         0
252 #define AR6320_CE_DEBUG_SEL_MASK                        0x0000003f
253 /* End */
254 
255 /* PLL start */
256 #define AR6320_EFUSE_OFFSET                             0x0000032c
257 #define AR6320_EFUSE_XTAL_SEL_MSB                       10
258 #define AR6320_EFUSE_XTAL_SEL_LSB                       8
259 #define AR6320_EFUSE_XTAL_SEL_MASK                      0x00000700
260 #define AR6320_BB_PLL_CONFIG_OFFSET                     0x000002f4
261 #define AR6320_BB_PLL_CONFIG_OUTDIV_MSB                 20
262 #define AR6320_BB_PLL_CONFIG_OUTDIV_LSB                 18
263 #define AR6320_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
264 #define AR6320_BB_PLL_CONFIG_FRAC_MSB                   17
265 #define AR6320_BB_PLL_CONFIG_FRAC_LSB                   0
266 #define AR6320_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
267 #define AR6320_WLAN_PLL_SETTLE_TIME_MSB                 10
268 #define AR6320_WLAN_PLL_SETTLE_TIME_LSB                 0
269 #define AR6320_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
270 #define AR6320_WLAN_PLL_SETTLE_OFFSET                   0x0018
271 #define AR6320_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
272 #define AR6320_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
273 #define AR6320_WLAN_PLL_SETTLE_RESET                    0x00000400
274 #define AR6320_WLAN_PLL_CONTROL_NOPWD_MSB               18
275 #define AR6320_WLAN_PLL_CONTROL_NOPWD_LSB               18
276 #define AR6320_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
277 #define AR6320_WLAN_PLL_CONTROL_BYPASS_MSB              16
278 #define AR6320_WLAN_PLL_CONTROL_BYPASS_LSB              16
279 #define AR6320_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
280 #define AR6320_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
281 #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
282 #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
283 #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
284 #define AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
285 #define AR6320_WLAN_PLL_CONTROL_REFDIV_MSB              13
286 #define AR6320_WLAN_PLL_CONTROL_REFDIV_LSB              10
287 #define AR6320_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
288 #define AR6320_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
289 #define AR6320_WLAN_PLL_CONTROL_DIV_MSB                 9
290 #define AR6320_WLAN_PLL_CONTROL_DIV_LSB                 0
291 #define AR6320_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
292 #define AR6320_WLAN_PLL_CONTROL_DIV_RESET               0x11
293 #define AR6320_WLAN_PLL_CONTROL_OFFSET                  0x0014
294 #define AR6320_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
295 #define AR6320_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
296 #define AR6320_WLAN_PLL_CONTROL_RESET                   0x00010011
297 #define AR6320_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
298 #define AR6320_SOC_CORE_CLK_CTRL_DIV_MSB                2
299 #define AR6320_SOC_CORE_CLK_CTRL_DIV_LSB                0
300 #define AR6320_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
301 #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
302 #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
303 #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
304 #define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
305 #define AR6320_RTC_SYNC_STATUS_OFFSET                   0x0244
306 #define AR6320_SOC_CPU_CLOCK_OFFSET                     0x00000020
307 #define AR6320_SOC_CPU_CLOCK_STANDARD_MSB               1
308 #define AR6320_SOC_CPU_CLOCK_STANDARD_LSB               0
309 #define AR6320_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
310 /* PLL end */
311 #define AR6320_PCIE_INTR_CE_MASK(n) \
312 	(AR6320_PCIE_INTR_CE0_MASK << (n))
313 #endif
314 #define AR6320_DRAM_BASE_ADDRESS          AR6320_TARG_DRAM_START
315 #define AR6320_FW_INDICATOR_ADDRESS \
316 	(AR6320_SOC_CORE_BASE_ADDRESS + AR6320_SCRATCH_3_ADDRESS)
317 #define AR6320_SYSTEM_SLEEP_OFFSET        AR6320_SOC_SYSTEM_SLEEP_OFFSET
318 #define AR6320_WLAN_SYSTEM_SLEEP_OFFSET   0x002c
319 #define AR6320_WLAN_RESET_CONTROL_OFFSET  AR6320_SOC_RESET_CONTROL_OFFSET
320 #define AR6320_CLOCK_CONTROL_OFFSET       AR6320_SOC_CLOCK_CONTROL_OFFSET
321 #define AR6320_CLOCK_CONTROL_SI0_CLK_MASK AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK
322 #define AR6320_RESET_CONTROL_MBOX_RST_MASK 0x00000004
323 #define AR6320_RESET_CONTROL_SI0_RST_MASK AR6320_SOC_RESET_CONTROL_SI0_RST_MASK
324 #define AR6320_GPIO_BASE_ADDRESS          AR6320_WLAN_GPIO_BASE_ADDRESS
325 #define AR6320_GPIO_PIN0_OFFSET           AR6320_WLAN_GPIO_PIN0_ADDRESS
326 #define AR6320_GPIO_PIN1_OFFSET           AR6320_WLAN_GPIO_PIN1_ADDRESS
327 #define AR6320_GPIO_PIN0_CONFIG_MASK      AR6320_WLAN_GPIO_PIN0_CONFIG_MASK
328 #define AR6320_GPIO_PIN1_CONFIG_MASK      AR6320_WLAN_GPIO_PIN1_CONFIG_MASK
329 #define AR6320_SI_BASE_ADDRESS            0x00050000
330 #define AR6320_CPU_CLOCK_OFFSET           AR6320_SOC_CPU_CLOCK_OFFSET
331 #define AR6320_LPO_CAL_OFFSET             AR6320_SOC_LPO_CAL_OFFSET
332 #define AR6320_GPIO_PIN10_OFFSET          AR6320_WLAN_GPIO_PIN10_ADDRESS
333 #define AR6320_GPIO_PIN11_OFFSET          AR6320_WLAN_GPIO_PIN11_ADDRESS
334 #define AR6320_GPIO_PIN12_OFFSET          AR6320_WLAN_GPIO_PIN12_ADDRESS
335 #define AR6320_GPIO_PIN13_OFFSET          AR6320_WLAN_GPIO_PIN13_ADDRESS
336 #define AR6320_CPU_CLOCK_STANDARD_LSB     AR6320_SOC_CPU_CLOCK_STANDARD_LSB
337 #define AR6320_CPU_CLOCK_STANDARD_MASK    AR6320_SOC_CPU_CLOCK_STANDARD_MASK
338 #define AR6320_LPO_CAL_ENABLE_LSB         AR6320_SOC_LPO_CAL_ENABLE_LSB
339 #define AR6320_LPO_CAL_ENABLE_MASK        AR6320_SOC_LPO_CAL_ENABLE_MASK
340 #define AR6320_ANALOG_INTF_BASE_ADDRESS   AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS
341 #define AR6320_MBOX_BASE_ADDRESS                       0x00008000
342 #define AR6320_INT_STATUS_ENABLE_ERROR_LSB             7
343 #define AR6320_INT_STATUS_ENABLE_ERROR_MASK            0x00000080
344 #define AR6320_INT_STATUS_ENABLE_CPU_LSB               6
345 #define AR6320_INT_STATUS_ENABLE_CPU_MASK              0x00000040
346 #define AR6320_INT_STATUS_ENABLE_COUNTER_LSB           4
347 #define AR6320_INT_STATUS_ENABLE_COUNTER_MASK          0x00000010
348 #define AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB         0
349 #define AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK        0x0000000f
350 #define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    17
351 #define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   0x00020000
352 #define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     16
353 #define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    0x00010000
354 #define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB       24
355 #define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK      0xff000000
356 #define AR6320_INT_STATUS_ENABLE_ADDRESS               0x0828
357 #define AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB           8
358 #define AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK          0x0000ff00
359 #define AR6320_HOST_INT_STATUS_ADDRESS                 0x0800
360 #define AR6320_CPU_INT_STATUS_ADDRESS                  0x0801
361 #define AR6320_ERROR_INT_STATUS_ADDRESS                0x0802
362 #define AR6320_ERROR_INT_STATUS_WAKEUP_MASK            0x00040000
363 #define AR6320_ERROR_INT_STATUS_WAKEUP_LSB             18
364 #define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      0x00020000
365 #define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       17
366 #define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK       0x00010000
367 #define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB        16
368 #define AR6320_COUNT_DEC_ADDRESS                       0x0840
369 #define AR6320_HOST_INT_STATUS_CPU_MASK                0x00000040
370 #define AR6320_HOST_INT_STATUS_CPU_LSB                 6
371 #define AR6320_HOST_INT_STATUS_ERROR_MASK              0x00000080
372 #define AR6320_HOST_INT_STATUS_ERROR_LSB               7
373 #define AR6320_HOST_INT_STATUS_COUNTER_MASK            0x00000010
374 #define AR6320_HOST_INT_STATUS_COUNTER_LSB             4
375 #define AR6320_RX_LOOKAHEAD_VALID_ADDRESS              0x0805
376 #define AR6320_WINDOW_DATA_ADDRESS                     0x0874
377 #define AR6320_WINDOW_READ_ADDR_ADDRESS                0x087c
378 #define AR6320_WINDOW_WRITE_ADDR_ADDRESS               0x0878
379 #define AR6320_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f
380 #define AR6320_HOST_INT_STATUS_MBOX_DATA_LSB 0
381 
382 struct targetdef_s ar6320_targetdef = {
383 	.d_RTC_SOC_BASE_ADDRESS = AR6320_RTC_SOC_BASE_ADDRESS,
384 	.d_RTC_WMAC_BASE_ADDRESS = AR6320_RTC_WMAC_BASE_ADDRESS,
385 	.d_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET,
386 	.d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET,
387 	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
388 		AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
389 	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
390 		AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
391 	.d_CLOCK_CONTROL_OFFSET = AR6320_CLOCK_CONTROL_OFFSET,
392 	.d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320_CLOCK_CONTROL_SI0_CLK_MASK,
393 	.d_RESET_CONTROL_OFFSET = AR6320_SOC_RESET_CONTROL_OFFSET,
394 	.d_RESET_CONTROL_MBOX_RST_MASK = AR6320_RESET_CONTROL_MBOX_RST_MASK,
395 	.d_RESET_CONTROL_SI0_RST_MASK = AR6320_RESET_CONTROL_SI0_RST_MASK,
396 	.d_WLAN_RESET_CONTROL_OFFSET = AR6320_WLAN_RESET_CONTROL_OFFSET,
397 	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
398 		AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK,
399 	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
400 		AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK,
401 	.d_GPIO_BASE_ADDRESS = AR6320_GPIO_BASE_ADDRESS,
402 	.d_GPIO_PIN0_OFFSET = AR6320_GPIO_PIN0_OFFSET,
403 	.d_GPIO_PIN1_OFFSET = AR6320_GPIO_PIN1_OFFSET,
404 	.d_GPIO_PIN0_CONFIG_MASK = AR6320_GPIO_PIN0_CONFIG_MASK,
405 	.d_GPIO_PIN1_CONFIG_MASK = AR6320_GPIO_PIN1_CONFIG_MASK,
406 	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB,
407 	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK,
408 	.d_SI_CONFIG_I2C_LSB = AR6320_SI_CONFIG_I2C_LSB,
409 	.d_SI_CONFIG_I2C_MASK = AR6320_SI_CONFIG_I2C_MASK,
410 	.d_SI_CONFIG_POS_SAMPLE_LSB = AR6320_SI_CONFIG_POS_SAMPLE_LSB,
411 	.d_SI_CONFIG_POS_SAMPLE_MASK = AR6320_SI_CONFIG_POS_SAMPLE_MASK,
412 	.d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320_SI_CONFIG_INACTIVE_CLK_LSB,
413 	.d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320_SI_CONFIG_INACTIVE_CLK_MASK,
414 	.d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320_SI_CONFIG_INACTIVE_DATA_LSB,
415 	.d_SI_CONFIG_INACTIVE_DATA_MASK = AR6320_SI_CONFIG_INACTIVE_DATA_MASK,
416 	.d_SI_CONFIG_DIVIDER_LSB = AR6320_SI_CONFIG_DIVIDER_LSB,
417 	.d_SI_CONFIG_DIVIDER_MASK = AR6320_SI_CONFIG_DIVIDER_MASK,
418 	.d_SI_BASE_ADDRESS = AR6320_SI_BASE_ADDRESS,
419 	.d_SI_CONFIG_OFFSET = AR6320_SI_CONFIG_OFFSET,
420 	.d_SI_TX_DATA0_OFFSET = AR6320_SI_TX_DATA0_OFFSET,
421 	.d_SI_TX_DATA1_OFFSET = AR6320_SI_TX_DATA1_OFFSET,
422 	.d_SI_RX_DATA0_OFFSET = AR6320_SI_RX_DATA0_OFFSET,
423 	.d_SI_RX_DATA1_OFFSET = AR6320_SI_RX_DATA1_OFFSET,
424 	.d_SI_CS_OFFSET = AR6320_SI_CS_OFFSET,
425 	.d_SI_CS_DONE_ERR_MASK = AR6320_SI_CS_DONE_ERR_MASK,
426 	.d_SI_CS_DONE_INT_MASK = AR6320_SI_CS_DONE_INT_MASK,
427 	.d_SI_CS_START_LSB = AR6320_SI_CS_START_LSB,
428 	.d_SI_CS_START_MASK = AR6320_SI_CS_START_MASK,
429 	.d_SI_CS_RX_CNT_LSB = AR6320_SI_CS_RX_CNT_LSB,
430 	.d_SI_CS_RX_CNT_MASK = AR6320_SI_CS_RX_CNT_MASK,
431 	.d_SI_CS_TX_CNT_LSB = AR6320_SI_CS_TX_CNT_LSB,
432 	.d_SI_CS_TX_CNT_MASK = AR6320_SI_CS_TX_CNT_MASK,
433 	.d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ,
434 	.d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ,
435 	.d_MBOX_BASE_ADDRESS = AR6320_MBOX_BASE_ADDRESS,
436 	.d_LOCAL_SCRATCH_OFFSET = AR6320_LOCAL_SCRATCH_OFFSET,
437 	.d_CPU_CLOCK_OFFSET = AR6320_CPU_CLOCK_OFFSET,
438 	.d_LPO_CAL_OFFSET = AR6320_LPO_CAL_OFFSET,
439 	.d_GPIO_PIN10_OFFSET = AR6320_GPIO_PIN10_OFFSET,
440 	.d_GPIO_PIN11_OFFSET = AR6320_GPIO_PIN11_OFFSET,
441 	.d_GPIO_PIN12_OFFSET = AR6320_GPIO_PIN12_OFFSET,
442 	.d_GPIO_PIN13_OFFSET = AR6320_GPIO_PIN13_OFFSET,
443 	.d_CLOCK_GPIO_OFFSET = AR6320_CLOCK_GPIO_OFFSET,
444 	.d_CPU_CLOCK_STANDARD_LSB = AR6320_CPU_CLOCK_STANDARD_LSB,
445 	.d_CPU_CLOCK_STANDARD_MASK = AR6320_CPU_CLOCK_STANDARD_MASK,
446 	.d_LPO_CAL_ENABLE_LSB = AR6320_LPO_CAL_ENABLE_LSB,
447 	.d_LPO_CAL_ENABLE_MASK = AR6320_LPO_CAL_ENABLE_MASK,
448 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
449 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
450 		AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
451 	.d_ANALOG_INTF_BASE_ADDRESS = AR6320_ANALOG_INTF_BASE_ADDRESS,
452 	.d_WLAN_MAC_BASE_ADDRESS = AR6320_WLAN_MAC_BASE_ADDRESS,
453 	.d_FW_INDICATOR_ADDRESS = AR6320_FW_INDICATOR_ADDRESS,
454 	.d_DRAM_BASE_ADDRESS = AR6320_DRAM_BASE_ADDRESS,
455 	.d_SOC_CORE_BASE_ADDRESS = AR6320_SOC_CORE_BASE_ADDRESS,
456 	.d_CORE_CTRL_ADDRESS = AR6320_CORE_CTRL_ADDRESS,
457 #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
458      defined(HIF_IPCI))
459 	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
460 	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
461 #endif
462 	.d_CORE_CTRL_CPU_INTR_MASK = AR6320_CORE_CTRL_CPU_INTR_MASK,
463 	.d_SR_WR_INDEX_ADDRESS = AR6320_SR_WR_INDEX_ADDRESS,
464 	.d_DST_WATERMARK_ADDRESS = AR6320_DST_WATERMARK_ADDRESS,
465 	/* htt_rx.c */
466 	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
467 		AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK,
468 	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB,
469 	.d_RX_MPDU_START_0_RETRY_LSB = AR6320_RX_MPDU_START_0_RETRY_LSB,
470 	.d_RX_MPDU_START_0_RETRY_MASK = AR6320_RX_MPDU_START_0_RETRY_MASK,
471 	.d_RX_MPDU_START_0_SEQ_NUM_MASK = AR6320_RX_MPDU_START_0_SEQ_NUM_MASK,
472 	.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320_RX_MPDU_START_0_SEQ_NUM_LSB,
473 	.d_RX_MPDU_START_2_PN_47_32_LSB = AR6320_RX_MPDU_START_2_PN_47_32_LSB,
474 	.d_RX_MPDU_START_2_PN_47_32_MASK =
475 		AR6320_RX_MPDU_START_2_PN_47_32_MASK,
476 	.d_RX_MPDU_START_2_TID_LSB = AR6320_RX_MPDU_START_2_TID_LSB,
477 	.d_RX_MPDU_START_2_TID_MASK = AR6320_RX_MPDU_START_2_TID_MASK,
478 	.d_RX_MSDU_END_1_KEY_ID_OCT_MASK =
479 		AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK,
480 	.d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB,
481 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
482 		AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
483 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
484 		AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
485 	.d_RX_MSDU_END_4_LAST_MSDU_MASK = AR6320_RX_MSDU_END_4_LAST_MSDU_MASK,
486 	.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320_RX_MSDU_END_4_LAST_MSDU_LSB,
487 	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
488 		AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK,
489 	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
490 		AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB,
491 	.d_RX_ATTENTION_0_FRAGMENT_MASK = AR6320_RX_ATTENTION_0_FRAGMENT_MASK,
492 	.d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320_RX_ATTENTION_0_FRAGMENT_LSB,
493 	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
494 		AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
495 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
496 		AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
497 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
498 		AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
499 	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
500 		AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK,
501 	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
502 		AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB,
503 	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
504 		AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
505 	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
506 		AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK,
507 	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
508 		AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB,
509 	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
510 		AR6320_RX_MPDU_START_0_ENCRYPTED_MASK,
511 	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
512 		AR6320_RX_MPDU_START_0_ENCRYPTED_LSB,
513 	.d_RX_ATTENTION_0_MORE_DATA_MASK =
514 		AR6320_RX_ATTENTION_0_MORE_DATA_MASK,
515 	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
516 		AR6320_RX_ATTENTION_0_MSDU_DONE_MASK,
517 	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
518 		AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
519 #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
520      defined(HIF_IPCI))
521 	.d_CE_COUNT = AR6320_CE_COUNT,
522 	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
523 	.d_PCIE_INTR_ENABLE_ADDRESS = AR6320_PCIE_INTR_ENABLE_ADDRESS,
524 	.d_PCIE_INTR_CLR_ADDRESS = AR6320_PCIE_INTR_CLR_ADDRESS,
525 	.d_PCIE_INTR_FIRMWARE_MASK = AR6320_PCIE_INTR_FIRMWARE_MASK,
526 	.d_PCIE_INTR_CE_MASK_ALL = AR6320_PCIE_INTR_CE_MASK_ALL,
527     /* PLL start */
528 	.d_EFUSE_OFFSET = AR6320_EFUSE_OFFSET,
529 	.d_EFUSE_XTAL_SEL_MSB = AR6320_EFUSE_XTAL_SEL_MSB,
530 	.d_EFUSE_XTAL_SEL_LSB = AR6320_EFUSE_XTAL_SEL_LSB,
531 	.d_EFUSE_XTAL_SEL_MASK = AR6320_EFUSE_XTAL_SEL_MASK,
532 	.d_BB_PLL_CONFIG_OFFSET = AR6320_BB_PLL_CONFIG_OFFSET,
533 	.d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320_BB_PLL_CONFIG_OUTDIV_MSB,
534 	.d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320_BB_PLL_CONFIG_OUTDIV_LSB,
535 	.d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320_BB_PLL_CONFIG_OUTDIV_MASK,
536 	.d_BB_PLL_CONFIG_FRAC_MSB = AR6320_BB_PLL_CONFIG_FRAC_MSB,
537 	.d_BB_PLL_CONFIG_FRAC_LSB = AR6320_BB_PLL_CONFIG_FRAC_LSB,
538 	.d_BB_PLL_CONFIG_FRAC_MASK = AR6320_BB_PLL_CONFIG_FRAC_MASK,
539 	.d_WLAN_PLL_SETTLE_TIME_MSB = AR6320_WLAN_PLL_SETTLE_TIME_MSB,
540 	.d_WLAN_PLL_SETTLE_TIME_LSB = AR6320_WLAN_PLL_SETTLE_TIME_LSB,
541 	.d_WLAN_PLL_SETTLE_TIME_MASK = AR6320_WLAN_PLL_SETTLE_TIME_MASK,
542 	.d_WLAN_PLL_SETTLE_OFFSET = AR6320_WLAN_PLL_SETTLE_OFFSET,
543 	.d_WLAN_PLL_SETTLE_SW_MASK = AR6320_WLAN_PLL_SETTLE_SW_MASK,
544 	.d_WLAN_PLL_SETTLE_RSTMASK = AR6320_WLAN_PLL_SETTLE_RSTMASK,
545 	.d_WLAN_PLL_SETTLE_RESET = AR6320_WLAN_PLL_SETTLE_RESET,
546 	.d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320_WLAN_PLL_CONTROL_NOPWD_MSB,
547 	.d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320_WLAN_PLL_CONTROL_NOPWD_LSB,
548 	.d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320_WLAN_PLL_CONTROL_NOPWD_MASK,
549 	.d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320_WLAN_PLL_CONTROL_BYPASS_MSB,
550 	.d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320_WLAN_PLL_CONTROL_BYPASS_LSB,
551 	.d_WLAN_PLL_CONTROL_BYPASS_MASK = AR6320_WLAN_PLL_CONTROL_BYPASS_MASK,
552 	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
553 		AR6320_WLAN_PLL_CONTROL_BYPASS_RESET,
554 	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB,
555 	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB,
556 	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
557 		AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK,
558 	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
559 		AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET,
560 	.d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320_WLAN_PLL_CONTROL_REFDIV_MSB,
561 	.d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320_WLAN_PLL_CONTROL_REFDIV_LSB,
562 	.d_WLAN_PLL_CONTROL_REFDIV_MASK = AR6320_WLAN_PLL_CONTROL_REFDIV_MASK,
563 	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
564 		AR6320_WLAN_PLL_CONTROL_REFDIV_RESET,
565 	.d_WLAN_PLL_CONTROL_DIV_MSB = AR6320_WLAN_PLL_CONTROL_DIV_MSB,
566 	.d_WLAN_PLL_CONTROL_DIV_LSB = AR6320_WLAN_PLL_CONTROL_DIV_LSB,
567 	.d_WLAN_PLL_CONTROL_DIV_MASK = AR6320_WLAN_PLL_CONTROL_DIV_MASK,
568 	.d_WLAN_PLL_CONTROL_DIV_RESET = AR6320_WLAN_PLL_CONTROL_DIV_RESET,
569 	.d_WLAN_PLL_CONTROL_OFFSET = AR6320_WLAN_PLL_CONTROL_OFFSET,
570 	.d_WLAN_PLL_CONTROL_SW_MASK = AR6320_WLAN_PLL_CONTROL_SW_MASK,
571 	.d_WLAN_PLL_CONTROL_RSTMASK = AR6320_WLAN_PLL_CONTROL_RSTMASK,
572 	.d_WLAN_PLL_CONTROL_RESET = AR6320_WLAN_PLL_CONTROL_RESET,
573 	.d_SOC_CORE_CLK_CTRL_OFFSET = AR6320_SOC_CORE_CLK_CTRL_OFFSET,
574 	.d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320_SOC_CORE_CLK_CTRL_DIV_MSB,
575 	.d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320_SOC_CORE_CLK_CTRL_DIV_LSB,
576 	.d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320_SOC_CORE_CLK_CTRL_DIV_MASK,
577 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
578 		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
579 	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
580 		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
581 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
582 		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
583 	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
584 		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
585 	.d_RTC_SYNC_STATUS_OFFSET = AR6320_RTC_SYNC_STATUS_OFFSET,
586 	.d_SOC_CPU_CLOCK_OFFSET = AR6320_SOC_CPU_CLOCK_OFFSET,
587 	.d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320_SOC_CPU_CLOCK_STANDARD_MSB,
588 	.d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320_SOC_CPU_CLOCK_STANDARD_LSB,
589 	.d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320_SOC_CPU_CLOCK_STANDARD_MASK,
590 	/* PLL end */
591 	.d_SOC_POWER_REG_OFFSET = AR6320_SOC_POWER_REG_OFFSET,
592 	.d_PCIE_INTR_CAUSE_ADDRESS = AR6320_PCIE_INTR_CAUSE_ADDRESS,
593 	.d_SOC_RESET_CONTROL_ADDRESS = AR6320_SOC_RESET_CONTROL_ADDRESS,
594 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
595 		AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
596 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
597 		AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
598 	.d_SOC_RESET_CONTROL_CE_RST_MASK =
599 		AR6320_SOC_RESET_CONTROL_CE_RST_MASK,
600 	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
601 		AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
602 	.d_CPU_INTR_ADDRESS = AR6320_CPU_INTR_ADDRESS,
603 	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
604 		AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS,
605 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
606 		AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
607 	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
608 		AR6320_SOC_LF_TIMER_STATUS0_ADDRESS,
609 
610 	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET,
611 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
612 	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
613 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
614 		AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
615 	.d_WLAN_DEBUG_CONTROL_OFFSET = AR6320_WLAN_DEBUG_CONTROL_OFFSET,
616 	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
617 		AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB,
618 	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
619 		AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB,
620 	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
621 		AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK,
622 	.d_WLAN_DEBUG_OUT_OFFSET = AR6320_WLAN_DEBUG_OUT_OFFSET,
623 	.d_WLAN_DEBUG_OUT_DATA_MSB = AR6320_WLAN_DEBUG_OUT_DATA_MSB,
624 	.d_WLAN_DEBUG_OUT_DATA_LSB = AR6320_WLAN_DEBUG_OUT_DATA_LSB,
625 	.d_WLAN_DEBUG_OUT_DATA_MASK = AR6320_WLAN_DEBUG_OUT_DATA_MASK,
626 	.d_AMBA_DEBUG_BUS_OFFSET = AR6320_AMBA_DEBUG_BUS_OFFSET,
627 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
628 		AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
629 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
630 		AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
631 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
632 		AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
633 	.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320_AMBA_DEBUG_BUS_SEL_MSB,
634 	.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320_AMBA_DEBUG_BUS_SEL_LSB,
635 	.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320_AMBA_DEBUG_BUS_SEL_MASK,
636 #endif
637 	/* chip id start */
638 	.d_SOC_CHIP_ID_ADDRESS = AR6320_SOC_CHIP_ID_ADDRESS,
639 	.d_SOC_CHIP_ID_VERSION_MASK = AR6320_SOC_CHIP_ID_VERSION_MASK,
640 	.d_SOC_CHIP_ID_VERSION_LSB = AR6320_SOC_CHIP_ID_VERSION_LSB,
641 	.d_SOC_CHIP_ID_REVISION_MASK = AR6320_SOC_CHIP_ID_REVISION_MASK,
642 	.d_SOC_CHIP_ID_REVISION_LSB = AR6320_SOC_CHIP_ID_REVISION_LSB,
643 	/* chip id end */
644 };
645 
646 struct hostdef_s ar6320_hostdef = {
647 	.d_INT_STATUS_ENABLE_ERROR_LSB = AR6320_INT_STATUS_ENABLE_ERROR_LSB,
648 	.d_INT_STATUS_ENABLE_ERROR_MASK = AR6320_INT_STATUS_ENABLE_ERROR_MASK,
649 	.d_INT_STATUS_ENABLE_CPU_LSB = AR6320_INT_STATUS_ENABLE_CPU_LSB,
650 	.d_INT_STATUS_ENABLE_CPU_MASK = AR6320_INT_STATUS_ENABLE_CPU_MASK,
651 	.d_INT_STATUS_ENABLE_COUNTER_LSB =
652 		AR6320_INT_STATUS_ENABLE_COUNTER_LSB,
653 	.d_INT_STATUS_ENABLE_COUNTER_MASK =
654 		AR6320_INT_STATUS_ENABLE_COUNTER_MASK,
655 	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
656 		AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB,
657 	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
658 		AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK,
659 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
660 		AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
661 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
662 		AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
663 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
664 		AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
665 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
666 		AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
667 	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
668 		AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
669 	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
670 		AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
671 	.d_INT_STATUS_ENABLE_ADDRESS = AR6320_INT_STATUS_ENABLE_ADDRESS,
672 	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
673 		AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB,
674 	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
675 		AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK,
676 	.d_HOST_INT_STATUS_ADDRESS = AR6320_HOST_INT_STATUS_ADDRESS,
677 	.d_CPU_INT_STATUS_ADDRESS = AR6320_CPU_INT_STATUS_ADDRESS,
678 	.d_ERROR_INT_STATUS_ADDRESS = AR6320_ERROR_INT_STATUS_ADDRESS,
679 	.d_ERROR_INT_STATUS_WAKEUP_MASK = AR6320_ERROR_INT_STATUS_WAKEUP_MASK,
680 	.d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320_ERROR_INT_STATUS_WAKEUP_LSB,
681 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
682 		AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
683 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
684 		AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
685 	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
686 		AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
687 	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
688 		AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
689 	.d_COUNT_DEC_ADDRESS = AR6320_COUNT_DEC_ADDRESS,
690 	.d_HOST_INT_STATUS_CPU_MASK = AR6320_HOST_INT_STATUS_CPU_MASK,
691 	.d_HOST_INT_STATUS_CPU_LSB = AR6320_HOST_INT_STATUS_CPU_LSB,
692 	.d_HOST_INT_STATUS_ERROR_MASK = AR6320_HOST_INT_STATUS_ERROR_MASK,
693 	.d_HOST_INT_STATUS_ERROR_LSB = AR6320_HOST_INT_STATUS_ERROR_LSB,
694 	.d_HOST_INT_STATUS_COUNTER_MASK = AR6320_HOST_INT_STATUS_COUNTER_MASK,
695 	.d_HOST_INT_STATUS_COUNTER_LSB = AR6320_HOST_INT_STATUS_COUNTER_LSB,
696 	.d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320_RX_LOOKAHEAD_VALID_ADDRESS,
697 	.d_WINDOW_DATA_ADDRESS = AR6320_WINDOW_DATA_ADDRESS,
698 	.d_WINDOW_READ_ADDR_ADDRESS = AR6320_WINDOW_READ_ADDR_ADDRESS,
699 	.d_WINDOW_WRITE_ADDR_ADDRESS = AR6320_WINDOW_WRITE_ADDR_ADDRESS,
700 	.d_SOC_GLOBAL_RESET_ADDRESS = AR6320_SOC_GLOBAL_RESET_ADDRESS,
701 	.d_RTC_STATE_ADDRESS = AR6320_RTC_STATE_ADDRESS,
702 	.d_RTC_STATE_COLD_RESET_MASK = AR6320_RTC_STATE_COLD_RESET_MASK,
703 #if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
704      defined(HIF_IPCI))
705 	.d_PCIE_LOCAL_BASE_ADDRESS = AR6320_PCIE_LOCAL_BASE_ADDRESS,
706 	.d_PCIE_SOC_WAKE_RESET = AR6320_PCIE_SOC_WAKE_RESET,
707 	.d_PCIE_SOC_WAKE_ADDRESS = AR6320_PCIE_SOC_WAKE_ADDRESS,
708 	.d_PCIE_SOC_WAKE_V_MASK = AR6320_PCIE_SOC_WAKE_V_MASK,
709 	.d_MUX_ID_MASK = AR6320_MUX_ID_MASK,
710 	.d_TRANSACTION_ID_MASK = AR6320_TRANSACTION_ID_MASK,
711 	.d_FW_IND_HELPER = AR6320_FW_IND_HELPER,
712 	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
713 	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
714 	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
715 	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
716 	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
717 	.d_HOST_CE_COUNT = 8,
718 	.d_ENABLE_MSI = 0,
719 #endif
720 	.d_RTC_STATE_V_MASK = AR6320_RTC_STATE_V_MASK,
721 	.d_RTC_STATE_V_LSB = AR6320_RTC_STATE_V_LSB,
722 	.d_FW_IND_EVENT_PENDING = AR6320_FW_IND_EVENT_PENDING,
723 	.d_FW_IND_INITIALIZED = AR6320_FW_IND_INITIALIZED,
724 	.d_RTC_STATE_V_ON = AR6320_RTC_STATE_V_ON,
725 #if defined(SDIO_3_0)
726 	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
727 		AR6320_HOST_INT_STATUS_MBOX_DATA_MASK,
728 	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
729 		AR6320_HOST_INT_STATUS_MBOX_DATA_LSB,
730 #endif
731 };
732 
733 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
734     defined(HIF_IPCI)
735 struct ce_reg_def ar6320_ce_targetdef = {
736 	/* copy_engine.c  */
737 	.d_DST_WR_INDEX_ADDRESS = AR6320_DST_WR_INDEX_ADDRESS,
738 	.d_SRC_WATERMARK_ADDRESS = AR6320_SRC_WATERMARK_ADDRESS,
739 	.d_SRC_WATERMARK_LOW_MASK = AR6320_SRC_WATERMARK_LOW_MASK,
740 	.d_SRC_WATERMARK_HIGH_MASK = AR6320_SRC_WATERMARK_HIGH_MASK,
741 	.d_DST_WATERMARK_LOW_MASK = AR6320_DST_WATERMARK_LOW_MASK,
742 	.d_DST_WATERMARK_HIGH_MASK = AR6320_DST_WATERMARK_HIGH_MASK,
743 	.d_CURRENT_SRRI_ADDRESS = AR6320_CURRENT_SRRI_ADDRESS,
744 	.d_CURRENT_DRRI_ADDRESS = AR6320_CURRENT_DRRI_ADDRESS,
745 	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
746 		AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
747 	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
748 		AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
749 	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
750 		AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
751 	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
752 		AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
753 	.d_HOST_IS_ADDRESS = AR6320_HOST_IS_ADDRESS,
754 	.d_HOST_IS_COPY_COMPLETE_MASK = AR6320_HOST_IS_COPY_COMPLETE_MASK,
755 	.d_CE_WRAPPER_BASE_ADDRESS = AR6320_CE_WRAPPER_BASE_ADDRESS,
756 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
757 		AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
758 	.d_HOST_IE_ADDRESS = AR6320_HOST_IE_ADDRESS,
759 	.d_HOST_IE_COPY_COMPLETE_MASK = AR6320_HOST_IE_COPY_COMPLETE_MASK,
760 	.d_SR_BA_ADDRESS = AR6320_SR_BA_ADDRESS,
761 	.d_SR_SIZE_ADDRESS = AR6320_SR_SIZE_ADDRESS,
762 	.d_CE_CTRL1_ADDRESS = AR6320_CE_CTRL1_ADDRESS,
763 	.d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320_CE_CTRL1_DMAX_LENGTH_MASK,
764 	.d_DR_BA_ADDRESS = AR6320_DR_BA_ADDRESS,
765 	.d_DR_SIZE_ADDRESS = AR6320_DR_SIZE_ADDRESS,
766 	.d_MISC_IE_ADDRESS = AR6320_MISC_IE_ADDRESS,
767 	.d_MISC_IS_AXI_ERR_MASK = AR6320_MISC_IS_AXI_ERR_MASK,
768 	.d_MISC_IS_DST_ADDR_ERR_MASK = AR6320_MISC_IS_DST_ADDR_ERR_MASK,
769 	.d_MISC_IS_SRC_LEN_ERR_MASK = AR6320_MISC_IS_SRC_LEN_ERR_MASK,
770 	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK,
771 	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
772 		AR6320_MISC_IS_DST_RING_OVERFLOW_MASK,
773 	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
774 		AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK,
775 	.d_SRC_WATERMARK_LOW_LSB = AR6320_SRC_WATERMARK_LOW_LSB,
776 	.d_SRC_WATERMARK_HIGH_LSB = AR6320_SRC_WATERMARK_HIGH_LSB,
777 	.d_DST_WATERMARK_LOW_LSB = AR6320_DST_WATERMARK_LOW_LSB,
778 	.d_DST_WATERMARK_HIGH_LSB = AR6320_DST_WATERMARK_HIGH_LSB,
779 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
780 		AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
781 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
782 		AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
783 	.d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320_CE_CTRL1_DMAX_LENGTH_LSB,
784 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
785 		AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
786 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
787 		AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
788 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
789 		AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
790 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
791 		AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
792 	.d_CE_WRAPPER_DEBUG_OFFSET = AR6320_CE_WRAPPER_DEBUG_OFFSET,
793 	.d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320_CE_WRAPPER_DEBUG_SEL_MSB,
794 	.d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320_CE_WRAPPER_DEBUG_SEL_LSB,
795 	.d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320_CE_WRAPPER_DEBUG_SEL_MASK,
796 	.d_CE_DEBUG_OFFSET = AR6320_CE_DEBUG_OFFSET,
797 	.d_CE_DEBUG_SEL_MSB = AR6320_CE_DEBUG_SEL_MSB,
798 	.d_CE_DEBUG_SEL_LSB = AR6320_CE_DEBUG_SEL_LSB,
799 	.d_CE_DEBUG_SEL_MASK = AR6320_CE_DEBUG_SEL_MASK,
800 	.d_CE0_BASE_ADDRESS = AR6320_CE0_BASE_ADDRESS,
801 	.d_CE1_BASE_ADDRESS = AR6320_CE1_BASE_ADDRESS,
802 
803 };
804 #endif
805 #endif
806