1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _AR6320V2DEF_H_ 20*5113495bSYour Name #define _AR6320V2DEF_H_ 21*5113495bSYour Name 22*5113495bSYour Name /* Base Addresses */ 23*5113495bSYour Name #define AR6320V2_RTC_SOC_BASE_ADDRESS 0x00000800 24*5113495bSYour Name #define AR6320V2_RTC_WMAC_BASE_ADDRESS 0x00001000 25*5113495bSYour Name #define AR6320V2_MAC_COEX_BASE_ADDRESS 0x0000f000 26*5113495bSYour Name #define AR6320V2_BT_COEX_BASE_ADDRESS 0x00002000 27*5113495bSYour Name #define AR6320V2_SOC_PCIE_BASE_ADDRESS 0x00038000 28*5113495bSYour Name #define AR6320V2_SOC_CORE_BASE_ADDRESS 0x0003a000 29*5113495bSYour Name #define AR6320V2_WLAN_UART_BASE_ADDRESS 0x0000c000 30*5113495bSYour Name #define AR6320V2_WLAN_SI_BASE_ADDRESS 0x00010000 31*5113495bSYour Name #define AR6320V2_WLAN_GPIO_BASE_ADDRESS 0x00005000 32*5113495bSYour Name #define AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS 0x00006000 33*5113495bSYour Name #define AR6320V2_WLAN_MAC_BASE_ADDRESS 0x00010000 34*5113495bSYour Name #define AR6320V2_EFUSE_BASE_ADDRESS 0x00024000 35*5113495bSYour Name #define AR6320V2_FPGA_REG_BASE_ADDRESS 0x00039000 36*5113495bSYour Name #define AR6320V2_WLAN_UART2_BASE_ADDRESS 0x00054c00 37*5113495bSYour Name #define AR6320V2_DBI_BASE_ADDRESS 0x0003c000 38*5113495bSYour Name 39*5113495bSYour Name #define AR6320V2_SCRATCH_3_ADDRESS 0x0028 40*5113495bSYour Name #define AR6320V2_TARG_DRAM_START 0x00400000 41*5113495bSYour Name #define AR6320V2_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0 42*5113495bSYour Name #define AR6320V2_SOC_RESET_CONTROL_OFFSET 0x00000000 43*5113495bSYour Name #define AR6320V2_SOC_CLOCK_CONTROL_OFFSET 0x00000028 44*5113495bSYour Name #define AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 45*5113495bSYour Name #define AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000000 46*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN0_ADDRESS 0x00000068 47*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN1_ADDRESS 0x0000006c 48*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 49*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 50*5113495bSYour Name #define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020 51*5113495bSYour Name #define AR6320V2_SOC_LPO_CAL_OFFSET 0x000000e0 52*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN10_ADDRESS 0x00000090 53*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN11_ADDRESS 0x00000094 54*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN12_ADDRESS 0x00000098 55*5113495bSYour Name #define AR6320V2_WLAN_GPIO_PIN13_ADDRESS 0x0000009c 56*5113495bSYour Name #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0 57*5113495bSYour Name #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 58*5113495bSYour Name #define AR6320V2_SOC_LPO_CAL_ENABLE_LSB 20 59*5113495bSYour Name #define AR6320V2_SOC_LPO_CAL_ENABLE_MASK 0x00100000 60*5113495bSYour Name 61*5113495bSYour Name #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 62*5113495bSYour Name #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 63*5113495bSYour Name #define AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 64*5113495bSYour Name #define AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 65*5113495bSYour Name #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB 18 66*5113495bSYour Name #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 67*5113495bSYour Name #define AR6320V2_SI_CONFIG_I2C_LSB 16 68*5113495bSYour Name #define AR6320V2_SI_CONFIG_I2C_MASK 0x00010000 69*5113495bSYour Name #define AR6320V2_SI_CONFIG_POS_SAMPLE_LSB 7 70*5113495bSYour Name #define AR6320V2_SI_CONFIG_POS_SAMPLE_MASK 0x00000080 71*5113495bSYour Name #define AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB 4 72*5113495bSYour Name #define AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 73*5113495bSYour Name #define AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB 5 74*5113495bSYour Name #define AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 75*5113495bSYour Name #define AR6320V2_SI_CONFIG_DIVIDER_LSB 0 76*5113495bSYour Name #define AR6320V2_SI_CONFIG_DIVIDER_MASK 0x0000000f 77*5113495bSYour Name #define AR6320V2_SI_CONFIG_OFFSET 0x00000000 78*5113495bSYour Name #define AR6320V2_SI_TX_DATA0_OFFSET 0x00000008 79*5113495bSYour Name #define AR6320V2_SI_TX_DATA1_OFFSET 0x0000000c 80*5113495bSYour Name #define AR6320V2_SI_RX_DATA0_OFFSET 0x00000010 81*5113495bSYour Name #define AR6320V2_SI_RX_DATA1_OFFSET 0x00000014 82*5113495bSYour Name #define AR6320V2_SI_CS_OFFSET 0x00000004 83*5113495bSYour Name #define AR6320V2_SI_CS_DONE_ERR_MASK 0x00000400 84*5113495bSYour Name #define AR6320V2_SI_CS_DONE_INT_MASK 0x00000200 85*5113495bSYour Name #define AR6320V2_SI_CS_START_LSB 8 86*5113495bSYour Name #define AR6320V2_SI_CS_START_MASK 0x00000100 87*5113495bSYour Name #define AR6320V2_SI_CS_RX_CNT_LSB 4 88*5113495bSYour Name #define AR6320V2_SI_CS_RX_CNT_MASK 0x000000f0 89*5113495bSYour Name #define AR6320V2_SI_CS_TX_CNT_LSB 0 90*5113495bSYour Name #define AR6320V2_SI_CS_TX_CNT_MASK 0x0000000f 91*5113495bSYour Name #define AR6320V2_CE_COUNT 8 92*5113495bSYour Name #define AR6320V2_SR_WR_INDEX_ADDRESS 0x003c 93*5113495bSYour Name #define AR6320V2_DST_WATERMARK_ADDRESS 0x0050 94*5113495bSYour Name #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB 14 95*5113495bSYour Name #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000 96*5113495bSYour Name #define AR6320V2_RX_MPDU_START_0_RETRY_LSB 14 97*5113495bSYour Name #define AR6320V2_RX_MPDU_START_0_RETRY_MASK 0x00004000 98*5113495bSYour Name #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB 16 99*5113495bSYour Name #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000 100*5113495bSYour Name #define AR6320V2_RX_MPDU_START_2_PN_47_32_LSB 0 101*5113495bSYour Name #define AR6320V2_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff 102*5113495bSYour Name #define AR6320V2_RX_MPDU_START_2_TID_LSB 28 103*5113495bSYour Name #define AR6320V2_RX_MPDU_START_2_TID_MASK 0xf0000000 104*5113495bSYour Name #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16 105*5113495bSYour Name #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000 106*5113495bSYour Name #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB 15 107*5113495bSYour Name #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000 108*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB 2 109*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004 110*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB 13 111*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000 112*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000 113*5113495bSYour Name #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16 114*5113495bSYour Name #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000 115*5113495bSYour Name #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB 0 116*5113495bSYour Name #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff 117*5113495bSYour Name 118*5113495bSYour Name #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 119*5113495bSYour Name #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB 8 120*5113495bSYour Name #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 121*5113495bSYour Name #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB 13 122*5113495bSYour Name #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000 123*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400 124*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000 125*5113495bSYour Name #define AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 126*5113495bSYour Name #define AR6320V2_DST_WR_INDEX_ADDRESS 0x0040 127*5113495bSYour Name #define AR6320V2_SRC_WATERMARK_ADDRESS 0x004c 128*5113495bSYour Name #define AR6320V2_SRC_WATERMARK_LOW_MASK 0xffff0000 129*5113495bSYour Name #define AR6320V2_SRC_WATERMARK_HIGH_MASK 0x0000ffff 130*5113495bSYour Name #define AR6320V2_DST_WATERMARK_LOW_MASK 0xffff0000 131*5113495bSYour Name #define AR6320V2_DST_WATERMARK_HIGH_MASK 0x0000ffff 132*5113495bSYour Name #define AR6320V2_CURRENT_SRRI_ADDRESS 0x0044 133*5113495bSYour Name #define AR6320V2_CURRENT_DRRI_ADDRESS 0x0048 134*5113495bSYour Name #define AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 135*5113495bSYour Name #define AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 136*5113495bSYour Name #define AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 137*5113495bSYour Name #define AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 138*5113495bSYour Name #define AR6320V2_HOST_IS_ADDRESS 0x0030 139*5113495bSYour Name #define AR6320V2_HOST_IS_COPY_COMPLETE_MASK 0x00000001 140*5113495bSYour Name #define AR6320V2_HOST_IE_ADDRESS 0x002c 141*5113495bSYour Name #define AR6320V2_HOST_IE_COPY_COMPLETE_MASK 0x00000001 142*5113495bSYour Name #define AR6320V2_SR_BA_ADDRESS 0x0000 143*5113495bSYour Name #define AR6320V2_SR_SIZE_ADDRESS 0x0004 144*5113495bSYour Name #define AR6320V2_DR_BA_ADDRESS 0x0008 145*5113495bSYour Name #define AR6320V2_DR_SIZE_ADDRESS 0x000c 146*5113495bSYour Name #define AR6320V2_MISC_IE_ADDRESS 0x0034 147*5113495bSYour Name #define AR6320V2_MISC_IS_AXI_ERR_MASK 0x00000400 148*5113495bSYour Name #define AR6320V2_MISC_IS_DST_ADDR_ERR_MASK 0x00000200 149*5113495bSYour Name #define AR6320V2_MISC_IS_SRC_LEN_ERR_MASK 0x00000100 150*5113495bSYour Name #define AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 151*5113495bSYour Name #define AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 152*5113495bSYour Name #define AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 153*5113495bSYour Name #define AR6320V2_SRC_WATERMARK_LOW_LSB 16 154*5113495bSYour Name #define AR6320V2_SRC_WATERMARK_HIGH_LSB 0 155*5113495bSYour Name #define AR6320V2_DST_WATERMARK_LOW_LSB 16 156*5113495bSYour Name #define AR6320V2_DST_WATERMARK_HIGH_LSB 0 157*5113495bSYour Name #define AR6320V2_SOC_GLOBAL_RESET_ADDRESS 0x0008 158*5113495bSYour Name #define AR6320V2_RTC_STATE_ADDRESS 0x0000 159*5113495bSYour Name #define AR6320V2_RTC_STATE_COLD_RESET_MASK 0x00002000 160*5113495bSYour Name #define AR6320V2_RTC_STATE_V_MASK 0x00000007 161*5113495bSYour Name #define AR6320V2_RTC_STATE_V_LSB 0 162*5113495bSYour Name #define AR6320V2_RTC_STATE_V_ON 3 163*5113495bSYour Name #define AR6320V2_FW_IND_EVENT_PENDING 1 164*5113495bSYour Name #define AR6320V2_FW_IND_INITIALIZED 2 165*5113495bSYour Name #define AR6320V2_CPU_INTR_ADDRESS 0x0010 166*5113495bSYour Name #define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 167*5113495bSYour Name #define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 168*5113495bSYour Name #define AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS 0x00000054 169*5113495bSYour Name #define AR6320V2_SOC_RESET_CONTROL_ADDRESS 0x00000000 170*5113495bSYour Name #define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 171*5113495bSYour Name #define AR6320V2_CORE_CTRL_ADDRESS 0x0000 172*5113495bSYour Name #define AR6320V2_CORE_CTRL_CPU_INTR_MASK 0x00002000 173*5113495bSYour Name #define AR6320V2_LOCAL_SCRATCH_OFFSET 0x000000c0 174*5113495bSYour Name #define AR6320V2_CLOCK_GPIO_OFFSET 0xffffffff 175*5113495bSYour Name #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 176*5113495bSYour Name #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 177*5113495bSYour Name #define AR6320V2_SOC_CHIP_ID_ADDRESS 0x000000f0 178*5113495bSYour Name #define AR6320V2_SOC_CHIP_ID_VERSION_MASK 0xfffc0000 179*5113495bSYour Name #define AR6320V2_SOC_CHIP_ID_VERSION_LSB 18 180*5113495bSYour Name #define AR6320V2_SOC_CHIP_ID_REVISION_MASK 0x00000f00 181*5113495bSYour Name #define AR6320V2_SOC_CHIP_ID_REVISION_LSB 8 182*5113495bSYour Name #if defined(HIF_SDIO) 183*5113495bSYour Name #define AR6320V2_FW_IND_HELPER 4 184*5113495bSYour Name #endif 185*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 186*5113495bSYour Name defined(HIF_IPCI) 187*5113495bSYour Name #define AR6320V2_CE_WRAPPER_BASE_ADDRESS 0x00034000 188*5113495bSYour Name #define AR6320V2_CE0_BASE_ADDRESS 0x00034400 189*5113495bSYour Name #define AR6320V2_CE1_BASE_ADDRESS 0x00034800 190*5113495bSYour Name #define AR6320V2_CE2_BASE_ADDRESS 0x00034c00 191*5113495bSYour Name #define AR6320V2_CE3_BASE_ADDRESS 0x00035000 192*5113495bSYour Name #define AR6320V2_CE4_BASE_ADDRESS 0x00035400 193*5113495bSYour Name #define AR6320V2_CE5_BASE_ADDRESS 0x00035800 194*5113495bSYour Name #define AR6320V2_CE6_BASE_ADDRESS 0x00035c00 195*5113495bSYour Name #define AR6320V2_CE7_BASE_ADDRESS 0x00036000 196*5113495bSYour Name #define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800 197*5113495bSYour Name #define AR6320V2_CE_CTRL1_ADDRESS 0x0010 198*5113495bSYour Name #define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 199*5113495bSYour Name #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 200*5113495bSYour Name #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00 201*5113495bSYour Name #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8 202*5113495bSYour Name #define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB 0 203*5113495bSYour Name #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 204*5113495bSYour Name #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 205*5113495bSYour Name #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 206*5113495bSYour Name #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 207*5113495bSYour Name #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020 208*5113495bSYour Name #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5 209*5113495bSYour Name #define AR6320V2_PCIE_SOC_WAKE_RESET 0x00000000 210*5113495bSYour Name #define AR6320V2_PCIE_SOC_WAKE_ADDRESS 0x0004 211*5113495bSYour Name #define AR6320V2_PCIE_SOC_WAKE_V_MASK 0x00000001 212*5113495bSYour Name #define AR6320V2_MUX_ID_MASK 0x0000 213*5113495bSYour Name #define AR6320V2_TRANSACTION_ID_MASK 0x3fff 214*5113495bSYour Name #define AR6320V2_PCIE_LOCAL_BASE_ADDRESS 0x80000 215*5113495bSYour Name #define AR6320V2_FW_IND_HELPER 4 216*5113495bSYour Name #define AR6320V2_PCIE_INTR_ENABLE_ADDRESS 0x0008 217*5113495bSYour Name #define AR6320V2_PCIE_INTR_CLR_ADDRESS 0x0014 218*5113495bSYour Name #define AR6320V2_PCIE_INTR_FIRMWARE_MASK 0x00000400 219*5113495bSYour Name #define AR6320V2_PCIE_INTR_CE0_MASK 0x00000800 220*5113495bSYour Name #define AR6320V2_PCIE_INTR_CE_MASK_ALL 0x0007f800 221*5113495bSYour Name #define AR6320V2_PCIE_INTR_CAUSE_ADDRESS 0x000c 222*5113495bSYour Name #define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001 223*5113495bSYour Name #define AR6320V2_SOC_POWER_REG_OFFSET 0x0000010c 224*5113495bSYour Name /* Copy Engine Debug */ 225*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c 226*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 227*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 228*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f 229*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_CONTROL_OFFSET 0x00000108 230*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB 0 231*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB 0 232*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 233*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_OUT_OFFSET 0x00000110 234*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_OUT_DATA_MSB 19 235*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_OUT_DATA_LSB 0 236*5113495bSYour Name #define AR6320V2_WLAN_DEBUG_OUT_DATA_MASK 0x000fffff 237*5113495bSYour Name #define AR6320V2_AMBA_DEBUG_BUS_OFFSET 0x0000011c 238*5113495bSYour Name #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB 13 239*5113495bSYour Name #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB 8 240*5113495bSYour Name #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK 0x00003f00 241*5113495bSYour Name #define AR6320V2_AMBA_DEBUG_BUS_SEL_MSB 4 242*5113495bSYour Name #define AR6320V2_AMBA_DEBUG_BUS_SEL_LSB 0 243*5113495bSYour Name #define AR6320V2_AMBA_DEBUG_BUS_SEL_MASK 0x0000001f 244*5113495bSYour Name #define AR6320V2_CE_WRAPPER_DEBUG_OFFSET 0x0008 245*5113495bSYour Name #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB 5 246*5113495bSYour Name #define AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB 0 247*5113495bSYour Name #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK 0x0000003f 248*5113495bSYour Name #define AR6320V2_CE_DEBUG_OFFSET 0x0054 249*5113495bSYour Name #define AR6320V2_CE_DEBUG_SEL_MSB 5 250*5113495bSYour Name #define AR6320V2_CE_DEBUG_SEL_LSB 0 251*5113495bSYour Name #define AR6320V2_CE_DEBUG_SEL_MASK 0x0000003f 252*5113495bSYour Name /* End */ 253*5113495bSYour Name 254*5113495bSYour Name /* PLL start */ 255*5113495bSYour Name #define AR6320V2_EFUSE_OFFSET 0x0000032c 256*5113495bSYour Name #define AR6320V2_EFUSE_XTAL_SEL_MSB 10 257*5113495bSYour Name #define AR6320V2_EFUSE_XTAL_SEL_LSB 8 258*5113495bSYour Name #define AR6320V2_EFUSE_XTAL_SEL_MASK 0x00000700 259*5113495bSYour Name #define AR6320V2_BB_PLL_CONFIG_OFFSET 0x000002f4 260*5113495bSYour Name #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB 20 261*5113495bSYour Name #define AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB 18 262*5113495bSYour Name #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 263*5113495bSYour Name #define AR6320V2_BB_PLL_CONFIG_FRAC_MSB 17 264*5113495bSYour Name #define AR6320V2_BB_PLL_CONFIG_FRAC_LSB 0 265*5113495bSYour Name #define AR6320V2_BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 266*5113495bSYour Name #define AR6320V2_WLAN_PLL_SETTLE_TIME_MSB 10 267*5113495bSYour Name #define AR6320V2_WLAN_PLL_SETTLE_TIME_LSB 0 268*5113495bSYour Name #define AR6320V2_WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 269*5113495bSYour Name #define AR6320V2_WLAN_PLL_SETTLE_OFFSET 0x0018 270*5113495bSYour Name #define AR6320V2_WLAN_PLL_SETTLE_SW_MASK 0x000007ff 271*5113495bSYour Name #define AR6320V2_WLAN_PLL_SETTLE_RSTMASK 0xffffffff 272*5113495bSYour Name #define AR6320V2_WLAN_PLL_SETTLE_RESET 0x00000400 273*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB 18 274*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB 18 275*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 276*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB 16 277*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB 16 278*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 279*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET 0x1 280*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB 15 281*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB 14 282*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK 0x0000c000 283*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET 0x0 284*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB 13 285*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB 10 286*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 287*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET 0x0 288*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_DIV_MSB 9 289*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_DIV_LSB 0 290*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 291*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_DIV_RESET 0x11 292*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_OFFSET 0x0014 293*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_SW_MASK 0x001fffff 294*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_RSTMASK 0xffffffff 295*5113495bSYour Name #define AR6320V2_WLAN_PLL_CONTROL_RESET 0x00010011 296*5113495bSYour Name #define AR6320V2_SOC_CORE_CLK_CTRL_OFFSET 0x00000114 297*5113495bSYour Name #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB 2 298*5113495bSYour Name #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB 0 299*5113495bSYour Name #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 300*5113495bSYour Name #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB 5 301*5113495bSYour Name #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 302*5113495bSYour Name #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 303*5113495bSYour Name #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET 0x0 304*5113495bSYour Name #define AR6320V2_RTC_SYNC_STATUS_OFFSET 0x0244 305*5113495bSYour Name #define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020 306*5113495bSYour Name #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB 1 307*5113495bSYour Name #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0 308*5113495bSYour Name #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 309*5113495bSYour Name /* PLL end */ 310*5113495bSYour Name 311*5113495bSYour Name #define AR6320V2_PCIE_INTR_CE_MASK(n) \ 312*5113495bSYour Name (AR6320V2_PCIE_INTR_CE0_MASK << (n)) 313*5113495bSYour Name #endif 314*5113495bSYour Name #define AR6320V2_DRAM_BASE_ADDRESS AR6320V2_TARG_DRAM_START 315*5113495bSYour Name #define AR6320V2_FW_INDICATOR_ADDRESS \ 316*5113495bSYour Name (AR6320V2_SOC_CORE_BASE_ADDRESS + AR6320V2_SCRATCH_3_ADDRESS) 317*5113495bSYour Name #define AR6320V2_SYSTEM_SLEEP_OFFSET AR6320V2_SOC_SYSTEM_SLEEP_OFFSET 318*5113495bSYour Name #define AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET 0x002c 319*5113495bSYour Name #define AR6320V2_WLAN_RESET_CONTROL_OFFSET AR6320V2_SOC_RESET_CONTROL_OFFSET 320*5113495bSYour Name #define AR6320V2_CLOCK_CONTROL_OFFSET AR6320V2_SOC_CLOCK_CONTROL_OFFSET 321*5113495bSYour Name #define AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK \ 322*5113495bSYour Name AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK 323*5113495bSYour Name #define AR6320V2_RESET_CONTROL_MBOX_RST_MASK 0x00000004 324*5113495bSYour Name #define AR6320V2_RESET_CONTROL_SI0_RST_MASK \ 325*5113495bSYour Name AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK 326*5113495bSYour Name #define AR6320V2_GPIO_BASE_ADDRESS AR6320V2_WLAN_GPIO_BASE_ADDRESS 327*5113495bSYour Name #define AR6320V2_GPIO_PIN0_OFFSET AR6320V2_WLAN_GPIO_PIN0_ADDRESS 328*5113495bSYour Name #define AR6320V2_GPIO_PIN1_OFFSET AR6320V2_WLAN_GPIO_PIN1_ADDRESS 329*5113495bSYour Name #define AR6320V2_GPIO_PIN0_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK 330*5113495bSYour Name #define AR6320V2_GPIO_PIN1_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK 331*5113495bSYour Name #define AR6320V2_SI_BASE_ADDRESS 0x00050000 332*5113495bSYour Name #define AR6320V2_CPU_CLOCK_OFFSET AR6320V2_SOC_CPU_CLOCK_OFFSET 333*5113495bSYour Name #define AR6320V2_LPO_CAL_OFFSET AR6320V2_SOC_LPO_CAL_OFFSET 334*5113495bSYour Name #define AR6320V2_GPIO_PIN10_OFFSET AR6320V2_WLAN_GPIO_PIN10_ADDRESS 335*5113495bSYour Name #define AR6320V2_GPIO_PIN11_OFFSET AR6320V2_WLAN_GPIO_PIN11_ADDRESS 336*5113495bSYour Name #define AR6320V2_GPIO_PIN12_OFFSET AR6320V2_WLAN_GPIO_PIN12_ADDRESS 337*5113495bSYour Name #define AR6320V2_GPIO_PIN13_OFFSET AR6320V2_WLAN_GPIO_PIN13_ADDRESS 338*5113495bSYour Name #define AR6320V2_CPU_CLOCK_STANDARD_LSB AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 339*5113495bSYour Name #define AR6320V2_CPU_CLOCK_STANDARD_MASK AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 340*5113495bSYour Name #define AR6320V2_LPO_CAL_ENABLE_LSB AR6320V2_SOC_LPO_CAL_ENABLE_LSB 341*5113495bSYour Name #define AR6320V2_LPO_CAL_ENABLE_MASK AR6320V2_SOC_LPO_CAL_ENABLE_MASK 342*5113495bSYour Name #define AR6320V2_ANALOG_INTF_BASE_ADDRESS \ 343*5113495bSYour Name AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS 344*5113495bSYour Name #define AR6320V2_MBOX_BASE_ADDRESS 0x00008000 345*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_ERROR_LSB 7 346*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 347*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_CPU_LSB 6 348*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_CPU_MASK 0x00000040 349*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB 4 350*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 351*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 352*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 353*5113495bSYour Name #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 17 354*5113495bSYour Name #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00020000 355*5113495bSYour Name #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 16 356*5113495bSYour Name #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00010000 357*5113495bSYour Name #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB 24 358*5113495bSYour Name #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0xff000000 359*5113495bSYour Name #define AR6320V2_INT_STATUS_ENABLE_ADDRESS 0x0828 360*5113495bSYour Name #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB 8 361*5113495bSYour Name #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK 0x0000ff00 362*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_ADDRESS 0x0800 363*5113495bSYour Name #define AR6320V2_CPU_INT_STATUS_ADDRESS 0x0801 364*5113495bSYour Name #define AR6320V2_ERROR_INT_STATUS_ADDRESS 0x0802 365*5113495bSYour Name #define AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK 0x00040000 366*5113495bSYour Name #define AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB 18 367*5113495bSYour Name #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00020000 368*5113495bSYour Name #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 17 369*5113495bSYour Name #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00010000 370*5113495bSYour Name #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB 16 371*5113495bSYour Name #define AR6320V2_COUNT_DEC_ADDRESS 0x0840 372*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_CPU_MASK 0x00000040 373*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_CPU_LSB 6 374*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_ERROR_MASK 0x00000080 375*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_ERROR_LSB 7 376*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_COUNTER_MASK 0x00000010 377*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_COUNTER_LSB 4 378*5113495bSYour Name #define AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS 0x0805 379*5113495bSYour Name #define AR6320V2_WINDOW_DATA_ADDRESS 0x0874 380*5113495bSYour Name #define AR6320V2_WINDOW_READ_ADDR_ADDRESS 0x087c 381*5113495bSYour Name #define AR6320V2_WINDOW_WRITE_ADDR_ADDRESS 0x0878 382*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f 383*5113495bSYour Name #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB 0 384*5113495bSYour Name 385*5113495bSYour Name struct targetdef_s ar6320v2_targetdef = { 386*5113495bSYour Name .d_RTC_SOC_BASE_ADDRESS = AR6320V2_RTC_SOC_BASE_ADDRESS, 387*5113495bSYour Name .d_RTC_WMAC_BASE_ADDRESS = AR6320V2_RTC_WMAC_BASE_ADDRESS, 388*5113495bSYour Name .d_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET, 389*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET, 390*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = 391*5113495bSYour Name AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB, 392*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = 393*5113495bSYour Name AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK, 394*5113495bSYour Name .d_CLOCK_CONTROL_OFFSET = AR6320V2_CLOCK_CONTROL_OFFSET, 395*5113495bSYour Name .d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK, 396*5113495bSYour Name .d_RESET_CONTROL_OFFSET = AR6320V2_SOC_RESET_CONTROL_OFFSET, 397*5113495bSYour Name .d_RESET_CONTROL_MBOX_RST_MASK = AR6320V2_RESET_CONTROL_MBOX_RST_MASK, 398*5113495bSYour Name .d_RESET_CONTROL_SI0_RST_MASK = AR6320V2_RESET_CONTROL_SI0_RST_MASK, 399*5113495bSYour Name .d_WLAN_RESET_CONTROL_OFFSET = AR6320V2_WLAN_RESET_CONTROL_OFFSET, 400*5113495bSYour Name .d_WLAN_RESET_CONTROL_COLD_RST_MASK = 401*5113495bSYour Name AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK, 402*5113495bSYour Name .d_WLAN_RESET_CONTROL_WARM_RST_MASK = 403*5113495bSYour Name AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK, 404*5113495bSYour Name .d_GPIO_BASE_ADDRESS = AR6320V2_GPIO_BASE_ADDRESS, 405*5113495bSYour Name .d_GPIO_PIN0_OFFSET = AR6320V2_GPIO_PIN0_OFFSET, 406*5113495bSYour Name .d_GPIO_PIN1_OFFSET = AR6320V2_GPIO_PIN1_OFFSET, 407*5113495bSYour Name .d_GPIO_PIN0_CONFIG_MASK = AR6320V2_GPIO_PIN0_CONFIG_MASK, 408*5113495bSYour Name .d_GPIO_PIN1_CONFIG_MASK = AR6320V2_GPIO_PIN1_CONFIG_MASK, 409*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB, 410*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_MASK = 411*5113495bSYour Name AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK, 412*5113495bSYour Name .d_SI_CONFIG_I2C_LSB = AR6320V2_SI_CONFIG_I2C_LSB, 413*5113495bSYour Name .d_SI_CONFIG_I2C_MASK = AR6320V2_SI_CONFIG_I2C_MASK, 414*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_LSB = AR6320V2_SI_CONFIG_POS_SAMPLE_LSB, 415*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_MASK = AR6320V2_SI_CONFIG_POS_SAMPLE_MASK, 416*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB, 417*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK, 418*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB, 419*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_MASK = 420*5113495bSYour Name AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK, 421*5113495bSYour Name .d_SI_CONFIG_DIVIDER_LSB = AR6320V2_SI_CONFIG_DIVIDER_LSB, 422*5113495bSYour Name .d_SI_CONFIG_DIVIDER_MASK = AR6320V2_SI_CONFIG_DIVIDER_MASK, 423*5113495bSYour Name .d_SI_BASE_ADDRESS = AR6320V2_SI_BASE_ADDRESS, 424*5113495bSYour Name .d_SI_CONFIG_OFFSET = AR6320V2_SI_CONFIG_OFFSET, 425*5113495bSYour Name .d_SI_TX_DATA0_OFFSET = AR6320V2_SI_TX_DATA0_OFFSET, 426*5113495bSYour Name .d_SI_TX_DATA1_OFFSET = AR6320V2_SI_TX_DATA1_OFFSET, 427*5113495bSYour Name .d_SI_RX_DATA0_OFFSET = AR6320V2_SI_RX_DATA0_OFFSET, 428*5113495bSYour Name .d_SI_RX_DATA1_OFFSET = AR6320V2_SI_RX_DATA1_OFFSET, 429*5113495bSYour Name .d_SI_CS_OFFSET = AR6320V2_SI_CS_OFFSET, 430*5113495bSYour Name .d_SI_CS_DONE_ERR_MASK = AR6320V2_SI_CS_DONE_ERR_MASK, 431*5113495bSYour Name .d_SI_CS_DONE_INT_MASK = AR6320V2_SI_CS_DONE_INT_MASK, 432*5113495bSYour Name .d_SI_CS_START_LSB = AR6320V2_SI_CS_START_LSB, 433*5113495bSYour Name .d_SI_CS_START_MASK = AR6320V2_SI_CS_START_MASK, 434*5113495bSYour Name .d_SI_CS_RX_CNT_LSB = AR6320V2_SI_CS_RX_CNT_LSB, 435*5113495bSYour Name .d_SI_CS_RX_CNT_MASK = AR6320V2_SI_CS_RX_CNT_MASK, 436*5113495bSYour Name .d_SI_CS_TX_CNT_LSB = AR6320V2_SI_CS_TX_CNT_LSB, 437*5113495bSYour Name .d_SI_CS_TX_CNT_MASK = AR6320V2_SI_CS_TX_CNT_MASK, 438*5113495bSYour Name .d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ, 439*5113495bSYour Name .d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ, 440*5113495bSYour Name .d_MBOX_BASE_ADDRESS = AR6320V2_MBOX_BASE_ADDRESS, 441*5113495bSYour Name .d_LOCAL_SCRATCH_OFFSET = AR6320V2_LOCAL_SCRATCH_OFFSET, 442*5113495bSYour Name .d_CPU_CLOCK_OFFSET = AR6320V2_CPU_CLOCK_OFFSET, 443*5113495bSYour Name .d_LPO_CAL_OFFSET = AR6320V2_LPO_CAL_OFFSET, 444*5113495bSYour Name .d_GPIO_PIN10_OFFSET = AR6320V2_GPIO_PIN10_OFFSET, 445*5113495bSYour Name .d_GPIO_PIN11_OFFSET = AR6320V2_GPIO_PIN11_OFFSET, 446*5113495bSYour Name .d_GPIO_PIN12_OFFSET = AR6320V2_GPIO_PIN12_OFFSET, 447*5113495bSYour Name .d_GPIO_PIN13_OFFSET = AR6320V2_GPIO_PIN13_OFFSET, 448*5113495bSYour Name .d_CLOCK_GPIO_OFFSET = AR6320V2_CLOCK_GPIO_OFFSET, 449*5113495bSYour Name .d_CPU_CLOCK_STANDARD_LSB = AR6320V2_CPU_CLOCK_STANDARD_LSB, 450*5113495bSYour Name .d_CPU_CLOCK_STANDARD_MASK = AR6320V2_CPU_CLOCK_STANDARD_MASK, 451*5113495bSYour Name .d_LPO_CAL_ENABLE_LSB = AR6320V2_LPO_CAL_ENABLE_LSB, 452*5113495bSYour Name .d_LPO_CAL_ENABLE_MASK = AR6320V2_LPO_CAL_ENABLE_MASK, 453*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = 454*5113495bSYour Name AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB, 455*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = 456*5113495bSYour Name AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK, 457*5113495bSYour Name .d_ANALOG_INTF_BASE_ADDRESS = AR6320V2_ANALOG_INTF_BASE_ADDRESS, 458*5113495bSYour Name .d_WLAN_MAC_BASE_ADDRESS = AR6320V2_WLAN_MAC_BASE_ADDRESS, 459*5113495bSYour Name .d_FW_INDICATOR_ADDRESS = AR6320V2_FW_INDICATOR_ADDRESS, 460*5113495bSYour Name .d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS, 461*5113495bSYour Name .d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS, 462*5113495bSYour Name .d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS, 463*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 464*5113495bSYour Name defined(HIF_IPCI) 465*5113495bSYour Name .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, 466*5113495bSYour Name .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, 467*5113495bSYour Name #endif 468*5113495bSYour Name .d_CORE_CTRL_CPU_INTR_MASK = AR6320V2_CORE_CTRL_CPU_INTR_MASK, 469*5113495bSYour Name .d_SR_WR_INDEX_ADDRESS = AR6320V2_SR_WR_INDEX_ADDRESS, 470*5113495bSYour Name .d_DST_WATERMARK_ADDRESS = AR6320V2_DST_WATERMARK_ADDRESS, 471*5113495bSYour Name /* htt_rx.c */ 472*5113495bSYour Name .d_RX_MSDU_END_4_FIRST_MSDU_MASK = 473*5113495bSYour Name AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK, 474*5113495bSYour Name .d_RX_MSDU_END_4_FIRST_MSDU_LSB = 475*5113495bSYour Name AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB, 476*5113495bSYour Name .d_RX_MPDU_START_0_RETRY_MASK = 477*5113495bSYour Name AR6320V2_RX_MPDU_START_0_RETRY_MASK, 478*5113495bSYour Name .d_RX_MPDU_START_0_SEQ_NUM_MASK = 479*5113495bSYour Name AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK, 480*5113495bSYour Name .d_RX_MPDU_START_0_SEQ_NUM_MASK = 481*5113495bSYour Name AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK, 482*5113495bSYour Name .d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB, 483*5113495bSYour Name .d_RX_MPDU_START_2_PN_47_32_LSB = 484*5113495bSYour Name AR6320V2_RX_MPDU_START_2_PN_47_32_LSB, 485*5113495bSYour Name .d_RX_MPDU_START_2_PN_47_32_MASK = 486*5113495bSYour Name AR6320V2_RX_MPDU_START_2_PN_47_32_MASK, 487*5113495bSYour Name .d_RX_MPDU_START_2_TID_LSB = 488*5113495bSYour Name AR6320V2_RX_MPDU_START_2_TID_LSB, 489*5113495bSYour Name .d_RX_MPDU_START_2_TID_MASK = 490*5113495bSYour Name AR6320V2_RX_MPDU_START_2_TID_MASK, 491*5113495bSYour Name .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK = 492*5113495bSYour Name AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK, 493*5113495bSYour Name .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB = 494*5113495bSYour Name AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB, 495*5113495bSYour Name .d_RX_MSDU_END_4_LAST_MSDU_MASK = 496*5113495bSYour Name AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK, 497*5113495bSYour Name .d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB, 498*5113495bSYour Name .d_RX_ATTENTION_0_MCAST_BCAST_MASK = 499*5113495bSYour Name AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK, 500*5113495bSYour Name .d_RX_ATTENTION_0_MCAST_BCAST_LSB = 501*5113495bSYour Name AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB, 502*5113495bSYour Name .d_RX_ATTENTION_0_FRAGMENT_MASK = 503*5113495bSYour Name AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK, 504*5113495bSYour Name .d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB, 505*5113495bSYour Name .d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK = 506*5113495bSYour Name AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK, 507*5113495bSYour Name .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK = 508*5113495bSYour Name AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK, 509*5113495bSYour Name .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB = 510*5113495bSYour Name AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB, 511*5113495bSYour Name .d_RX_MSDU_START_0_MSDU_LENGTH_MASK = 512*5113495bSYour Name AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK, 513*5113495bSYour Name .d_RX_MSDU_START_0_MSDU_LENGTH_LSB = 514*5113495bSYour Name AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB, 515*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET = 516*5113495bSYour Name AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET, 517*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_MASK = 518*5113495bSYour Name AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK, 519*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_LSB = 520*5113495bSYour Name AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB, 521*5113495bSYour Name .d_RX_MPDU_START_0_ENCRYPTED_MASK = 522*5113495bSYour Name AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK, 523*5113495bSYour Name .d_RX_MPDU_START_0_ENCRYPTED_LSB = 524*5113495bSYour Name AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB, 525*5113495bSYour Name .d_RX_ATTENTION_0_MORE_DATA_MASK = 526*5113495bSYour Name AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK, 527*5113495bSYour Name .d_RX_ATTENTION_0_MSDU_DONE_MASK = 528*5113495bSYour Name AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK, 529*5113495bSYour Name .d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK = 530*5113495bSYour Name AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK, 531*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 532*5113495bSYour Name defined(HIF_IPCI) 533*5113495bSYour Name .d_CE_COUNT = AR6320V2_CE_COUNT, 534*5113495bSYour Name .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, 535*5113495bSYour Name .d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS, 536*5113495bSYour Name .d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS, 537*5113495bSYour Name .d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK, 538*5113495bSYour Name .d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL, 539*5113495bSYour Name /* PLL start */ 540*5113495bSYour Name .d_EFUSE_OFFSET = AR6320V2_EFUSE_OFFSET, 541*5113495bSYour Name .d_EFUSE_XTAL_SEL_MSB = AR6320V2_EFUSE_XTAL_SEL_MSB, 542*5113495bSYour Name .d_EFUSE_XTAL_SEL_LSB = AR6320V2_EFUSE_XTAL_SEL_LSB, 543*5113495bSYour Name .d_EFUSE_XTAL_SEL_MASK = AR6320V2_EFUSE_XTAL_SEL_MASK, 544*5113495bSYour Name .d_BB_PLL_CONFIG_OFFSET = AR6320V2_BB_PLL_CONFIG_OFFSET, 545*5113495bSYour Name .d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB, 546*5113495bSYour Name .d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB, 547*5113495bSYour Name .d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK, 548*5113495bSYour Name .d_BB_PLL_CONFIG_FRAC_MSB = AR6320V2_BB_PLL_CONFIG_FRAC_MSB, 549*5113495bSYour Name .d_BB_PLL_CONFIG_FRAC_LSB = AR6320V2_BB_PLL_CONFIG_FRAC_LSB, 550*5113495bSYour Name .d_BB_PLL_CONFIG_FRAC_MASK = AR6320V2_BB_PLL_CONFIG_FRAC_MASK, 551*5113495bSYour Name .d_WLAN_PLL_SETTLE_TIME_MSB = AR6320V2_WLAN_PLL_SETTLE_TIME_MSB, 552*5113495bSYour Name .d_WLAN_PLL_SETTLE_TIME_LSB = AR6320V2_WLAN_PLL_SETTLE_TIME_LSB, 553*5113495bSYour Name .d_WLAN_PLL_SETTLE_TIME_MASK = AR6320V2_WLAN_PLL_SETTLE_TIME_MASK, 554*5113495bSYour Name .d_WLAN_PLL_SETTLE_OFFSET = AR6320V2_WLAN_PLL_SETTLE_OFFSET, 555*5113495bSYour Name .d_WLAN_PLL_SETTLE_SW_MASK = AR6320V2_WLAN_PLL_SETTLE_SW_MASK, 556*5113495bSYour Name .d_WLAN_PLL_SETTLE_RSTMASK = AR6320V2_WLAN_PLL_SETTLE_RSTMASK, 557*5113495bSYour Name .d_WLAN_PLL_SETTLE_RESET = AR6320V2_WLAN_PLL_SETTLE_RESET, 558*5113495bSYour Name .d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB, 559*5113495bSYour Name .d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB, 560*5113495bSYour Name .d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK, 561*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB, 562*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB, 563*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_MASK = 564*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK, 565*5113495bSYour Name .d_WLAN_PLL_CONTROL_BYPASS_RESET = 566*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET, 567*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_MSB = 568*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB, 569*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_LSB = 570*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB, 571*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_MASK = 572*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK, 573*5113495bSYour Name .d_WLAN_PLL_CONTROL_CLK_SEL_RESET = 574*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET, 575*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB, 576*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB, 577*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_MASK = 578*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK, 579*5113495bSYour Name .d_WLAN_PLL_CONTROL_REFDIV_RESET = 580*5113495bSYour Name AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET, 581*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_MSB = AR6320V2_WLAN_PLL_CONTROL_DIV_MSB, 582*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_LSB = AR6320V2_WLAN_PLL_CONTROL_DIV_LSB, 583*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_MASK = AR6320V2_WLAN_PLL_CONTROL_DIV_MASK, 584*5113495bSYour Name .d_WLAN_PLL_CONTROL_DIV_RESET = AR6320V2_WLAN_PLL_CONTROL_DIV_RESET, 585*5113495bSYour Name .d_WLAN_PLL_CONTROL_OFFSET = AR6320V2_WLAN_PLL_CONTROL_OFFSET, 586*5113495bSYour Name .d_WLAN_PLL_CONTROL_SW_MASK = AR6320V2_WLAN_PLL_CONTROL_SW_MASK, 587*5113495bSYour Name .d_WLAN_PLL_CONTROL_RSTMASK = AR6320V2_WLAN_PLL_CONTROL_RSTMASK, 588*5113495bSYour Name .d_WLAN_PLL_CONTROL_RESET = AR6320V2_WLAN_PLL_CONTROL_RESET, 589*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_OFFSET = AR6320V2_SOC_CORE_CLK_CTRL_OFFSET, 590*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB, 591*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB, 592*5113495bSYour Name .d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK, 593*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_MSB = 594*5113495bSYour Name AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB, 595*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_LSB = 596*5113495bSYour Name AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB, 597*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_MASK = 598*5113495bSYour Name AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK, 599*5113495bSYour Name .d_RTC_SYNC_STATUS_PLL_CHANGING_RESET = 600*5113495bSYour Name AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET, 601*5113495bSYour Name .d_RTC_SYNC_STATUS_OFFSET = AR6320V2_RTC_SYNC_STATUS_OFFSET, 602*5113495bSYour Name .d_SOC_CPU_CLOCK_OFFSET = AR6320V2_SOC_CPU_CLOCK_OFFSET, 603*5113495bSYour Name .d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB, 604*5113495bSYour Name .d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB, 605*5113495bSYour Name .d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK, 606*5113495bSYour Name /* PLL end */ 607*5113495bSYour Name .d_SOC_POWER_REG_OFFSET = AR6320V2_SOC_POWER_REG_OFFSET, 608*5113495bSYour Name .d_PCIE_INTR_CAUSE_ADDRESS = AR6320V2_PCIE_INTR_CAUSE_ADDRESS, 609*5113495bSYour Name .d_SOC_RESET_CONTROL_ADDRESS = AR6320V2_SOC_RESET_CONTROL_ADDRESS, 610*5113495bSYour Name .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = 611*5113495bSYour Name AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK, 612*5113495bSYour Name .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB = 613*5113495bSYour Name AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB, 614*5113495bSYour Name .d_SOC_RESET_CONTROL_CE_RST_MASK = 615*5113495bSYour Name AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK, 616*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET, 617*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = 618*5113495bSYour Name AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB, 619*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = 620*5113495bSYour Name AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB, 621*5113495bSYour Name .d_WLAN_DEBUG_INPUT_SEL_SRC_MASK = 622*5113495bSYour Name AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK, 623*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_OFFSET = AR6320V2_WLAN_DEBUG_CONTROL_OFFSET, 624*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_ENABLE_MSB = 625*5113495bSYour Name AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB, 626*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_ENABLE_LSB = 627*5113495bSYour Name AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB, 628*5113495bSYour Name .d_WLAN_DEBUG_CONTROL_ENABLE_MASK = 629*5113495bSYour Name AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK, 630*5113495bSYour Name .d_WLAN_DEBUG_OUT_OFFSET = AR6320V2_WLAN_DEBUG_OUT_OFFSET, 631*5113495bSYour Name .d_WLAN_DEBUG_OUT_DATA_MSB = AR6320V2_WLAN_DEBUG_OUT_DATA_MSB, 632*5113495bSYour Name .d_WLAN_DEBUG_OUT_DATA_LSB = AR6320V2_WLAN_DEBUG_OUT_DATA_LSB, 633*5113495bSYour Name .d_WLAN_DEBUG_OUT_DATA_MASK = AR6320V2_WLAN_DEBUG_OUT_DATA_MASK, 634*5113495bSYour Name .d_AMBA_DEBUG_BUS_OFFSET = AR6320V2_AMBA_DEBUG_BUS_OFFSET, 635*5113495bSYour Name .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB = 636*5113495bSYour Name AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB, 637*5113495bSYour Name .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB = 638*5113495bSYour Name AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB, 639*5113495bSYour Name .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK = 640*5113495bSYour Name AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK, 641*5113495bSYour Name .d_AMBA_DEBUG_BUS_SEL_MSB = AR6320V2_AMBA_DEBUG_BUS_SEL_MSB, 642*5113495bSYour Name .d_AMBA_DEBUG_BUS_SEL_LSB = AR6320V2_AMBA_DEBUG_BUS_SEL_LSB, 643*5113495bSYour Name .d_AMBA_DEBUG_BUS_SEL_MASK = AR6320V2_AMBA_DEBUG_BUS_SEL_MASK, 644*5113495bSYour Name #endif 645*5113495bSYour Name .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK = 646*5113495bSYour Name AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK, 647*5113495bSYour Name .d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS, 648*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ADDRESS = 649*5113495bSYour Name AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS, 650*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK = 651*5113495bSYour Name AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK, 652*5113495bSYour Name .d_SOC_LF_TIMER_STATUS0_ADDRESS = 653*5113495bSYour Name AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS, 654*5113495bSYour Name /* chip id start */ 655*5113495bSYour Name .d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS, 656*5113495bSYour Name .d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK, 657*5113495bSYour Name .d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB, 658*5113495bSYour Name .d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK, 659*5113495bSYour Name .d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB, 660*5113495bSYour Name /* chip id end */ 661*5113495bSYour Name }; 662*5113495bSYour Name 663*5113495bSYour Name struct hostdef_s ar6320v2_hostdef = { 664*5113495bSYour Name .d_INT_STATUS_ENABLE_ERROR_LSB = AR6320V2_INT_STATUS_ENABLE_ERROR_LSB, 665*5113495bSYour Name .d_INT_STATUS_ENABLE_ERROR_MASK = 666*5113495bSYour Name AR6320V2_INT_STATUS_ENABLE_ERROR_MASK, 667*5113495bSYour Name .d_INT_STATUS_ENABLE_CPU_LSB = AR6320V2_INT_STATUS_ENABLE_CPU_LSB, 668*5113495bSYour Name .d_INT_STATUS_ENABLE_CPU_MASK = AR6320V2_INT_STATUS_ENABLE_CPU_MASK, 669*5113495bSYour Name .d_INT_STATUS_ENABLE_COUNTER_LSB = 670*5113495bSYour Name AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB, 671*5113495bSYour Name .d_INT_STATUS_ENABLE_COUNTER_MASK = 672*5113495bSYour Name AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK, 673*5113495bSYour Name .d_INT_STATUS_ENABLE_MBOX_DATA_LSB = 674*5113495bSYour Name AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB, 675*5113495bSYour Name .d_INT_STATUS_ENABLE_MBOX_DATA_MASK = 676*5113495bSYour Name AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK, 677*5113495bSYour Name .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB = 678*5113495bSYour Name AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB, 679*5113495bSYour Name .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK = 680*5113495bSYour Name AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 681*5113495bSYour Name .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB = 682*5113495bSYour Name AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB, 683*5113495bSYour Name .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK = 684*5113495bSYour Name AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 685*5113495bSYour Name .d_COUNTER_INT_STATUS_ENABLE_BIT_LSB = 686*5113495bSYour Name AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB, 687*5113495bSYour Name .d_COUNTER_INT_STATUS_ENABLE_BIT_MASK = 688*5113495bSYour Name AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK, 689*5113495bSYour Name .d_INT_STATUS_ENABLE_ADDRESS = AR6320V2_INT_STATUS_ENABLE_ADDRESS, 690*5113495bSYour Name .d_CPU_INT_STATUS_ENABLE_BIT_LSB = 691*5113495bSYour Name AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB, 692*5113495bSYour Name .d_CPU_INT_STATUS_ENABLE_BIT_MASK = 693*5113495bSYour Name AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK, 694*5113495bSYour Name .d_HOST_INT_STATUS_ADDRESS = AR6320V2_HOST_INT_STATUS_ADDRESS, 695*5113495bSYour Name .d_CPU_INT_STATUS_ADDRESS = AR6320V2_CPU_INT_STATUS_ADDRESS, 696*5113495bSYour Name .d_ERROR_INT_STATUS_ADDRESS = AR6320V2_ERROR_INT_STATUS_ADDRESS, 697*5113495bSYour Name .d_ERROR_INT_STATUS_WAKEUP_MASK = 698*5113495bSYour Name AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK, 699*5113495bSYour Name .d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB, 700*5113495bSYour Name .d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK = 701*5113495bSYour Name AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK, 702*5113495bSYour Name .d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB = 703*5113495bSYour Name AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB, 704*5113495bSYour Name .d_ERROR_INT_STATUS_TX_OVERFLOW_MASK = 705*5113495bSYour Name AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK, 706*5113495bSYour Name .d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = 707*5113495bSYour Name AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB, 708*5113495bSYour Name .d_COUNT_DEC_ADDRESS = AR6320V2_COUNT_DEC_ADDRESS, 709*5113495bSYour Name .d_HOST_INT_STATUS_CPU_MASK = AR6320V2_HOST_INT_STATUS_CPU_MASK, 710*5113495bSYour Name .d_HOST_INT_STATUS_CPU_LSB = AR6320V2_HOST_INT_STATUS_CPU_LSB, 711*5113495bSYour Name .d_HOST_INT_STATUS_ERROR_MASK = AR6320V2_HOST_INT_STATUS_ERROR_MASK, 712*5113495bSYour Name .d_HOST_INT_STATUS_ERROR_LSB = AR6320V2_HOST_INT_STATUS_ERROR_LSB, 713*5113495bSYour Name .d_HOST_INT_STATUS_COUNTER_MASK = 714*5113495bSYour Name AR6320V2_HOST_INT_STATUS_COUNTER_MASK, 715*5113495bSYour Name .d_HOST_INT_STATUS_COUNTER_LSB = AR6320V2_HOST_INT_STATUS_COUNTER_LSB, 716*5113495bSYour Name .d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS, 717*5113495bSYour Name .d_WINDOW_DATA_ADDRESS = AR6320V2_WINDOW_DATA_ADDRESS, 718*5113495bSYour Name .d_WINDOW_READ_ADDR_ADDRESS = AR6320V2_WINDOW_READ_ADDR_ADDRESS, 719*5113495bSYour Name .d_WINDOW_WRITE_ADDR_ADDRESS = AR6320V2_WINDOW_WRITE_ADDR_ADDRESS, 720*5113495bSYour Name .d_SOC_GLOBAL_RESET_ADDRESS = AR6320V2_SOC_GLOBAL_RESET_ADDRESS, 721*5113495bSYour Name .d_RTC_STATE_ADDRESS = AR6320V2_RTC_STATE_ADDRESS, 722*5113495bSYour Name .d_RTC_STATE_COLD_RESET_MASK = AR6320V2_RTC_STATE_COLD_RESET_MASK, 723*5113495bSYour Name .d_RTC_STATE_V_MASK = AR6320V2_RTC_STATE_V_MASK, 724*5113495bSYour Name .d_RTC_STATE_V_LSB = AR6320V2_RTC_STATE_V_LSB, 725*5113495bSYour Name .d_FW_IND_EVENT_PENDING = AR6320V2_FW_IND_EVENT_PENDING, 726*5113495bSYour Name .d_FW_IND_INITIALIZED = AR6320V2_FW_IND_INITIALIZED, 727*5113495bSYour Name .d_RTC_STATE_V_ON = AR6320V2_RTC_STATE_V_ON, 728*5113495bSYour Name #if defined(SDIO_3_0) 729*5113495bSYour Name .d_HOST_INT_STATUS_MBOX_DATA_MASK = 730*5113495bSYour Name AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK, 731*5113495bSYour Name .d_HOST_INT_STATUS_MBOX_DATA_LSB = 732*5113495bSYour Name AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB, 733*5113495bSYour Name #endif 734*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 735*5113495bSYour Name defined(HIF_IPCI) 736*5113495bSYour Name .d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER, 737*5113495bSYour Name .d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK, 738*5113495bSYour Name .d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK, 739*5113495bSYour Name .d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS, 740*5113495bSYour Name .d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET, 741*5113495bSYour Name .d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS, 742*5113495bSYour Name .d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK, 743*5113495bSYour Name .d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS, 744*5113495bSYour Name .d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK, 745*5113495bSYour Name .d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS, 746*5113495bSYour Name .d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS, 747*5113495bSYour Name .d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS, 748*5113495bSYour Name .d_HOST_CE_COUNT = 8, 749*5113495bSYour Name .d_ENABLE_MSI = 0, 750*5113495bSYour Name #endif 751*5113495bSYour Name #if defined(HIF_SDIO) 752*5113495bSYour Name .d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER, 753*5113495bSYour Name #endif 754*5113495bSYour Name }; 755*5113495bSYour Name 756*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \ 757*5113495bSYour Name defined(HIF_IPCI) 758*5113495bSYour Name struct ce_reg_def ar6320v2_ce_targetdef = { 759*5113495bSYour Name /* copy_engine.c */ 760*5113495bSYour Name .d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS, 761*5113495bSYour Name .d_SRC_WATERMARK_ADDRESS = AR6320V2_SRC_WATERMARK_ADDRESS, 762*5113495bSYour Name .d_SRC_WATERMARK_LOW_MASK = AR6320V2_SRC_WATERMARK_LOW_MASK, 763*5113495bSYour Name .d_SRC_WATERMARK_HIGH_MASK = AR6320V2_SRC_WATERMARK_HIGH_MASK, 764*5113495bSYour Name .d_DST_WATERMARK_LOW_MASK = AR6320V2_DST_WATERMARK_LOW_MASK, 765*5113495bSYour Name .d_DST_WATERMARK_HIGH_MASK = AR6320V2_DST_WATERMARK_HIGH_MASK, 766*5113495bSYour Name .d_CURRENT_SRRI_ADDRESS = AR6320V2_CURRENT_SRRI_ADDRESS, 767*5113495bSYour Name .d_CURRENT_DRRI_ADDRESS = AR6320V2_CURRENT_DRRI_ADDRESS, 768*5113495bSYour Name .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = 769*5113495bSYour Name AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 770*5113495bSYour Name .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = 771*5113495bSYour Name AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 772*5113495bSYour Name .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = 773*5113495bSYour Name AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 774*5113495bSYour Name .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = 775*5113495bSYour Name AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK, 776*5113495bSYour Name .d_HOST_IS_ADDRESS = AR6320V2_HOST_IS_ADDRESS, 777*5113495bSYour Name .d_HOST_IS_COPY_COMPLETE_MASK = AR6320V2_HOST_IS_COPY_COMPLETE_MASK, 778*5113495bSYour Name .d_CE_WRAPPER_BASE_ADDRESS = AR6320V2_CE_WRAPPER_BASE_ADDRESS, 779*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = 780*5113495bSYour Name AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, 781*5113495bSYour Name .d_HOST_IE_ADDRESS = AR6320V2_HOST_IE_ADDRESS, 782*5113495bSYour Name .d_HOST_IE_COPY_COMPLETE_MASK = AR6320V2_HOST_IE_COPY_COMPLETE_MASK, 783*5113495bSYour Name .d_SR_BA_ADDRESS = AR6320V2_SR_BA_ADDRESS, 784*5113495bSYour Name .d_SR_SIZE_ADDRESS = AR6320V2_SR_SIZE_ADDRESS, 785*5113495bSYour Name .d_CE_CTRL1_ADDRESS = AR6320V2_CE_CTRL1_ADDRESS, 786*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK, 787*5113495bSYour Name .d_DR_BA_ADDRESS = AR6320V2_DR_BA_ADDRESS, 788*5113495bSYour Name .d_DR_SIZE_ADDRESS = AR6320V2_DR_SIZE_ADDRESS, 789*5113495bSYour Name .d_MISC_IE_ADDRESS = AR6320V2_MISC_IE_ADDRESS, 790*5113495bSYour Name .d_MISC_IS_AXI_ERR_MASK = AR6320V2_MISC_IS_AXI_ERR_MASK, 791*5113495bSYour Name .d_MISC_IS_DST_ADDR_ERR_MASK = AR6320V2_MISC_IS_DST_ADDR_ERR_MASK, 792*5113495bSYour Name .d_MISC_IS_SRC_LEN_ERR_MASK = AR6320V2_MISC_IS_SRC_LEN_ERR_MASK, 793*5113495bSYour Name .d_MISC_IS_DST_MAX_LEN_VIO_MASK = 794*5113495bSYour Name AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK, 795*5113495bSYour Name .d_MISC_IS_DST_RING_OVERFLOW_MASK = 796*5113495bSYour Name AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK, 797*5113495bSYour Name .d_MISC_IS_SRC_RING_OVERFLOW_MASK = 798*5113495bSYour Name AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK, 799*5113495bSYour Name .d_SRC_WATERMARK_LOW_LSB = AR6320V2_SRC_WATERMARK_LOW_LSB, 800*5113495bSYour Name .d_SRC_WATERMARK_HIGH_LSB = AR6320V2_SRC_WATERMARK_HIGH_LSB, 801*5113495bSYour Name .d_DST_WATERMARK_LOW_LSB = AR6320V2_DST_WATERMARK_LOW_LSB, 802*5113495bSYour Name .d_DST_WATERMARK_HIGH_LSB = AR6320V2_DST_WATERMARK_HIGH_LSB, 803*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = 804*5113495bSYour Name AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 805*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = 806*5113495bSYour Name AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 807*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB, 808*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = 809*5113495bSYour Name AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 810*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = 811*5113495bSYour Name AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 812*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = 813*5113495bSYour Name AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 814*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = 815*5113495bSYour Name AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 816*5113495bSYour Name .d_CE_WRAPPER_DEBUG_OFFSET = AR6320V2_CE_WRAPPER_DEBUG_OFFSET, 817*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB, 818*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB, 819*5113495bSYour Name .d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK, 820*5113495bSYour Name .d_CE_DEBUG_OFFSET = AR6320V2_CE_DEBUG_OFFSET, 821*5113495bSYour Name .d_CE_DEBUG_SEL_MSB = AR6320V2_CE_DEBUG_SEL_MSB, 822*5113495bSYour Name .d_CE_DEBUG_SEL_LSB = AR6320V2_CE_DEBUG_SEL_LSB, 823*5113495bSYour Name .d_CE_DEBUG_SEL_MASK = AR6320V2_CE_DEBUG_SEL_MASK, 824*5113495bSYour Name .d_CE0_BASE_ADDRESS = AR6320V2_CE0_BASE_ADDRESS, 825*5113495bSYour Name .d_CE1_BASE_ADDRESS = AR6320V2_CE1_BASE_ADDRESS, 826*5113495bSYour Name 827*5113495bSYour Name }; 828*5113495bSYour Name #endif 829*5113495bSYour Name #endif 830