xref: /wlan-driver/qca-wifi-host-cmn/hif/src/ar6320v2def.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef _AR6320V2DEF_H_
20 #define _AR6320V2DEF_H_
21 
22 /* Base Addresses */
23 #define AR6320V2_RTC_SOC_BASE_ADDRESS                     0x00000800
24 #define AR6320V2_RTC_WMAC_BASE_ADDRESS                    0x00001000
25 #define AR6320V2_MAC_COEX_BASE_ADDRESS                    0x0000f000
26 #define AR6320V2_BT_COEX_BASE_ADDRESS                     0x00002000
27 #define AR6320V2_SOC_PCIE_BASE_ADDRESS                    0x00038000
28 #define AR6320V2_SOC_CORE_BASE_ADDRESS                    0x0003a000
29 #define AR6320V2_WLAN_UART_BASE_ADDRESS                   0x0000c000
30 #define AR6320V2_WLAN_SI_BASE_ADDRESS                     0x00010000
31 #define AR6320V2_WLAN_GPIO_BASE_ADDRESS                   0x00005000
32 #define AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS            0x00006000
33 #define AR6320V2_WLAN_MAC_BASE_ADDRESS                    0x00010000
34 #define AR6320V2_EFUSE_BASE_ADDRESS                       0x00024000
35 #define AR6320V2_FPGA_REG_BASE_ADDRESS                    0x00039000
36 #define AR6320V2_WLAN_UART2_BASE_ADDRESS                  0x00054c00
37 #define AR6320V2_DBI_BASE_ADDRESS                         0x0003c000
38 
39 #define AR6320V2_SCRATCH_3_ADDRESS                        0x0028
40 #define AR6320V2_TARG_DRAM_START                          0x00400000
41 #define AR6320V2_SOC_SYSTEM_SLEEP_OFFSET                  0x000000c0
42 #define AR6320V2_SOC_RESET_CONTROL_OFFSET                 0x00000000
43 #define AR6320V2_SOC_CLOCK_CONTROL_OFFSET                 0x00000028
44 #define AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
45 #define AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK           0x00000000
46 #define AR6320V2_WLAN_GPIO_PIN0_ADDRESS                   0x00000068
47 #define AR6320V2_WLAN_GPIO_PIN1_ADDRESS                   0x0000006c
48 #define AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK               0x00007800
49 #define AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK               0x00007800
50 #define AR6320V2_SOC_CPU_CLOCK_OFFSET                     0x00000020
51 #define AR6320V2_SOC_LPO_CAL_OFFSET                       0x000000e0
52 #define AR6320V2_WLAN_GPIO_PIN10_ADDRESS                  0x00000090
53 #define AR6320V2_WLAN_GPIO_PIN11_ADDRESS                  0x00000094
54 #define AR6320V2_WLAN_GPIO_PIN12_ADDRESS                  0x00000098
55 #define AR6320V2_WLAN_GPIO_PIN13_ADDRESS                  0x0000009c
56 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB               0
57 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
58 #define AR6320V2_SOC_LPO_CAL_ENABLE_LSB                   20
59 #define AR6320V2_SOC_LPO_CAL_ENABLE_MASK                  0x00100000
60 
61 #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
62 #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
63 #define AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000008
64 #define AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000004
65 #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB              18
66 #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
67 #define AR6320V2_SI_CONFIG_I2C_LSB                        16
68 #define AR6320V2_SI_CONFIG_I2C_MASK                       0x00010000
69 #define AR6320V2_SI_CONFIG_POS_SAMPLE_LSB                 7
70 #define AR6320V2_SI_CONFIG_POS_SAMPLE_MASK                0x00000080
71 #define AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB               4
72 #define AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
73 #define AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB              5
74 #define AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
75 #define AR6320V2_SI_CONFIG_DIVIDER_LSB                    0
76 #define AR6320V2_SI_CONFIG_DIVIDER_MASK                   0x0000000f
77 #define AR6320V2_SI_CONFIG_OFFSET                         0x00000000
78 #define AR6320V2_SI_TX_DATA0_OFFSET                       0x00000008
79 #define AR6320V2_SI_TX_DATA1_OFFSET                       0x0000000c
80 #define AR6320V2_SI_RX_DATA0_OFFSET                       0x00000010
81 #define AR6320V2_SI_RX_DATA1_OFFSET                       0x00000014
82 #define AR6320V2_SI_CS_OFFSET                             0x00000004
83 #define AR6320V2_SI_CS_DONE_ERR_MASK                      0x00000400
84 #define AR6320V2_SI_CS_DONE_INT_MASK                      0x00000200
85 #define AR6320V2_SI_CS_START_LSB                          8
86 #define AR6320V2_SI_CS_START_MASK                         0x00000100
87 #define AR6320V2_SI_CS_RX_CNT_LSB                         4
88 #define AR6320V2_SI_CS_RX_CNT_MASK                        0x000000f0
89 #define AR6320V2_SI_CS_TX_CNT_LSB                         0
90 #define AR6320V2_SI_CS_TX_CNT_MASK                        0x0000000f
91 #define AR6320V2_CE_COUNT                                 8
92 #define AR6320V2_SR_WR_INDEX_ADDRESS                      0x003c
93 #define AR6320V2_DST_WATERMARK_ADDRESS                    0x0050
94 #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB             14
95 #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK            0x00004000
96 #define AR6320V2_RX_MPDU_START_0_RETRY_LSB                14
97 #define AR6320V2_RX_MPDU_START_0_RETRY_MASK               0x00004000
98 #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB              16
99 #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK             0x0fff0000
100 #define AR6320V2_RX_MPDU_START_2_PN_47_32_LSB             0
101 #define AR6320V2_RX_MPDU_START_2_PN_47_32_MASK            0x0000ffff
102 #define AR6320V2_RX_MPDU_START_2_TID_LSB                  28
103 #define AR6320V2_RX_MPDU_START_2_TID_MASK                 0xf0000000
104 #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB      16
105 #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK     0xffff0000
106 #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB              15
107 #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK             0x00008000
108 #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB           2
109 #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK          0x00000004
110 #define AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB              13
111 #define AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK             0x00002000
112 #define AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK      0x08000000
113 #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB      16
114 #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK     0x00ff0000
115 #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB          0
116 #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK         0x00003fff
117 
118 #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET      0x00000008
119 #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB         8
120 #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK        0x00000300
121 #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB            13
122 #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK           0x00002000
123 #define AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK            0x00000400
124 #define AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK            0x80000000
125 #define AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK  0x00040000
126 #define AR6320V2_DST_WR_INDEX_ADDRESS                     0x0040
127 #define AR6320V2_SRC_WATERMARK_ADDRESS                    0x004c
128 #define AR6320V2_SRC_WATERMARK_LOW_MASK                   0xffff0000
129 #define AR6320V2_SRC_WATERMARK_HIGH_MASK                  0x0000ffff
130 #define AR6320V2_DST_WATERMARK_LOW_MASK                   0xffff0000
131 #define AR6320V2_DST_WATERMARK_HIGH_MASK                  0x0000ffff
132 #define AR6320V2_CURRENT_SRRI_ADDRESS                     0x0044
133 #define AR6320V2_CURRENT_DRRI_ADDRESS                     0x0048
134 #define AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK     0x00000002
135 #define AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK      0x00000004
136 #define AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK     0x00000008
137 #define AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK      0x00000010
138 #define AR6320V2_HOST_IS_ADDRESS                          0x0030
139 #define AR6320V2_HOST_IS_COPY_COMPLETE_MASK               0x00000001
140 #define AR6320V2_HOST_IE_ADDRESS                          0x002c
141 #define AR6320V2_HOST_IE_COPY_COMPLETE_MASK               0x00000001
142 #define AR6320V2_SR_BA_ADDRESS                            0x0000
143 #define AR6320V2_SR_SIZE_ADDRESS                          0x0004
144 #define AR6320V2_DR_BA_ADDRESS                            0x0008
145 #define AR6320V2_DR_SIZE_ADDRESS                          0x000c
146 #define AR6320V2_MISC_IE_ADDRESS                          0x0034
147 #define AR6320V2_MISC_IS_AXI_ERR_MASK                     0x00000400
148 #define AR6320V2_MISC_IS_DST_ADDR_ERR_MASK                0x00000200
149 #define AR6320V2_MISC_IS_SRC_LEN_ERR_MASK                 0x00000100
150 #define AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK             0x00000080
151 #define AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK           0x00000040
152 #define AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK           0x00000020
153 #define AR6320V2_SRC_WATERMARK_LOW_LSB                    16
154 #define AR6320V2_SRC_WATERMARK_HIGH_LSB                   0
155 #define AR6320V2_DST_WATERMARK_LOW_LSB                    16
156 #define AR6320V2_DST_WATERMARK_HIGH_LSB                   0
157 #define AR6320V2_SOC_GLOBAL_RESET_ADDRESS                 0x0008
158 #define AR6320V2_RTC_STATE_ADDRESS                        0x0000
159 #define AR6320V2_RTC_STATE_COLD_RESET_MASK                0x00002000
160 #define AR6320V2_RTC_STATE_V_MASK                         0x00000007
161 #define AR6320V2_RTC_STATE_V_LSB                          0
162 #define AR6320V2_RTC_STATE_V_ON                           3
163 #define AR6320V2_FW_IND_EVENT_PENDING                     1
164 #define AR6320V2_FW_IND_INITIALIZED                       2
165 #define AR6320V2_CPU_INTR_ADDRESS                         0x0010
166 #define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
167 #define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
168 #define AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
169 #define AR6320V2_SOC_RESET_CONTROL_ADDRESS                0x00000000
170 #define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
171 #define AR6320V2_CORE_CTRL_ADDRESS                        0x0000
172 #define AR6320V2_CORE_CTRL_CPU_INTR_MASK                  0x00002000
173 #define AR6320V2_LOCAL_SCRATCH_OFFSET                     0x000000c0
174 #define AR6320V2_CLOCK_GPIO_OFFSET                        0xffffffff
175 #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
176 #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
177 #define AR6320V2_SOC_CHIP_ID_ADDRESS                      0x000000f0
178 #define AR6320V2_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
179 #define AR6320V2_SOC_CHIP_ID_VERSION_LSB                  18
180 #define AR6320V2_SOC_CHIP_ID_REVISION_MASK                0x00000f00
181 #define AR6320V2_SOC_CHIP_ID_REVISION_LSB                 8
182 #if defined(HIF_SDIO)
183 #define AR6320V2_FW_IND_HELPER                            4
184 #endif
185 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
186     defined(HIF_IPCI)
187 #define AR6320V2_CE_WRAPPER_BASE_ADDRESS                  0x00034000
188 #define AR6320V2_CE0_BASE_ADDRESS                         0x00034400
189 #define AR6320V2_CE1_BASE_ADDRESS                         0x00034800
190 #define AR6320V2_CE2_BASE_ADDRESS                         0x00034c00
191 #define AR6320V2_CE3_BASE_ADDRESS                         0x00035000
192 #define AR6320V2_CE4_BASE_ADDRESS                         0x00035400
193 #define AR6320V2_CE5_BASE_ADDRESS                         0x00035800
194 #define AR6320V2_CE6_BASE_ADDRESS                         0x00035c00
195 #define AR6320V2_CE7_BASE_ADDRESS                         0x00036000
196 #define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS       0x00007800
197 #define AR6320V2_CE_CTRL1_ADDRESS                         0x0010
198 #define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK                0x0000ffff
199 #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS     0x0000
200 #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
201 #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  8
202 #define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB                 0
203 #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK      0x00010000
204 #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK      0x00020000
205 #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB       16
206 #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB       17
207 #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
208 #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB  5
209 #define AR6320V2_PCIE_SOC_WAKE_RESET                      0x00000000
210 #define AR6320V2_PCIE_SOC_WAKE_ADDRESS                    0x0004
211 #define AR6320V2_PCIE_SOC_WAKE_V_MASK                     0x00000001
212 #define AR6320V2_MUX_ID_MASK                              0x0000
213 #define AR6320V2_TRANSACTION_ID_MASK                      0x3fff
214 #define AR6320V2_PCIE_LOCAL_BASE_ADDRESS                  0x80000
215 #define AR6320V2_FW_IND_HELPER                            4
216 #define AR6320V2_PCIE_INTR_ENABLE_ADDRESS                 0x0008
217 #define AR6320V2_PCIE_INTR_CLR_ADDRESS                    0x0014
218 #define AR6320V2_PCIE_INTR_FIRMWARE_MASK                  0x00000400
219 #define AR6320V2_PCIE_INTR_CE0_MASK                       0x00000800
220 #define AR6320V2_PCIE_INTR_CE_MASK_ALL                    0x0007f800
221 #define AR6320V2_PCIE_INTR_CAUSE_ADDRESS                  0x000c
222 #define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK            0x00000001
223 #define AR6320V2_SOC_POWER_REG_OFFSET                     0x0000010c
224 /* Copy Engine Debug */
225 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
226 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
227 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
228 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
229 #define AR6320V2_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
230 #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
231 #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
232 #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
233 #define AR6320V2_WLAN_DEBUG_OUT_OFFSET                    0x00000110
234 #define AR6320V2_WLAN_DEBUG_OUT_DATA_MSB                  19
235 #define AR6320V2_WLAN_DEBUG_OUT_DATA_LSB                  0
236 #define AR6320V2_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
237 #define AR6320V2_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
238 #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
239 #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
240 #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
241 #define AR6320V2_AMBA_DEBUG_BUS_SEL_MSB                   4
242 #define AR6320V2_AMBA_DEBUG_BUS_SEL_LSB                   0
243 #define AR6320V2_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
244 #define AR6320V2_CE_WRAPPER_DEBUG_OFFSET                  0x0008
245 #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB                 5
246 #define AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB                 0
247 #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK                0x0000003f
248 #define AR6320V2_CE_DEBUG_OFFSET                          0x0054
249 #define AR6320V2_CE_DEBUG_SEL_MSB                         5
250 #define AR6320V2_CE_DEBUG_SEL_LSB                         0
251 #define AR6320V2_CE_DEBUG_SEL_MASK                        0x0000003f
252 /* End */
253 
254 /* PLL start */
255 #define AR6320V2_EFUSE_OFFSET                             0x0000032c
256 #define AR6320V2_EFUSE_XTAL_SEL_MSB                       10
257 #define AR6320V2_EFUSE_XTAL_SEL_LSB                       8
258 #define AR6320V2_EFUSE_XTAL_SEL_MASK                      0x00000700
259 #define AR6320V2_BB_PLL_CONFIG_OFFSET                     0x000002f4
260 #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB                 20
261 #define AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB                 18
262 #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
263 #define AR6320V2_BB_PLL_CONFIG_FRAC_MSB                   17
264 #define AR6320V2_BB_PLL_CONFIG_FRAC_LSB                   0
265 #define AR6320V2_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
266 #define AR6320V2_WLAN_PLL_SETTLE_TIME_MSB                 10
267 #define AR6320V2_WLAN_PLL_SETTLE_TIME_LSB                 0
268 #define AR6320V2_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
269 #define AR6320V2_WLAN_PLL_SETTLE_OFFSET                   0x0018
270 #define AR6320V2_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
271 #define AR6320V2_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
272 #define AR6320V2_WLAN_PLL_SETTLE_RESET                    0x00000400
273 #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB               18
274 #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB               18
275 #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
276 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB              16
277 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB              16
278 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
279 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
280 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
281 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
282 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
283 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
284 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB              13
285 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB              10
286 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
287 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
288 #define AR6320V2_WLAN_PLL_CONTROL_DIV_MSB                 9
289 #define AR6320V2_WLAN_PLL_CONTROL_DIV_LSB                 0
290 #define AR6320V2_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
291 #define AR6320V2_WLAN_PLL_CONTROL_DIV_RESET               0x11
292 #define AR6320V2_WLAN_PLL_CONTROL_OFFSET                  0x0014
293 #define AR6320V2_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
294 #define AR6320V2_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
295 #define AR6320V2_WLAN_PLL_CONTROL_RESET                   0x00010011
296 #define AR6320V2_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
297 #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB                2
298 #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB                0
299 #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
300 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
301 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
302 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
303 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
304 #define AR6320V2_RTC_SYNC_STATUS_OFFSET                   0x0244
305 #define AR6320V2_SOC_CPU_CLOCK_OFFSET                     0x00000020
306 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB               1
307 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB               0
308 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
309 /* PLL end */
310 
311 #define AR6320V2_PCIE_INTR_CE_MASK(n) \
312 	(AR6320V2_PCIE_INTR_CE0_MASK << (n))
313 #endif
314 #define AR6320V2_DRAM_BASE_ADDRESS            AR6320V2_TARG_DRAM_START
315 #define AR6320V2_FW_INDICATOR_ADDRESS \
316 	(AR6320V2_SOC_CORE_BASE_ADDRESS + AR6320V2_SCRATCH_3_ADDRESS)
317 #define AR6320V2_SYSTEM_SLEEP_OFFSET          AR6320V2_SOC_SYSTEM_SLEEP_OFFSET
318 #define AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET     0x002c
319 #define AR6320V2_WLAN_RESET_CONTROL_OFFSET    AR6320V2_SOC_RESET_CONTROL_OFFSET
320 #define AR6320V2_CLOCK_CONTROL_OFFSET         AR6320V2_SOC_CLOCK_CONTROL_OFFSET
321 #define AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK \
322 	AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK
323 #define AR6320V2_RESET_CONTROL_MBOX_RST_MASK  0x00000004
324 #define AR6320V2_RESET_CONTROL_SI0_RST_MASK \
325 	AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK
326 #define AR6320V2_GPIO_BASE_ADDRESS         AR6320V2_WLAN_GPIO_BASE_ADDRESS
327 #define AR6320V2_GPIO_PIN0_OFFSET          AR6320V2_WLAN_GPIO_PIN0_ADDRESS
328 #define AR6320V2_GPIO_PIN1_OFFSET          AR6320V2_WLAN_GPIO_PIN1_ADDRESS
329 #define AR6320V2_GPIO_PIN0_CONFIG_MASK     AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK
330 #define AR6320V2_GPIO_PIN1_CONFIG_MASK     AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK
331 #define AR6320V2_SI_BASE_ADDRESS           0x00050000
332 #define AR6320V2_CPU_CLOCK_OFFSET          AR6320V2_SOC_CPU_CLOCK_OFFSET
333 #define AR6320V2_LPO_CAL_OFFSET            AR6320V2_SOC_LPO_CAL_OFFSET
334 #define AR6320V2_GPIO_PIN10_OFFSET         AR6320V2_WLAN_GPIO_PIN10_ADDRESS
335 #define AR6320V2_GPIO_PIN11_OFFSET         AR6320V2_WLAN_GPIO_PIN11_ADDRESS
336 #define AR6320V2_GPIO_PIN12_OFFSET         AR6320V2_WLAN_GPIO_PIN12_ADDRESS
337 #define AR6320V2_GPIO_PIN13_OFFSET         AR6320V2_WLAN_GPIO_PIN13_ADDRESS
338 #define AR6320V2_CPU_CLOCK_STANDARD_LSB    AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB
339 #define AR6320V2_CPU_CLOCK_STANDARD_MASK   AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK
340 #define AR6320V2_LPO_CAL_ENABLE_LSB        AR6320V2_SOC_LPO_CAL_ENABLE_LSB
341 #define AR6320V2_LPO_CAL_ENABLE_MASK       AR6320V2_SOC_LPO_CAL_ENABLE_MASK
342 #define AR6320V2_ANALOG_INTF_BASE_ADDRESS \
343 	AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS
344 #define AR6320V2_MBOX_BASE_ADDRESS                       0x00008000
345 #define AR6320V2_INT_STATUS_ENABLE_ERROR_LSB             7
346 #define AR6320V2_INT_STATUS_ENABLE_ERROR_MASK            0x00000080
347 #define AR6320V2_INT_STATUS_ENABLE_CPU_LSB               6
348 #define AR6320V2_INT_STATUS_ENABLE_CPU_MASK              0x00000040
349 #define AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB           4
350 #define AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK          0x00000010
351 #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB         0
352 #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK        0x0000000f
353 #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    17
354 #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   0x00020000
355 #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     16
356 #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    0x00010000
357 #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB       24
358 #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK      0xff000000
359 #define AR6320V2_INT_STATUS_ENABLE_ADDRESS               0x0828
360 #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB           8
361 #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK          0x0000ff00
362 #define AR6320V2_HOST_INT_STATUS_ADDRESS                 0x0800
363 #define AR6320V2_CPU_INT_STATUS_ADDRESS                  0x0801
364 #define AR6320V2_ERROR_INT_STATUS_ADDRESS                0x0802
365 #define AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK            0x00040000
366 #define AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB             18
367 #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      0x00020000
368 #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       17
369 #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK       0x00010000
370 #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB        16
371 #define AR6320V2_COUNT_DEC_ADDRESS                       0x0840
372 #define AR6320V2_HOST_INT_STATUS_CPU_MASK                0x00000040
373 #define AR6320V2_HOST_INT_STATUS_CPU_LSB                 6
374 #define AR6320V2_HOST_INT_STATUS_ERROR_MASK              0x00000080
375 #define AR6320V2_HOST_INT_STATUS_ERROR_LSB               7
376 #define AR6320V2_HOST_INT_STATUS_COUNTER_MASK            0x00000010
377 #define AR6320V2_HOST_INT_STATUS_COUNTER_LSB             4
378 #define AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS              0x0805
379 #define AR6320V2_WINDOW_DATA_ADDRESS                     0x0874
380 #define AR6320V2_WINDOW_READ_ADDR_ADDRESS                0x087c
381 #define AR6320V2_WINDOW_WRITE_ADDR_ADDRESS               0x0878
382 #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f
383 #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB 0
384 
385 struct targetdef_s ar6320v2_targetdef = {
386 	.d_RTC_SOC_BASE_ADDRESS = AR6320V2_RTC_SOC_BASE_ADDRESS,
387 	.d_RTC_WMAC_BASE_ADDRESS = AR6320V2_RTC_WMAC_BASE_ADDRESS,
388 	.d_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET,
389 	.d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET,
390 	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
391 		AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
392 	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
393 		AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
394 	.d_CLOCK_CONTROL_OFFSET = AR6320V2_CLOCK_CONTROL_OFFSET,
395 	.d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK,
396 	.d_RESET_CONTROL_OFFSET = AR6320V2_SOC_RESET_CONTROL_OFFSET,
397 	.d_RESET_CONTROL_MBOX_RST_MASK = AR6320V2_RESET_CONTROL_MBOX_RST_MASK,
398 	.d_RESET_CONTROL_SI0_RST_MASK = AR6320V2_RESET_CONTROL_SI0_RST_MASK,
399 	.d_WLAN_RESET_CONTROL_OFFSET = AR6320V2_WLAN_RESET_CONTROL_OFFSET,
400 	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
401 		AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK,
402 	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
403 		AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK,
404 	.d_GPIO_BASE_ADDRESS = AR6320V2_GPIO_BASE_ADDRESS,
405 	.d_GPIO_PIN0_OFFSET = AR6320V2_GPIO_PIN0_OFFSET,
406 	.d_GPIO_PIN1_OFFSET = AR6320V2_GPIO_PIN1_OFFSET,
407 	.d_GPIO_PIN0_CONFIG_MASK = AR6320V2_GPIO_PIN0_CONFIG_MASK,
408 	.d_GPIO_PIN1_CONFIG_MASK = AR6320V2_GPIO_PIN1_CONFIG_MASK,
409 	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB,
410 	.d_SI_CONFIG_BIDIR_OD_DATA_MASK =
411 		AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK,
412 	.d_SI_CONFIG_I2C_LSB = AR6320V2_SI_CONFIG_I2C_LSB,
413 	.d_SI_CONFIG_I2C_MASK = AR6320V2_SI_CONFIG_I2C_MASK,
414 	.d_SI_CONFIG_POS_SAMPLE_LSB = AR6320V2_SI_CONFIG_POS_SAMPLE_LSB,
415 	.d_SI_CONFIG_POS_SAMPLE_MASK = AR6320V2_SI_CONFIG_POS_SAMPLE_MASK,
416 	.d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB,
417 	.d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK,
418 	.d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB,
419 	.d_SI_CONFIG_INACTIVE_DATA_MASK =
420 		AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK,
421 	.d_SI_CONFIG_DIVIDER_LSB = AR6320V2_SI_CONFIG_DIVIDER_LSB,
422 	.d_SI_CONFIG_DIVIDER_MASK = AR6320V2_SI_CONFIG_DIVIDER_MASK,
423 	.d_SI_BASE_ADDRESS = AR6320V2_SI_BASE_ADDRESS,
424 	.d_SI_CONFIG_OFFSET = AR6320V2_SI_CONFIG_OFFSET,
425 	.d_SI_TX_DATA0_OFFSET = AR6320V2_SI_TX_DATA0_OFFSET,
426 	.d_SI_TX_DATA1_OFFSET = AR6320V2_SI_TX_DATA1_OFFSET,
427 	.d_SI_RX_DATA0_OFFSET = AR6320V2_SI_RX_DATA0_OFFSET,
428 	.d_SI_RX_DATA1_OFFSET = AR6320V2_SI_RX_DATA1_OFFSET,
429 	.d_SI_CS_OFFSET = AR6320V2_SI_CS_OFFSET,
430 	.d_SI_CS_DONE_ERR_MASK = AR6320V2_SI_CS_DONE_ERR_MASK,
431 	.d_SI_CS_DONE_INT_MASK = AR6320V2_SI_CS_DONE_INT_MASK,
432 	.d_SI_CS_START_LSB = AR6320V2_SI_CS_START_LSB,
433 	.d_SI_CS_START_MASK = AR6320V2_SI_CS_START_MASK,
434 	.d_SI_CS_RX_CNT_LSB = AR6320V2_SI_CS_RX_CNT_LSB,
435 	.d_SI_CS_RX_CNT_MASK = AR6320V2_SI_CS_RX_CNT_MASK,
436 	.d_SI_CS_TX_CNT_LSB = AR6320V2_SI_CS_TX_CNT_LSB,
437 	.d_SI_CS_TX_CNT_MASK = AR6320V2_SI_CS_TX_CNT_MASK,
438 	.d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ,
439 	.d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ,
440 	.d_MBOX_BASE_ADDRESS = AR6320V2_MBOX_BASE_ADDRESS,
441 	.d_LOCAL_SCRATCH_OFFSET = AR6320V2_LOCAL_SCRATCH_OFFSET,
442 	.d_CPU_CLOCK_OFFSET = AR6320V2_CPU_CLOCK_OFFSET,
443 	.d_LPO_CAL_OFFSET = AR6320V2_LPO_CAL_OFFSET,
444 	.d_GPIO_PIN10_OFFSET = AR6320V2_GPIO_PIN10_OFFSET,
445 	.d_GPIO_PIN11_OFFSET = AR6320V2_GPIO_PIN11_OFFSET,
446 	.d_GPIO_PIN12_OFFSET = AR6320V2_GPIO_PIN12_OFFSET,
447 	.d_GPIO_PIN13_OFFSET = AR6320V2_GPIO_PIN13_OFFSET,
448 	.d_CLOCK_GPIO_OFFSET = AR6320V2_CLOCK_GPIO_OFFSET,
449 	.d_CPU_CLOCK_STANDARD_LSB = AR6320V2_CPU_CLOCK_STANDARD_LSB,
450 	.d_CPU_CLOCK_STANDARD_MASK = AR6320V2_CPU_CLOCK_STANDARD_MASK,
451 	.d_LPO_CAL_ENABLE_LSB = AR6320V2_LPO_CAL_ENABLE_LSB,
452 	.d_LPO_CAL_ENABLE_MASK = AR6320V2_LPO_CAL_ENABLE_MASK,
453 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB =
454 		AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
455 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
456 		AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
457 	.d_ANALOG_INTF_BASE_ADDRESS = AR6320V2_ANALOG_INTF_BASE_ADDRESS,
458 	.d_WLAN_MAC_BASE_ADDRESS = AR6320V2_WLAN_MAC_BASE_ADDRESS,
459 	.d_FW_INDICATOR_ADDRESS = AR6320V2_FW_INDICATOR_ADDRESS,
460 	.d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS,
461 	.d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS,
462 	.d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS,
463 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
464     defined(HIF_IPCI)
465 	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
466 	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
467 #endif
468 	.d_CORE_CTRL_CPU_INTR_MASK = AR6320V2_CORE_CTRL_CPU_INTR_MASK,
469 	.d_SR_WR_INDEX_ADDRESS = AR6320V2_SR_WR_INDEX_ADDRESS,
470 	.d_DST_WATERMARK_ADDRESS = AR6320V2_DST_WATERMARK_ADDRESS,
471 	/* htt_rx.c */
472 	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
473 		AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK,
474 	.d_RX_MSDU_END_4_FIRST_MSDU_LSB =
475 		AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB,
476 	.d_RX_MPDU_START_0_RETRY_MASK =
477 		AR6320V2_RX_MPDU_START_0_RETRY_MASK,
478 	.d_RX_MPDU_START_0_SEQ_NUM_MASK =
479 		AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK,
480 	.d_RX_MPDU_START_0_SEQ_NUM_MASK =
481 		AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK,
482 	.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB,
483 	.d_RX_MPDU_START_2_PN_47_32_LSB =
484 		AR6320V2_RX_MPDU_START_2_PN_47_32_LSB,
485 	.d_RX_MPDU_START_2_PN_47_32_MASK =
486 		AR6320V2_RX_MPDU_START_2_PN_47_32_MASK,
487 	.d_RX_MPDU_START_2_TID_LSB =
488 		AR6320V2_RX_MPDU_START_2_TID_LSB,
489 	.d_RX_MPDU_START_2_TID_MASK =
490 		AR6320V2_RX_MPDU_START_2_TID_MASK,
491 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
492 		AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
493 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
494 		AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
495 	.d_RX_MSDU_END_4_LAST_MSDU_MASK =
496 		AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK,
497 	.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB,
498 	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
499 		AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK,
500 	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
501 		AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB,
502 	.d_RX_ATTENTION_0_FRAGMENT_MASK =
503 		AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK,
504 	.d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB,
505 	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
506 		AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
507 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
508 		AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
509 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
510 		AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
511 	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
512 		AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK,
513 	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
514 		AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB,
515 	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
516 		AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
517 	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
518 		AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK,
519 	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
520 		AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB,
521 	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
522 		AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK,
523 	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
524 		AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB,
525 	.d_RX_ATTENTION_0_MORE_DATA_MASK =
526 		AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK,
527 	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
528 		AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK,
529 	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
530 		AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
531 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
532     defined(HIF_IPCI)
533 	.d_CE_COUNT = AR6320V2_CE_COUNT,
534 	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
535 	.d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS,
536 	.d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS,
537 	.d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK,
538 	.d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL,
539 	/* PLL start */
540 	.d_EFUSE_OFFSET = AR6320V2_EFUSE_OFFSET,
541 	.d_EFUSE_XTAL_SEL_MSB = AR6320V2_EFUSE_XTAL_SEL_MSB,
542 	.d_EFUSE_XTAL_SEL_LSB = AR6320V2_EFUSE_XTAL_SEL_LSB,
543 	.d_EFUSE_XTAL_SEL_MASK = AR6320V2_EFUSE_XTAL_SEL_MASK,
544 	.d_BB_PLL_CONFIG_OFFSET = AR6320V2_BB_PLL_CONFIG_OFFSET,
545 	.d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB,
546 	.d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB,
547 	.d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK,
548 	.d_BB_PLL_CONFIG_FRAC_MSB = AR6320V2_BB_PLL_CONFIG_FRAC_MSB,
549 	.d_BB_PLL_CONFIG_FRAC_LSB = AR6320V2_BB_PLL_CONFIG_FRAC_LSB,
550 	.d_BB_PLL_CONFIG_FRAC_MASK = AR6320V2_BB_PLL_CONFIG_FRAC_MASK,
551 	.d_WLAN_PLL_SETTLE_TIME_MSB = AR6320V2_WLAN_PLL_SETTLE_TIME_MSB,
552 	.d_WLAN_PLL_SETTLE_TIME_LSB = AR6320V2_WLAN_PLL_SETTLE_TIME_LSB,
553 	.d_WLAN_PLL_SETTLE_TIME_MASK = AR6320V2_WLAN_PLL_SETTLE_TIME_MASK,
554 	.d_WLAN_PLL_SETTLE_OFFSET = AR6320V2_WLAN_PLL_SETTLE_OFFSET,
555 	.d_WLAN_PLL_SETTLE_SW_MASK = AR6320V2_WLAN_PLL_SETTLE_SW_MASK,
556 	.d_WLAN_PLL_SETTLE_RSTMASK = AR6320V2_WLAN_PLL_SETTLE_RSTMASK,
557 	.d_WLAN_PLL_SETTLE_RESET = AR6320V2_WLAN_PLL_SETTLE_RESET,
558 	.d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB,
559 	.d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB,
560 	.d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK,
561 	.d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB,
562 	.d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB,
563 	.d_WLAN_PLL_CONTROL_BYPASS_MASK =
564 		AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK,
565 	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
566 		AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET,
567 	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB =
568 		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB,
569 	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB =
570 		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB,
571 	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
572 		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK,
573 	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
574 		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET,
575 	.d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB,
576 	.d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB,
577 	.d_WLAN_PLL_CONTROL_REFDIV_MASK =
578 		AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK,
579 	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
580 		AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET,
581 	.d_WLAN_PLL_CONTROL_DIV_MSB = AR6320V2_WLAN_PLL_CONTROL_DIV_MSB,
582 	.d_WLAN_PLL_CONTROL_DIV_LSB = AR6320V2_WLAN_PLL_CONTROL_DIV_LSB,
583 	.d_WLAN_PLL_CONTROL_DIV_MASK = AR6320V2_WLAN_PLL_CONTROL_DIV_MASK,
584 	.d_WLAN_PLL_CONTROL_DIV_RESET = AR6320V2_WLAN_PLL_CONTROL_DIV_RESET,
585 	.d_WLAN_PLL_CONTROL_OFFSET = AR6320V2_WLAN_PLL_CONTROL_OFFSET,
586 	.d_WLAN_PLL_CONTROL_SW_MASK = AR6320V2_WLAN_PLL_CONTROL_SW_MASK,
587 	.d_WLAN_PLL_CONTROL_RSTMASK = AR6320V2_WLAN_PLL_CONTROL_RSTMASK,
588 	.d_WLAN_PLL_CONTROL_RESET = AR6320V2_WLAN_PLL_CONTROL_RESET,
589 	.d_SOC_CORE_CLK_CTRL_OFFSET = AR6320V2_SOC_CORE_CLK_CTRL_OFFSET,
590 	.d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB,
591 	.d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB,
592 	.d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK,
593 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
594 		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
595 	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
596 		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
597 	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
598 		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
599 	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
600 		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
601 	.d_RTC_SYNC_STATUS_OFFSET = AR6320V2_RTC_SYNC_STATUS_OFFSET,
602 	.d_SOC_CPU_CLOCK_OFFSET = AR6320V2_SOC_CPU_CLOCK_OFFSET,
603 	.d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB,
604 	.d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB,
605 	.d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK,
606 	/* PLL end */
607 	.d_SOC_POWER_REG_OFFSET = AR6320V2_SOC_POWER_REG_OFFSET,
608 	.d_PCIE_INTR_CAUSE_ADDRESS = AR6320V2_PCIE_INTR_CAUSE_ADDRESS,
609 	.d_SOC_RESET_CONTROL_ADDRESS = AR6320V2_SOC_RESET_CONTROL_ADDRESS,
610 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
611 		AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
612 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
613 		AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
614 	.d_SOC_RESET_CONTROL_CE_RST_MASK =
615 		AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK,
616 	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET,
617 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB =
618 		AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
619 	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB =
620 		AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
621 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
622 		AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
623 	.d_WLAN_DEBUG_CONTROL_OFFSET = AR6320V2_WLAN_DEBUG_CONTROL_OFFSET,
624 	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
625 		AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB,
626 	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
627 		AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB,
628 	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
629 		AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK,
630 	.d_WLAN_DEBUG_OUT_OFFSET = AR6320V2_WLAN_DEBUG_OUT_OFFSET,
631 	.d_WLAN_DEBUG_OUT_DATA_MSB = AR6320V2_WLAN_DEBUG_OUT_DATA_MSB,
632 	.d_WLAN_DEBUG_OUT_DATA_LSB = AR6320V2_WLAN_DEBUG_OUT_DATA_LSB,
633 	.d_WLAN_DEBUG_OUT_DATA_MASK = AR6320V2_WLAN_DEBUG_OUT_DATA_MASK,
634 	.d_AMBA_DEBUG_BUS_OFFSET = AR6320V2_AMBA_DEBUG_BUS_OFFSET,
635 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
636 		AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
637 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
638 		AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
639 	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
640 		AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
641 	.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320V2_AMBA_DEBUG_BUS_SEL_MSB,
642 	.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320V2_AMBA_DEBUG_BUS_SEL_LSB,
643 	.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320V2_AMBA_DEBUG_BUS_SEL_MASK,
644 #endif
645 	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
646 		AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
647 	.d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS,
648 	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
649 		AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS,
650 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
651 		AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
652 	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
653 		AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS,
654 	/* chip id start */
655 	.d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS,
656 	.d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK,
657 	.d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB,
658 	.d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK,
659 	.d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB,
660 	/* chip id end */
661 };
662 
663 struct hostdef_s ar6320v2_hostdef = {
664 	.d_INT_STATUS_ENABLE_ERROR_LSB = AR6320V2_INT_STATUS_ENABLE_ERROR_LSB,
665 	.d_INT_STATUS_ENABLE_ERROR_MASK =
666 		AR6320V2_INT_STATUS_ENABLE_ERROR_MASK,
667 	.d_INT_STATUS_ENABLE_CPU_LSB = AR6320V2_INT_STATUS_ENABLE_CPU_LSB,
668 	.d_INT_STATUS_ENABLE_CPU_MASK = AR6320V2_INT_STATUS_ENABLE_CPU_MASK,
669 	.d_INT_STATUS_ENABLE_COUNTER_LSB =
670 		AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB,
671 	.d_INT_STATUS_ENABLE_COUNTER_MASK =
672 		AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK,
673 	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
674 		AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB,
675 	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
676 		AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK,
677 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
678 		AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
679 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
680 		AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
681 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
682 		AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
683 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
684 		AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
685 	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
686 		AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
687 	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
688 		AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
689 	.d_INT_STATUS_ENABLE_ADDRESS = AR6320V2_INT_STATUS_ENABLE_ADDRESS,
690 	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
691 		AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB,
692 	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
693 		AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK,
694 	.d_HOST_INT_STATUS_ADDRESS = AR6320V2_HOST_INT_STATUS_ADDRESS,
695 	.d_CPU_INT_STATUS_ADDRESS = AR6320V2_CPU_INT_STATUS_ADDRESS,
696 	.d_ERROR_INT_STATUS_ADDRESS = AR6320V2_ERROR_INT_STATUS_ADDRESS,
697 	.d_ERROR_INT_STATUS_WAKEUP_MASK =
698 		AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK,
699 	.d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB,
700 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
701 		AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
702 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
703 		AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
704 	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
705 		AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
706 	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
707 		AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
708 	.d_COUNT_DEC_ADDRESS = AR6320V2_COUNT_DEC_ADDRESS,
709 	.d_HOST_INT_STATUS_CPU_MASK = AR6320V2_HOST_INT_STATUS_CPU_MASK,
710 	.d_HOST_INT_STATUS_CPU_LSB = AR6320V2_HOST_INT_STATUS_CPU_LSB,
711 	.d_HOST_INT_STATUS_ERROR_MASK = AR6320V2_HOST_INT_STATUS_ERROR_MASK,
712 	.d_HOST_INT_STATUS_ERROR_LSB = AR6320V2_HOST_INT_STATUS_ERROR_LSB,
713 	.d_HOST_INT_STATUS_COUNTER_MASK =
714 		AR6320V2_HOST_INT_STATUS_COUNTER_MASK,
715 	.d_HOST_INT_STATUS_COUNTER_LSB = AR6320V2_HOST_INT_STATUS_COUNTER_LSB,
716 	.d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS,
717 	.d_WINDOW_DATA_ADDRESS = AR6320V2_WINDOW_DATA_ADDRESS,
718 	.d_WINDOW_READ_ADDR_ADDRESS = AR6320V2_WINDOW_READ_ADDR_ADDRESS,
719 	.d_WINDOW_WRITE_ADDR_ADDRESS = AR6320V2_WINDOW_WRITE_ADDR_ADDRESS,
720 	.d_SOC_GLOBAL_RESET_ADDRESS = AR6320V2_SOC_GLOBAL_RESET_ADDRESS,
721 	.d_RTC_STATE_ADDRESS = AR6320V2_RTC_STATE_ADDRESS,
722 	.d_RTC_STATE_COLD_RESET_MASK = AR6320V2_RTC_STATE_COLD_RESET_MASK,
723 	.d_RTC_STATE_V_MASK = AR6320V2_RTC_STATE_V_MASK,
724 	.d_RTC_STATE_V_LSB = AR6320V2_RTC_STATE_V_LSB,
725 	.d_FW_IND_EVENT_PENDING = AR6320V2_FW_IND_EVENT_PENDING,
726 	.d_FW_IND_INITIALIZED = AR6320V2_FW_IND_INITIALIZED,
727 	.d_RTC_STATE_V_ON = AR6320V2_RTC_STATE_V_ON,
728 #if defined(SDIO_3_0)
729 	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
730 		AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK,
731 	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
732 		AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB,
733 #endif
734 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
735     defined(HIF_IPCI)
736 	.d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER,
737 	.d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK,
738 	.d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK,
739 	.d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS,
740 	.d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET,
741 	.d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS,
742 	.d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK,
743 	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
744 	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
745 	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
746 	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
747 	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
748 	.d_HOST_CE_COUNT = 8,
749 	.d_ENABLE_MSI = 0,
750 #endif
751 #if defined(HIF_SDIO)
752 	.d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER,
753 #endif
754 };
755 
756 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
757     defined(HIF_IPCI)
758 struct ce_reg_def ar6320v2_ce_targetdef = {
759 	/* copy_engine.c  */
760 	.d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS,
761 	.d_SRC_WATERMARK_ADDRESS = AR6320V2_SRC_WATERMARK_ADDRESS,
762 	.d_SRC_WATERMARK_LOW_MASK = AR6320V2_SRC_WATERMARK_LOW_MASK,
763 	.d_SRC_WATERMARK_HIGH_MASK = AR6320V2_SRC_WATERMARK_HIGH_MASK,
764 	.d_DST_WATERMARK_LOW_MASK = AR6320V2_DST_WATERMARK_LOW_MASK,
765 	.d_DST_WATERMARK_HIGH_MASK = AR6320V2_DST_WATERMARK_HIGH_MASK,
766 	.d_CURRENT_SRRI_ADDRESS = AR6320V2_CURRENT_SRRI_ADDRESS,
767 	.d_CURRENT_DRRI_ADDRESS = AR6320V2_CURRENT_DRRI_ADDRESS,
768 	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
769 		AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
770 	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
771 		AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
772 	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
773 		AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
774 	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
775 		AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
776 	.d_HOST_IS_ADDRESS = AR6320V2_HOST_IS_ADDRESS,
777 	.d_HOST_IS_COPY_COMPLETE_MASK = AR6320V2_HOST_IS_COPY_COMPLETE_MASK,
778 	.d_CE_WRAPPER_BASE_ADDRESS = AR6320V2_CE_WRAPPER_BASE_ADDRESS,
779 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
780 		AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
781 	.d_HOST_IE_ADDRESS = AR6320V2_HOST_IE_ADDRESS,
782 	.d_HOST_IE_COPY_COMPLETE_MASK = AR6320V2_HOST_IE_COPY_COMPLETE_MASK,
783 	.d_SR_BA_ADDRESS = AR6320V2_SR_BA_ADDRESS,
784 	.d_SR_SIZE_ADDRESS = AR6320V2_SR_SIZE_ADDRESS,
785 	.d_CE_CTRL1_ADDRESS = AR6320V2_CE_CTRL1_ADDRESS,
786 	.d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK,
787 	.d_DR_BA_ADDRESS = AR6320V2_DR_BA_ADDRESS,
788 	.d_DR_SIZE_ADDRESS = AR6320V2_DR_SIZE_ADDRESS,
789 	.d_MISC_IE_ADDRESS = AR6320V2_MISC_IE_ADDRESS,
790 	.d_MISC_IS_AXI_ERR_MASK = AR6320V2_MISC_IS_AXI_ERR_MASK,
791 	.d_MISC_IS_DST_ADDR_ERR_MASK = AR6320V2_MISC_IS_DST_ADDR_ERR_MASK,
792 	.d_MISC_IS_SRC_LEN_ERR_MASK = AR6320V2_MISC_IS_SRC_LEN_ERR_MASK,
793 	.d_MISC_IS_DST_MAX_LEN_VIO_MASK =
794 		AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK,
795 	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
796 		AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK,
797 	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
798 		AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK,
799 	.d_SRC_WATERMARK_LOW_LSB = AR6320V2_SRC_WATERMARK_LOW_LSB,
800 	.d_SRC_WATERMARK_HIGH_LSB = AR6320V2_SRC_WATERMARK_HIGH_LSB,
801 	.d_DST_WATERMARK_LOW_LSB = AR6320V2_DST_WATERMARK_LOW_LSB,
802 	.d_DST_WATERMARK_HIGH_LSB = AR6320V2_DST_WATERMARK_HIGH_LSB,
803 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
804 		AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
805 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
806 		AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
807 	.d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB,
808 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
809 		AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
810 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
811 		AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
812 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
813 		AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
814 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
815 		AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
816 	.d_CE_WRAPPER_DEBUG_OFFSET = AR6320V2_CE_WRAPPER_DEBUG_OFFSET,
817 	.d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB,
818 	.d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB,
819 	.d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK,
820 	.d_CE_DEBUG_OFFSET = AR6320V2_CE_DEBUG_OFFSET,
821 	.d_CE_DEBUG_SEL_MSB = AR6320V2_CE_DEBUG_SEL_MSB,
822 	.d_CE_DEBUG_SEL_LSB = AR6320V2_CE_DEBUG_SEL_LSB,
823 	.d_CE_DEBUG_SEL_MASK = AR6320V2_CE_DEBUG_SEL_MASK,
824 	.d_CE0_BASE_ADDRESS = AR6320V2_CE0_BASE_ADDRESS,
825 	.d_CE1_BASE_ADDRESS = AR6320V2_CE1_BASE_ADDRESS,
826 
827 };
828 #endif
829 #endif
830