xref: /wlan-driver/qca-wifi-host-cmn/hif/src/ar9888def.c (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2013,2016,2018 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #include "qdf_module.h"
20 
21 #if defined(AR9888_HEADERS_DEF)
22 #define AR9888 1
23 
24 #define WLAN_HEADERS 1
25 #include "common_drv.h"
26 #include "AR9888/v2/soc_addrs.h"
27 #include "AR9888/v2/hw/apb_athr_wlan_map.h"
28 #include "AR9888/v2/hw/gpio_athr_wlan_reg.h"
29 #include "AR9888/v2/hw/rtc_soc_reg.h"
30 #include "AR9888/v2/hw/rtc_wlan_reg.h"
31 #include "AR9888/v2/hw/si_reg.h"
32 #include "AR9888/v2/extra/hw/pcie_local_reg.h"
33 
34 #include "AR9888/v2/extra/hw/soc_core_reg.h"
35 #include "AR9888/v2/hw/soc_pcie_reg.h"
36 #include "AR9888/v2/extra/hw/ce_reg_csr.h"
37 #include "AR9888/v2/hw/ce_wrapper_reg_csr.h"
38 
39 #include <AR9888/v2/hw/mac_descriptors/rx_attention.h>
40 #include <AR9888/v2/hw/mac_descriptors/rx_frag_info.h>
41 #include <AR9888/v2/hw/mac_descriptors/rx_msdu_start.h>
42 #include <AR9888/v2/hw/mac_descriptors/rx_msdu_end.h>
43 #include <AR9888/v2/hw/mac_descriptors/rx_mpdu_start.h>
44 #include <AR9888/v2/hw/mac_descriptors/rx_mpdu_end.h>
45 #include <AR9888/v2/hw/mac_descriptors/rx_ppdu_start.h>
46 #include <AR9888/v2/hw/mac_descriptors/rx_ppdu_end.h>
47 
48 /* TBDXXX: Eventually, this Base Address will be defined in HW header files */
49 #define PCIE_LOCAL_BASE_ADDRESS 0x80000
50 
51 #define FW_EVENT_PENDING_ADDRESS (SOC_CORE_BASE_ADDRESS+SCRATCH_3_ADDRESS)
52 #define DRAM_BASE_ADDRESS TARG_DRAM_START
53 
54 /* Backwards compatibility -- TBDXXX */
55 
56 #define MISSING 0
57 
58 #define SYSTEM_SLEEP_OFFSET                     SOC_SYSTEM_SLEEP_OFFSET
59 #define WLAN_SYSTEM_SLEEP_OFFSET                SOC_SYSTEM_SLEEP_OFFSET
60 #define WLAN_RESET_CONTROL_OFFSET               SOC_RESET_CONTROL_OFFSET
61 #define CLOCK_CONTROL_OFFSET                    SOC_CLOCK_CONTROL_OFFSET
62 #define CLOCK_CONTROL_SI0_CLK_MASK              SOC_CLOCK_CONTROL_SI0_CLK_MASK
63 #define RESET_CONTROL_MBOX_RST_MASK             MISSING
64 #define RESET_CONTROL_SI0_RST_MASK              SOC_RESET_CONTROL_SI0_RST_MASK
65 #define GPIO_BASE_ADDRESS                       WLAN_GPIO_BASE_ADDRESS
66 #define GPIO_PIN0_OFFSET                        WLAN_GPIO_PIN0_ADDRESS
67 #define GPIO_PIN1_OFFSET                        WLAN_GPIO_PIN1_ADDRESS
68 #define GPIO_PIN0_CONFIG_MASK                   WLAN_GPIO_PIN0_CONFIG_MASK
69 #define GPIO_PIN1_CONFIG_MASK                   WLAN_GPIO_PIN1_CONFIG_MASK
70 #define SI_BASE_ADDRESS                         WLAN_SI_BASE_ADDRESS
71 #define SCRATCH_BASE_ADDRESS                    SOC_CORE_BASE_ADDRESS
72 #define LOCAL_SCRATCH_OFFSET                    0x18
73 #define CPU_CLOCK_OFFSET                        SOC_CPU_CLOCK_OFFSET
74 #define LPO_CAL_OFFSET                          SOC_LPO_CAL_OFFSET
75 #define GPIO_PIN10_OFFSET                       WLAN_GPIO_PIN10_ADDRESS
76 #define GPIO_PIN11_OFFSET                       WLAN_GPIO_PIN11_ADDRESS
77 #define GPIO_PIN12_OFFSET                       WLAN_GPIO_PIN12_ADDRESS
78 #define GPIO_PIN13_OFFSET                       WLAN_GPIO_PIN13_ADDRESS
79 #define CPU_CLOCK_STANDARD_LSB                  SOC_CPU_CLOCK_STANDARD_LSB
80 #define CPU_CLOCK_STANDARD_MASK                 SOC_CPU_CLOCK_STANDARD_MASK
81 #define LPO_CAL_ENABLE_LSB                      SOC_LPO_CAL_ENABLE_LSB
82 #define LPO_CAL_ENABLE_MASK                     SOC_LPO_CAL_ENABLE_MASK
83 #define ANALOG_INTF_BASE_ADDRESS                WLAN_ANALOG_INTF_BASE_ADDRESS
84 #define MBOX_BASE_ADDRESS                       MISSING
85 #define INT_STATUS_ENABLE_ERROR_LSB             MISSING
86 #define INT_STATUS_ENABLE_ERROR_MASK            MISSING
87 #define INT_STATUS_ENABLE_CPU_LSB               MISSING
88 #define INT_STATUS_ENABLE_CPU_MASK              MISSING
89 #define INT_STATUS_ENABLE_COUNTER_LSB           MISSING
90 #define INT_STATUS_ENABLE_COUNTER_MASK          MISSING
91 #define INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
92 #define INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
93 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
94 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
95 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
96 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
97 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
98 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
99 #define INT_STATUS_ENABLE_ADDRESS               MISSING
100 #define CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
101 #define CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
102 #define HOST_INT_STATUS_ADDRESS                 MISSING
103 #define CPU_INT_STATUS_ADDRESS                  MISSING
104 #define ERROR_INT_STATUS_ADDRESS                MISSING
105 #define ERROR_INT_STATUS_WAKEUP_MASK            MISSING
106 #define ERROR_INT_STATUS_WAKEUP_LSB             MISSING
107 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
108 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
109 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
110 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
111 #define COUNT_DEC_ADDRESS                       MISSING
112 #define HOST_INT_STATUS_CPU_MASK                MISSING
113 #define HOST_INT_STATUS_CPU_LSB                 MISSING
114 #define HOST_INT_STATUS_ERROR_MASK              MISSING
115 #define HOST_INT_STATUS_ERROR_LSB               MISSING
116 #define HOST_INT_STATUS_COUNTER_MASK            MISSING
117 #define HOST_INT_STATUS_COUNTER_LSB             MISSING
118 #define RX_LOOKAHEAD_VALID_ADDRESS              MISSING
119 #define WINDOW_DATA_ADDRESS                     MISSING
120 #define WINDOW_READ_ADDR_ADDRESS                MISSING
121 #define WINDOW_WRITE_ADDR_ADDRESS               MISSING
122 /* MAC descriptor */
123 #define RX_ATTENTION_0_PHY_DATA_TYPE_MASK       MISSING
124 #define RX_MSDU_END_8_LRO_ELIGIBLE_MASK         MISSING
125 #define RX_MSDU_END_8_LRO_ELIGIBLE_LSB          MISSING
126 #define RX_MSDU_END_8_L3_HEADER_PADDING_LSB     MISSING
127 #define RX_MSDU_END_8_L3_HEADER_PADDING_MASK    MISSING
128 #define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_19_RX_ANTENNA_OFFSET >> 2)
129 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK  MISSING
130 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK  MISSING
131 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK  MISSING
132 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK  MISSING
133 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB   MISSING
134 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB   MISSING
135 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB   MISSING
136 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB   MISSING
137 /* GPIO Register */
138 
139 #define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS
140 #define GPIO_PIN0_CONFIG_LSB         WLAN_GPIO_PIN0_CONFIG_LSB
141 #define GPIO_PIN0_PAD_PULL_LSB       WLAN_GPIO_PIN0_PAD_PULL_LSB
142 #define GPIO_PIN0_PAD_PULL_MASK      WLAN_GPIO_PIN0_PAD_PULL_MASK
143 /* CE descriptor */
144 #define CE_SRC_DESC_SIZE_DWORD         2
145 #define CE_DEST_DESC_SIZE_DWORD        2
146 #define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD    0
147 #define CE_SRC_DESC_INFO_OFFSET_DWORD       1
148 #define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD  0
149 #define CE_DEST_DESC_INFO_OFFSET_DWORD      1
150 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK     MISSING
151 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT    MISSING
152 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK   MISSING
153 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT  MISSING
154 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK    MISSING
155 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT   MISSING
156 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK  MISSING
157 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT MISSING
158 #if _BYTE_ORDER == _BIG_ENDIAN
159 #define CE_SRC_DESC_INFO_NBYTES_MASK               0xFFFF0000
160 #define CE_SRC_DESC_INFO_NBYTES_SHIFT              16
161 #define CE_SRC_DESC_INFO_GATHER_MASK               0x00008000
162 #define CE_SRC_DESC_INFO_GATHER_SHIFT              15
163 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK            0x00004000
164 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT           14
165 #define CE_SRC_DESC_INFO_META_DATA_MASK            0x00003FFF
166 #define CE_SRC_DESC_INFO_META_DATA_SHIFT           0
167 #else
168 #define CE_SRC_DESC_INFO_NBYTES_MASK               0x0000FFFF
169 #define CE_SRC_DESC_INFO_NBYTES_SHIFT              0
170 #define CE_SRC_DESC_INFO_GATHER_MASK               0x00010000
171 #define CE_SRC_DESC_INFO_GATHER_SHIFT              16
172 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK            0x00020000
173 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT           17
174 #define CE_SRC_DESC_INFO_META_DATA_MASK            0xFFFC0000
175 #define CE_SRC_DESC_INFO_META_DATA_SHIFT           18
176 #endif
177 #if _BYTE_ORDER == _BIG_ENDIAN
178 #define CE_DEST_DESC_INFO_NBYTES_MASK              0xFFFF0000
179 #define CE_DEST_DESC_INFO_NBYTES_SHIFT             16
180 #define CE_DEST_DESC_INFO_GATHER_MASK              0x00008000
181 #define CE_DEST_DESC_INFO_GATHER_SHIFT             15
182 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK           0x00004000
183 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT          14
184 #define CE_DEST_DESC_INFO_META_DATA_MASK           0x00003FFF
185 #define CE_DEST_DESC_INFO_META_DATA_SHIFT          0
186 #else
187 #define CE_DEST_DESC_INFO_NBYTES_MASK              0x0000FFFF
188 #define CE_DEST_DESC_INFO_NBYTES_SHIFT             0
189 #define CE_DEST_DESC_INFO_GATHER_MASK              0x00010000
190 #define CE_DEST_DESC_INFO_GATHER_SHIFT             16
191 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK           0x00020000
192 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT          17
193 #define CE_DEST_DESC_INFO_META_DATA_MASK           0xFFFC0000
194 #define CE_DEST_DESC_INFO_META_DATA_SHIFT          18
195 #endif
196 
197 #define MY_TARGET_DEF AR9888_TARGETdef
198 #define MY_HOST_DEF AR9888_HOSTdef
199 #define MY_CEREG_DEF AR9888_CE_TARGETdef
200 #define MY_TARGET_BOARD_DATA_SZ AR9888_BOARD_DATA_SZ
201 #define MY_TARGET_BOARD_EXT_DATA_SZ AR9888_BOARD_EXT_DATA_SZ
202 #include "targetdef.h"
203 #include "hostdef.h"
204 qdf_export_symbol(AR9888_CE_TARGETdef);
205 #else
206 #include "common_drv.h"
207 #include "targetdef.h"
208 #include "hostdef.h"
209 struct targetdef_s *AR9888_TARGETdef;
210 struct hostdef_s *AR9888_HOSTdef;
211 #endif /*AR9888_HEADERS_DEF */
212 qdf_export_symbol(AR9888_TARGETdef);
213 qdf_export_symbol(AR9888_HOSTdef);
214