1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2011-2016, 2018 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _AR9888DEF_H_ 20*5113495bSYour Name #define _AR9888DEF_H_ 21*5113495bSYour Name 22*5113495bSYour Name /* Base Addresses */ 23*5113495bSYour Name #define AR9888_RTC_SOC_BASE_ADDRESS 0x00004000 24*5113495bSYour Name #define AR9888_RTC_WMAC_BASE_ADDRESS 0x00005000 25*5113495bSYour Name #define AR9888_MAC_COEX_BASE_ADDRESS 0x00006000 26*5113495bSYour Name #define AR9888_BT_COEX_BASE_ADDRESS 0x00007000 27*5113495bSYour Name #define AR9888_SOC_PCIE_BASE_ADDRESS 0x00008000 28*5113495bSYour Name #define AR9888_SOC_CORE_BASE_ADDRESS 0x00009000 29*5113495bSYour Name #define AR9888_WLAN_UART_BASE_ADDRESS 0x0000c000 30*5113495bSYour Name #define AR9888_WLAN_SI_BASE_ADDRESS 0x00010000 31*5113495bSYour Name #define AR9888_WLAN_GPIO_BASE_ADDRESS 0x00014000 32*5113495bSYour Name #define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 33*5113495bSYour Name #define AR9888_WLAN_MAC_BASE_ADDRESS 0x00020000 34*5113495bSYour Name #define AR9888_EFUSE_BASE_ADDRESS 0x00030000 35*5113495bSYour Name #define AR9888_FPGA_REG_BASE_ADDRESS 0x00039000 36*5113495bSYour Name #define AR9888_WLAN_UART2_BASE_ADDRESS 0x00054c00 37*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 38*5113495bSYour Name #define AR9888_CE_WRAPPER_BASE_ADDRESS 0x00057000 39*5113495bSYour Name #define AR9888_CE0_BASE_ADDRESS 0x00057400 40*5113495bSYour Name #define AR9888_CE1_BASE_ADDRESS 0x00057800 41*5113495bSYour Name #define AR9888_CE2_BASE_ADDRESS 0x00057c00 42*5113495bSYour Name #define AR9888_CE3_BASE_ADDRESS 0x00058000 43*5113495bSYour Name #define AR9888_CE4_BASE_ADDRESS 0x00058400 44*5113495bSYour Name #define AR9888_CE5_BASE_ADDRESS 0x00058800 45*5113495bSYour Name #define AR9888_CE6_BASE_ADDRESS 0x00058c00 46*5113495bSYour Name #define AR9888_CE7_BASE_ADDRESS 0x00059000 47*5113495bSYour Name #define AR9888_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 48*5113495bSYour Name #define AR9888_CE_CTRL1_ADDRESS 0x0010 49*5113495bSYour Name #define AR9888_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 50*5113495bSYour Name #define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 51*5113495bSYour Name #define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00 52*5113495bSYour Name #define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8 53*5113495bSYour Name #define AR9888_CE_CTRL1_DMAX_LENGTH_LSB 0 54*5113495bSYour Name #define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 55*5113495bSYour Name #define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 56*5113495bSYour Name #define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 57*5113495bSYour Name #define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 58*5113495bSYour Name #define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004 59*5113495bSYour Name #define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2 60*5113495bSYour Name #define AR9888_PCIE_SOC_WAKE_RESET 0x00000000 61*5113495bSYour Name #define AR9888_PCIE_SOC_WAKE_ADDRESS 0x0004 62*5113495bSYour Name #define AR9888_PCIE_SOC_WAKE_V_MASK 0x00000001 63*5113495bSYour Name #define AR9888_PCIE_INTR_ENABLE_ADDRESS 0x0008 64*5113495bSYour Name #define AR9888_PCIE_INTR_CLR_ADDRESS 0x0014 65*5113495bSYour Name #define AR9888_PCIE_INTR_FIRMWARE_MASK 0x00000400 66*5113495bSYour Name #define AR9888_PCIE_INTR_CE0_MASK 0x00000800 67*5113495bSYour Name #define AR9888_PCIE_INTR_CE_MASK_ALL 0x0007f800 68*5113495bSYour Name #define AR9888_PCIE_INTR_CAUSE_ADDRESS 0x000c 69*5113495bSYour Name #define AR9888_MUX_ID_MASK 0x0000 70*5113495bSYour Name #define AR9888_TRANSACTION_ID_MASK 0x3fff 71*5113495bSYour Name #define AR9888_PCIE_LOCAL_BASE_ADDRESS 0x80000 72*5113495bSYour Name #define AR9888_SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 73*5113495bSYour Name #define AR9888_PCIE_INTR_CE_MASK(n) (AR9888_PCIE_INTR_CE0_MASK << (n)) 74*5113495bSYour Name #endif 75*5113495bSYour Name #define AR9888_DBI_BASE_ADDRESS 0x00060000 76*5113495bSYour Name #define AR9888_SCRATCH_3_ADDRESS 0x0030 77*5113495bSYour Name #define AR9888_TARG_DRAM_START 0x00400000 78*5113495bSYour Name #define AR9888_SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 79*5113495bSYour Name #define AR9888_SOC_RESET_CONTROL_OFFSET 0x00000000 80*5113495bSYour Name #define AR9888_SOC_CLOCK_CONTROL_OFFSET 0x00000028 81*5113495bSYour Name #define AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 82*5113495bSYour Name #define AR9888_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 83*5113495bSYour Name #define AR9888_WLAN_GPIO_BASE_ADDRESS 0x00014000 84*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN0_ADDRESS 0x00000028 85*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN1_ADDRESS 0x0000002c 86*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 87*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 88*5113495bSYour Name #define AR9888_WLAN_SI_BASE_ADDRESS 0x00010000 89*5113495bSYour Name #define AR9888_SOC_CPU_CLOCK_OFFSET 0x00000020 90*5113495bSYour Name #define AR9888_SOC_LPO_CAL_OFFSET 0x000000e0 91*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN10_ADDRESS 0x00000050 92*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN11_ADDRESS 0x00000054 93*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN12_ADDRESS 0x00000058 94*5113495bSYour Name #define AR9888_WLAN_GPIO_PIN13_ADDRESS 0x0000005c 95*5113495bSYour Name #define AR9888_SOC_CPU_CLOCK_STANDARD_LSB 0 96*5113495bSYour Name #define AR9888_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 97*5113495bSYour Name #define AR9888_SOC_LPO_CAL_ENABLE_LSB 20 98*5113495bSYour Name #define AR9888_SOC_LPO_CAL_ENABLE_MASK 0x00100000 99*5113495bSYour Name #define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 100*5113495bSYour Name 101*5113495bSYour Name #define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 102*5113495bSYour Name #define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 103*5113495bSYour Name #define AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 104*5113495bSYour Name #define AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 105*5113495bSYour Name #define AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB 18 106*5113495bSYour Name #define AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 107*5113495bSYour Name #define AR9888_SI_CONFIG_I2C_LSB 16 108*5113495bSYour Name #define AR9888_SI_CONFIG_I2C_MASK 0x00010000 109*5113495bSYour Name #define AR9888_SI_CONFIG_POS_SAMPLE_LSB 7 110*5113495bSYour Name #define AR9888_SI_CONFIG_POS_SAMPLE_MASK 0x00000080 111*5113495bSYour Name #define AR9888_SI_CONFIG_INACTIVE_CLK_LSB 4 112*5113495bSYour Name #define AR9888_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 113*5113495bSYour Name #define AR9888_SI_CONFIG_INACTIVE_DATA_LSB 5 114*5113495bSYour Name #define AR9888_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 115*5113495bSYour Name #define AR9888_SI_CONFIG_DIVIDER_LSB 0 116*5113495bSYour Name #define AR9888_SI_CONFIG_DIVIDER_MASK 0x0000000f 117*5113495bSYour Name #define AR9888_SI_CONFIG_OFFSET 0x00000000 118*5113495bSYour Name #define AR9888_SI_TX_DATA0_OFFSET 0x00000008 119*5113495bSYour Name #define AR9888_SI_TX_DATA1_OFFSET 0x0000000c 120*5113495bSYour Name #define AR9888_SI_RX_DATA0_OFFSET 0x00000010 121*5113495bSYour Name #define AR9888_SI_RX_DATA1_OFFSET 0x00000014 122*5113495bSYour Name #define AR9888_SI_CS_OFFSET 0x00000004 123*5113495bSYour Name #define AR9888_SI_CS_DONE_ERR_MASK 0x00000400 124*5113495bSYour Name #define AR9888_SI_CS_DONE_INT_MASK 0x00000200 125*5113495bSYour Name #define AR9888_SI_CS_START_LSB 8 126*5113495bSYour Name #define AR9888_SI_CS_START_MASK 0x00000100 127*5113495bSYour Name #define AR9888_SI_CS_RX_CNT_LSB 4 128*5113495bSYour Name #define AR9888_SI_CS_RX_CNT_MASK 0x000000f0 129*5113495bSYour Name #define AR9888_SI_CS_TX_CNT_LSB 0 130*5113495bSYour Name #define AR9888_SI_CS_TX_CNT_MASK 0x0000000f 131*5113495bSYour Name #define AR9888_CE_COUNT 8 132*5113495bSYour Name #define AR9888_SR_WR_INDEX_ADDRESS 0x003c 133*5113495bSYour Name #define AR9888_DST_WATERMARK_ADDRESS 0x0050 134*5113495bSYour Name #define AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB 14 135*5113495bSYour Name #define AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000 136*5113495bSYour Name #define AR9888_RX_MPDU_START_0_SEQ_NUM_LSB 16 137*5113495bSYour Name #define AR9888_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000 138*5113495bSYour Name #define AR9888_RX_MPDU_START_2_PN_47_32_LSB 0 139*5113495bSYour Name #define AR9888_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff 140*5113495bSYour Name #define AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK 0x000000ff 141*5113495bSYour Name #define AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB 0 142*5113495bSYour Name #define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16 143*5113495bSYour Name #define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000 144*5113495bSYour Name #define AR9888_RX_MSDU_END_4_LAST_MSDU_LSB 15 145*5113495bSYour Name #define AR9888_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000 146*5113495bSYour Name #define AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB 2 147*5113495bSYour Name #define AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004 148*5113495bSYour Name #define AR9888_RX_ATTENTION_0_FRAGMENT_LSB 13 149*5113495bSYour Name #define AR9888_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000 150*5113495bSYour Name #define AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000 151*5113495bSYour Name #define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16 152*5113495bSYour Name #define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000 153*5113495bSYour Name #define AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB 0 154*5113495bSYour Name #define AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff 155*5113495bSYour Name #define AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 156*5113495bSYour Name #define AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB 8 157*5113495bSYour Name #define AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 158*5113495bSYour Name #define AR9888_RX_MPDU_START_0_ENCRYPTED_LSB 13 159*5113495bSYour Name #define AR9888_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000 160*5113495bSYour Name #define AR9888_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400 161*5113495bSYour Name #define AR9888_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000 162*5113495bSYour Name #define AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 163*5113495bSYour Name #define AR9888_DST_WR_INDEX_ADDRESS 0x0040 164*5113495bSYour Name #define AR9888_SRC_WATERMARK_ADDRESS 0x004c 165*5113495bSYour Name #define AR9888_SRC_WATERMARK_LOW_MASK 0xffff0000 166*5113495bSYour Name #define AR9888_SRC_WATERMARK_HIGH_MASK 0x0000ffff 167*5113495bSYour Name #define AR9888_DST_WATERMARK_LOW_MASK 0xffff0000 168*5113495bSYour Name #define AR9888_DST_WATERMARK_HIGH_MASK 0x0000ffff 169*5113495bSYour Name #define AR9888_CURRENT_SRRI_ADDRESS 0x0044 170*5113495bSYour Name #define AR9888_CURRENT_DRRI_ADDRESS 0x0048 171*5113495bSYour Name #define AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 172*5113495bSYour Name #define AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 173*5113495bSYour Name #define AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 174*5113495bSYour Name #define AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 175*5113495bSYour Name #define AR9888_HOST_IS_ADDRESS 0x0030 176*5113495bSYour Name #define AR9888_HOST_IS_COPY_COMPLETE_MASK 0x00000001 177*5113495bSYour Name #define AR9888_HOST_IE_ADDRESS 0x002c 178*5113495bSYour Name #define AR9888_HOST_IE_COPY_COMPLETE_MASK 0x00000001 179*5113495bSYour Name #define AR9888_SR_BA_ADDRESS 0x0000 180*5113495bSYour Name #define AR9888_SR_SIZE_ADDRESS 0x0004 181*5113495bSYour Name #define AR9888_DR_BA_ADDRESS 0x0008 182*5113495bSYour Name #define AR9888_DR_SIZE_ADDRESS 0x000c 183*5113495bSYour Name #define AR9888_MISC_IE_ADDRESS 0x0034 184*5113495bSYour Name #define AR9888_MISC_IS_AXI_ERR_MASK 0x00000400 185*5113495bSYour Name #define AR9888_MISC_IS_DST_ADDR_ERR_MASK 0x00000200 186*5113495bSYour Name #define AR9888_MISC_IS_SRC_LEN_ERR_MASK 0x00000100 187*5113495bSYour Name #define AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 188*5113495bSYour Name #define AR9888_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 189*5113495bSYour Name #define AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 190*5113495bSYour Name #define AR9888_SRC_WATERMARK_LOW_LSB 16 191*5113495bSYour Name #define AR9888_SRC_WATERMARK_HIGH_LSB 0 192*5113495bSYour Name #define AR9888_DST_WATERMARK_LOW_LSB 16 193*5113495bSYour Name #define AR9888_DST_WATERMARK_HIGH_LSB 0 194*5113495bSYour Name #define AR9888_SOC_GLOBAL_RESET_ADDRESS 0x0008 195*5113495bSYour Name #define AR9888_RTC_STATE_ADDRESS 0x0000 196*5113495bSYour Name #define AR9888_RTC_STATE_COLD_RESET_MASK 0x00000400 197*5113495bSYour Name 198*5113495bSYour Name #define AR9888_RTC_STATE_V_MASK 0x00000007 199*5113495bSYour Name #define AR9888_RTC_STATE_V_LSB 0 200*5113495bSYour Name #define AR9888_RTC_STATE_V_ON 3 201*5113495bSYour Name #define AR9888_FW_IND_EVENT_PENDING 1 202*5113495bSYour Name #define AR9888_FW_IND_INITIALIZED 2 203*5113495bSYour Name #define AR9888_CPU_INTR_ADDRESS 0x0010 204*5113495bSYour Name #define AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 205*5113495bSYour Name #define AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 206*5113495bSYour Name #define AR9888_SOC_LF_TIMER_STATUS0_ADDRESS 0x00000054 207*5113495bSYour Name #define AR9888_SOC_RESET_CONTROL_ADDRESS 0x00000000 208*5113495bSYour Name #define AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 209*5113495bSYour Name #define AR9888_CORE_CTRL_ADDRESS 0x0000 210*5113495bSYour Name #define AR9888_CORE_CTRL_CPU_INTR_MASK 0x00002000 211*5113495bSYour Name #define AR9888_LOCAL_SCRATCH_OFFSET 0x18 212*5113495bSYour Name #define AR9888_CLOCK_GPIO_OFFSET 0xffffffff 213*5113495bSYour Name #define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 214*5113495bSYour Name #define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 215*5113495bSYour Name 216*5113495bSYour Name #define AR9888_FW_EVENT_PENDING_ADDRESS \ 217*5113495bSYour Name (AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS) 218*5113495bSYour Name #define AR9888_DRAM_BASE_ADDRESS AR9888_TARG_DRAM_START 219*5113495bSYour Name #define AR9888_FW_INDICATOR_ADDRESS \ 220*5113495bSYour Name (AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS) 221*5113495bSYour Name #define AR9888_SYSTEM_SLEEP_OFFSET AR9888_SOC_SYSTEM_SLEEP_OFFSET 222*5113495bSYour Name #define AR9888_WLAN_SYSTEM_SLEEP_OFFSET AR9888_SOC_SYSTEM_SLEEP_OFFSET 223*5113495bSYour Name #define AR9888_WLAN_RESET_CONTROL_OFFSET AR9888_SOC_RESET_CONTROL_OFFSET 224*5113495bSYour Name #define AR9888_CLOCK_CONTROL_OFFSET AR9888_SOC_CLOCK_CONTROL_OFFSET 225*5113495bSYour Name #define AR9888_CLOCK_CONTROL_SI0_CLK_MASK AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK 226*5113495bSYour Name #define AR9888_RESET_CONTROL_MBOX_RST_MASK MISSING 227*5113495bSYour Name #define AR9888_RESET_CONTROL_SI0_RST_MASK AR9888_SOC_RESET_CONTROL_SI0_RST_MASK 228*5113495bSYour Name #define AR9888_GPIO_BASE_ADDRESS AR9888_WLAN_GPIO_BASE_ADDRESS 229*5113495bSYour Name #define AR9888_GPIO_PIN0_OFFSET AR9888_WLAN_GPIO_PIN0_ADDRESS 230*5113495bSYour Name #define AR9888_GPIO_PIN1_OFFSET AR9888_WLAN_GPIO_PIN1_ADDRESS 231*5113495bSYour Name #define AR9888_GPIO_PIN0_CONFIG_MASK AR9888_WLAN_GPIO_PIN0_CONFIG_MASK 232*5113495bSYour Name #define AR9888_GPIO_PIN1_CONFIG_MASK AR9888_WLAN_GPIO_PIN1_CONFIG_MASK 233*5113495bSYour Name #define AR9888_SI_BASE_ADDRESS AR9888_WLAN_SI_BASE_ADDRESS 234*5113495bSYour Name #define AR9888_SCRATCH_BASE_ADDRESS AR9888_SOC_CORE_BASE_ADDRESS 235*5113495bSYour Name #define AR9888_CPU_CLOCK_OFFSET AR9888_SOC_CPU_CLOCK_OFFSET 236*5113495bSYour Name #define AR9888_LPO_CAL_OFFSET AR9888_SOC_LPO_CAL_OFFSET 237*5113495bSYour Name #define AR9888_GPIO_PIN10_OFFSET AR9888_WLAN_GPIO_PIN10_ADDRESS 238*5113495bSYour Name #define AR9888_GPIO_PIN11_OFFSET AR9888_WLAN_GPIO_PIN11_ADDRESS 239*5113495bSYour Name #define AR9888_GPIO_PIN12_OFFSET AR9888_WLAN_GPIO_PIN12_ADDRESS 240*5113495bSYour Name #define AR9888_GPIO_PIN13_OFFSET AR9888_WLAN_GPIO_PIN13_ADDRESS 241*5113495bSYour Name #define AR9888_CPU_CLOCK_STANDARD_LSB AR9888_SOC_CPU_CLOCK_STANDARD_LSB 242*5113495bSYour Name #define AR9888_CPU_CLOCK_STANDARD_MASK AR9888_SOC_CPU_CLOCK_STANDARD_MASK 243*5113495bSYour Name #define AR9888_LPO_CAL_ENABLE_LSB AR9888_SOC_LPO_CAL_ENABLE_LSB 244*5113495bSYour Name #define AR9888_LPO_CAL_ENABLE_MASK AR9888_SOC_LPO_CAL_ENABLE_MASK 245*5113495bSYour Name #define AR9888_ANALOG_INTF_BASE_ADDRESS AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS 246*5113495bSYour Name #define AR9888_MBOX_BASE_ADDRESS MISSING 247*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_ERROR_LSB MISSING 248*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_ERROR_MASK MISSING 249*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_CPU_LSB MISSING 250*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_CPU_MASK MISSING 251*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_COUNTER_LSB MISSING 252*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_COUNTER_MASK MISSING 253*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 254*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 255*5113495bSYour Name #define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 256*5113495bSYour Name #define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 257*5113495bSYour Name #define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 258*5113495bSYour Name #define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 259*5113495bSYour Name #define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 260*5113495bSYour Name #define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 261*5113495bSYour Name #define AR9888_INT_STATUS_ENABLE_ADDRESS MISSING 262*5113495bSYour Name #define AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 263*5113495bSYour Name #define AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 264*5113495bSYour Name #define AR9888_HOST_INT_STATUS_ADDRESS MISSING 265*5113495bSYour Name #define AR9888_CPU_INT_STATUS_ADDRESS MISSING 266*5113495bSYour Name #define AR9888_ERROR_INT_STATUS_ADDRESS MISSING 267*5113495bSYour Name #define AR9888_ERROR_INT_STATUS_WAKEUP_MASK MISSING 268*5113495bSYour Name #define AR9888_ERROR_INT_STATUS_WAKEUP_LSB MISSING 269*5113495bSYour Name #define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 270*5113495bSYour Name #define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 271*5113495bSYour Name #define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 272*5113495bSYour Name #define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 273*5113495bSYour Name #define AR9888_COUNT_DEC_ADDRESS MISSING 274*5113495bSYour Name #define AR9888_HOST_INT_STATUS_CPU_MASK MISSING 275*5113495bSYour Name #define AR9888_HOST_INT_STATUS_CPU_LSB MISSING 276*5113495bSYour Name #define AR9888_HOST_INT_STATUS_ERROR_MASK MISSING 277*5113495bSYour Name #define AR9888_HOST_INT_STATUS_ERROR_LSB MISSING 278*5113495bSYour Name #define AR9888_HOST_INT_STATUS_COUNTER_MASK MISSING 279*5113495bSYour Name #define AR9888_HOST_INT_STATUS_COUNTER_LSB MISSING 280*5113495bSYour Name #define AR9888_RX_LOOKAHEAD_VALID_ADDRESS MISSING 281*5113495bSYour Name #define AR9888_WINDOW_DATA_ADDRESS MISSING 282*5113495bSYour Name #define AR9888_WINDOW_READ_ADDR_ADDRESS MISSING 283*5113495bSYour Name #define AR9888_WINDOW_WRITE_ADDR_ADDRESS MISSING 284*5113495bSYour Name #define AR9888_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f 285*5113495bSYour Name #define AR9888_HOST_INT_STATUS_MBOX_DATA_LSB 0 286*5113495bSYour Name 287*5113495bSYour Name struct targetdef_s ar9888_targetdef = { 288*5113495bSYour Name .d_RTC_SOC_BASE_ADDRESS = AR9888_RTC_SOC_BASE_ADDRESS, 289*5113495bSYour Name .d_RTC_WMAC_BASE_ADDRESS = AR9888_RTC_WMAC_BASE_ADDRESS, 290*5113495bSYour Name .d_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET, 291*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET, 292*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = 293*5113495bSYour Name AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB, 294*5113495bSYour Name .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = 295*5113495bSYour Name AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK, 296*5113495bSYour Name .d_CLOCK_CONTROL_OFFSET = AR9888_CLOCK_CONTROL_OFFSET, 297*5113495bSYour Name .d_CLOCK_CONTROL_SI0_CLK_MASK = AR9888_CLOCK_CONTROL_SI0_CLK_MASK, 298*5113495bSYour Name .d_RESET_CONTROL_OFFSET = AR9888_SOC_RESET_CONTROL_OFFSET, 299*5113495bSYour Name .d_RESET_CONTROL_MBOX_RST_MASK = AR9888_RESET_CONTROL_MBOX_RST_MASK, 300*5113495bSYour Name .d_RESET_CONTROL_SI0_RST_MASK = AR9888_RESET_CONTROL_SI0_RST_MASK, 301*5113495bSYour Name .d_WLAN_RESET_CONTROL_OFFSET = AR9888_WLAN_RESET_CONTROL_OFFSET, 302*5113495bSYour Name .d_WLAN_RESET_CONTROL_COLD_RST_MASK = 303*5113495bSYour Name AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK, 304*5113495bSYour Name .d_WLAN_RESET_CONTROL_WARM_RST_MASK = 305*5113495bSYour Name AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK, 306*5113495bSYour Name .d_GPIO_BASE_ADDRESS = AR9888_GPIO_BASE_ADDRESS, 307*5113495bSYour Name .d_GPIO_PIN0_OFFSET = AR9888_GPIO_PIN0_OFFSET, 308*5113495bSYour Name .d_GPIO_PIN1_OFFSET = AR9888_GPIO_PIN1_OFFSET, 309*5113495bSYour Name .d_GPIO_PIN0_CONFIG_MASK = AR9888_GPIO_PIN0_CONFIG_MASK, 310*5113495bSYour Name .d_GPIO_PIN1_CONFIG_MASK = AR9888_GPIO_PIN1_CONFIG_MASK, 311*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB, 312*5113495bSYour Name .d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK, 313*5113495bSYour Name .d_SI_CONFIG_I2C_LSB = AR9888_SI_CONFIG_I2C_LSB, 314*5113495bSYour Name .d_SI_CONFIG_I2C_MASK = AR9888_SI_CONFIG_I2C_MASK, 315*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_LSB = AR9888_SI_CONFIG_POS_SAMPLE_LSB, 316*5113495bSYour Name .d_SI_CONFIG_POS_SAMPLE_MASK = AR9888_SI_CONFIG_POS_SAMPLE_MASK, 317*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_LSB = AR9888_SI_CONFIG_INACTIVE_CLK_LSB, 318*5113495bSYour Name .d_SI_CONFIG_INACTIVE_CLK_MASK = AR9888_SI_CONFIG_INACTIVE_CLK_MASK, 319*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_LSB = AR9888_SI_CONFIG_INACTIVE_DATA_LSB, 320*5113495bSYour Name .d_SI_CONFIG_INACTIVE_DATA_MASK = AR9888_SI_CONFIG_INACTIVE_DATA_MASK, 321*5113495bSYour Name .d_SI_CONFIG_DIVIDER_LSB = AR9888_SI_CONFIG_DIVIDER_LSB, 322*5113495bSYour Name .d_SI_CONFIG_DIVIDER_MASK = AR9888_SI_CONFIG_DIVIDER_MASK, 323*5113495bSYour Name .d_SI_BASE_ADDRESS = AR9888_SI_BASE_ADDRESS, 324*5113495bSYour Name .d_SI_CONFIG_OFFSET = AR9888_SI_CONFIG_OFFSET, 325*5113495bSYour Name .d_SI_TX_DATA0_OFFSET = AR9888_SI_TX_DATA0_OFFSET, 326*5113495bSYour Name .d_SI_TX_DATA1_OFFSET = AR9888_SI_TX_DATA1_OFFSET, 327*5113495bSYour Name .d_SI_RX_DATA0_OFFSET = AR9888_SI_RX_DATA0_OFFSET, 328*5113495bSYour Name .d_SI_RX_DATA1_OFFSET = AR9888_SI_RX_DATA1_OFFSET, 329*5113495bSYour Name .d_SI_CS_OFFSET = AR9888_SI_CS_OFFSET, 330*5113495bSYour Name .d_SI_CS_DONE_ERR_MASK = AR9888_SI_CS_DONE_ERR_MASK, 331*5113495bSYour Name .d_SI_CS_DONE_INT_MASK = AR9888_SI_CS_DONE_INT_MASK, 332*5113495bSYour Name .d_SI_CS_START_LSB = AR9888_SI_CS_START_LSB, 333*5113495bSYour Name .d_SI_CS_START_MASK = AR9888_SI_CS_START_MASK, 334*5113495bSYour Name .d_SI_CS_RX_CNT_LSB = AR9888_SI_CS_RX_CNT_LSB, 335*5113495bSYour Name .d_SI_CS_RX_CNT_MASK = AR9888_SI_CS_RX_CNT_MASK, 336*5113495bSYour Name .d_SI_CS_TX_CNT_LSB = AR9888_SI_CS_TX_CNT_LSB, 337*5113495bSYour Name .d_SI_CS_TX_CNT_MASK = AR9888_SI_CS_TX_CNT_MASK, 338*5113495bSYour Name .d_BOARD_DATA_SZ = AR9888_BOARD_DATA_SZ, 339*5113495bSYour Name .d_BOARD_EXT_DATA_SZ = AR9888_BOARD_EXT_DATA_SZ, 340*5113495bSYour Name .d_MBOX_BASE_ADDRESS = AR9888_MBOX_BASE_ADDRESS, 341*5113495bSYour Name .d_LOCAL_SCRATCH_OFFSET = AR9888_LOCAL_SCRATCH_OFFSET, 342*5113495bSYour Name .d_CPU_CLOCK_OFFSET = AR9888_CPU_CLOCK_OFFSET, 343*5113495bSYour Name .d_LPO_CAL_OFFSET = AR9888_LPO_CAL_OFFSET, 344*5113495bSYour Name .d_GPIO_PIN10_OFFSET = AR9888_GPIO_PIN10_OFFSET, 345*5113495bSYour Name .d_GPIO_PIN11_OFFSET = AR9888_GPIO_PIN11_OFFSET, 346*5113495bSYour Name .d_GPIO_PIN12_OFFSET = AR9888_GPIO_PIN12_OFFSET, 347*5113495bSYour Name .d_GPIO_PIN13_OFFSET = AR9888_GPIO_PIN13_OFFSET, 348*5113495bSYour Name .d_CLOCK_GPIO_OFFSET = AR9888_CLOCK_GPIO_OFFSET, 349*5113495bSYour Name .d_CPU_CLOCK_STANDARD_LSB = AR9888_CPU_CLOCK_STANDARD_LSB, 350*5113495bSYour Name .d_CPU_CLOCK_STANDARD_MASK = AR9888_CPU_CLOCK_STANDARD_MASK, 351*5113495bSYour Name .d_LPO_CAL_ENABLE_LSB = AR9888_LPO_CAL_ENABLE_LSB, 352*5113495bSYour Name .d_LPO_CAL_ENABLE_MASK = AR9888_LPO_CAL_ENABLE_MASK, 353*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB, 354*5113495bSYour Name .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = 355*5113495bSYour Name AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK, 356*5113495bSYour Name .d_ANALOG_INTF_BASE_ADDRESS = AR9888_ANALOG_INTF_BASE_ADDRESS, 357*5113495bSYour Name .d_WLAN_MAC_BASE_ADDRESS = AR9888_WLAN_MAC_BASE_ADDRESS, 358*5113495bSYour Name .d_FW_INDICATOR_ADDRESS = AR9888_FW_INDICATOR_ADDRESS, 359*5113495bSYour Name .d_DRAM_BASE_ADDRESS = AR9888_DRAM_BASE_ADDRESS, 360*5113495bSYour Name .d_SOC_CORE_BASE_ADDRESS = AR9888_SOC_CORE_BASE_ADDRESS, 361*5113495bSYour Name .d_CORE_CTRL_ADDRESS = AR9888_CORE_CTRL_ADDRESS, 362*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 363*5113495bSYour Name .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, 364*5113495bSYour Name .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, 365*5113495bSYour Name #endif 366*5113495bSYour Name .d_CORE_CTRL_CPU_INTR_MASK = AR9888_CORE_CTRL_CPU_INTR_MASK, 367*5113495bSYour Name .d_SR_WR_INDEX_ADDRESS = AR9888_SR_WR_INDEX_ADDRESS, 368*5113495bSYour Name .d_DST_WATERMARK_ADDRESS = AR9888_DST_WATERMARK_ADDRESS, 369*5113495bSYour Name /* htt_rx.c */ 370*5113495bSYour Name .d_RX_MSDU_END_4_FIRST_MSDU_MASK = 371*5113495bSYour Name AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK, 372*5113495bSYour Name .d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB, 373*5113495bSYour Name .d_RX_MPDU_START_0_SEQ_NUM_MASK = AR9888_RX_MPDU_START_0_SEQ_NUM_MASK, 374*5113495bSYour Name .d_RX_MPDU_START_0_SEQ_NUM_LSB = AR9888_RX_MPDU_START_0_SEQ_NUM_LSB, 375*5113495bSYour Name .d_RX_MPDU_START_2_PN_47_32_LSB = AR9888_RX_MPDU_START_2_PN_47_32_LSB, 376*5113495bSYour Name .d_RX_MPDU_START_2_PN_47_32_MASK = 377*5113495bSYour Name AR9888_RX_MPDU_START_2_PN_47_32_MASK, 378*5113495bSYour Name .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK = 379*5113495bSYour Name AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK, 380*5113495bSYour Name .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB = 381*5113495bSYour Name AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB, 382*5113495bSYour Name .d_RX_MSDU_END_1_KEY_ID_OCT_MASK = 383*5113495bSYour Name AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK, 384*5113495bSYour Name .d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB, 385*5113495bSYour Name .d_RX_MSDU_END_4_LAST_MSDU_MASK = AR9888_RX_MSDU_END_4_LAST_MSDU_MASK, 386*5113495bSYour Name .d_RX_MSDU_END_4_LAST_MSDU_LSB = AR9888_RX_MSDU_END_4_LAST_MSDU_LSB, 387*5113495bSYour Name .d_RX_ATTENTION_0_MCAST_BCAST_MASK = 388*5113495bSYour Name AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK, 389*5113495bSYour Name .d_RX_ATTENTION_0_MCAST_BCAST_LSB = 390*5113495bSYour Name AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB, 391*5113495bSYour Name .d_RX_ATTENTION_0_FRAGMENT_MASK = AR9888_RX_ATTENTION_0_FRAGMENT_MASK, 392*5113495bSYour Name .d_RX_ATTENTION_0_FRAGMENT_LSB = AR9888_RX_ATTENTION_0_FRAGMENT_LSB, 393*5113495bSYour Name .d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK = 394*5113495bSYour Name AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK, 395*5113495bSYour Name .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK = 396*5113495bSYour Name AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK, 397*5113495bSYour Name .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB = 398*5113495bSYour Name AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB, 399*5113495bSYour Name .d_RX_MSDU_START_0_MSDU_LENGTH_MASK = 400*5113495bSYour Name AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK, 401*5113495bSYour Name .d_RX_MSDU_START_0_MSDU_LENGTH_LSB = 402*5113495bSYour Name AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB, 403*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET = 404*5113495bSYour Name AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET, 405*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_MASK = 406*5113495bSYour Name AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK, 407*5113495bSYour Name .d_RX_MSDU_START_2_DECAP_FORMAT_LSB = 408*5113495bSYour Name AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB, 409*5113495bSYour Name .d_RX_MPDU_START_0_ENCRYPTED_MASK = 410*5113495bSYour Name AR9888_RX_MPDU_START_0_ENCRYPTED_MASK, 411*5113495bSYour Name .d_RX_MPDU_START_0_ENCRYPTED_LSB = 412*5113495bSYour Name AR9888_RX_MPDU_START_0_ENCRYPTED_LSB, 413*5113495bSYour Name .d_RX_ATTENTION_0_MORE_DATA_MASK = 414*5113495bSYour Name AR9888_RX_ATTENTION_0_MORE_DATA_MASK, 415*5113495bSYour Name .d_RX_ATTENTION_0_MSDU_DONE_MASK = 416*5113495bSYour Name AR9888_RX_ATTENTION_0_MSDU_DONE_MASK, 417*5113495bSYour Name .d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK = 418*5113495bSYour Name AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK, 419*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 420*5113495bSYour Name .d_CE_COUNT = AR9888_CE_COUNT, 421*5113495bSYour Name .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, 422*5113495bSYour Name .d_PCIE_INTR_ENABLE_ADDRESS = AR9888_PCIE_INTR_ENABLE_ADDRESS, 423*5113495bSYour Name .d_PCIE_INTR_CLR_ADDRESS = AR9888_PCIE_INTR_CLR_ADDRESS, 424*5113495bSYour Name .d_PCIE_INTR_FIRMWARE_MASK = AR9888_PCIE_INTR_FIRMWARE_MASK, 425*5113495bSYour Name .d_PCIE_INTR_CE_MASK_ALL = AR9888_PCIE_INTR_CE_MASK_ALL, 426*5113495bSYour Name .d_PCIE_INTR_CAUSE_ADDRESS = AR9888_PCIE_INTR_CAUSE_ADDRESS, 427*5113495bSYour Name .d_SOC_RESET_CONTROL_ADDRESS = AR9888_SOC_RESET_CONTROL_ADDRESS, 428*5113495bSYour Name .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = 429*5113495bSYour Name AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK, 430*5113495bSYour Name .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB = 431*5113495bSYour Name AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB, 432*5113495bSYour Name .d_SOC_RESET_CONTROL_CE_RST_MASK = 433*5113495bSYour Name AR9888_SOC_RESET_CONTROL_CE_RST_MASK, 434*5113495bSYour Name #endif 435*5113495bSYour Name .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK = 436*5113495bSYour Name AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK, 437*5113495bSYour Name .d_CPU_INTR_ADDRESS = AR9888_CPU_INTR_ADDRESS, 438*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ADDRESS = 439*5113495bSYour Name AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS, 440*5113495bSYour Name .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK = 441*5113495bSYour Name AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK, 442*5113495bSYour Name .d_SOC_LF_TIMER_STATUS0_ADDRESS = 443*5113495bSYour Name AR9888_SOC_LF_TIMER_STATUS0_ADDRESS, 444*5113495bSYour Name }; 445*5113495bSYour Name 446*5113495bSYour Name struct hostdef_s ar9888_hostdef = { 447*5113495bSYour Name .d_INT_STATUS_ENABLE_ERROR_LSB = AR9888_INT_STATUS_ENABLE_ERROR_LSB, 448*5113495bSYour Name .d_INT_STATUS_ENABLE_ERROR_MASK = AR9888_INT_STATUS_ENABLE_ERROR_MASK, 449*5113495bSYour Name .d_INT_STATUS_ENABLE_CPU_LSB = AR9888_INT_STATUS_ENABLE_CPU_LSB, 450*5113495bSYour Name .d_INT_STATUS_ENABLE_CPU_MASK = AR9888_INT_STATUS_ENABLE_CPU_MASK, 451*5113495bSYour Name .d_INT_STATUS_ENABLE_COUNTER_LSB = 452*5113495bSYour Name AR9888_INT_STATUS_ENABLE_COUNTER_LSB, 453*5113495bSYour Name .d_INT_STATUS_ENABLE_COUNTER_MASK = 454*5113495bSYour Name AR9888_INT_STATUS_ENABLE_COUNTER_MASK, 455*5113495bSYour Name .d_INT_STATUS_ENABLE_MBOX_DATA_LSB = 456*5113495bSYour Name AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB, 457*5113495bSYour Name .d_INT_STATUS_ENABLE_MBOX_DATA_MASK = 458*5113495bSYour Name AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK, 459*5113495bSYour Name .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB = 460*5113495bSYour Name AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB, 461*5113495bSYour Name .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK = 462*5113495bSYour Name AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 463*5113495bSYour Name .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB = 464*5113495bSYour Name AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB, 465*5113495bSYour Name .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK = 466*5113495bSYour Name AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 467*5113495bSYour Name .d_COUNTER_INT_STATUS_ENABLE_BIT_LSB = 468*5113495bSYour Name AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB, 469*5113495bSYour Name .d_COUNTER_INT_STATUS_ENABLE_BIT_MASK = 470*5113495bSYour Name AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK, 471*5113495bSYour Name .d_INT_STATUS_ENABLE_ADDRESS = AR9888_INT_STATUS_ENABLE_ADDRESS, 472*5113495bSYour Name .d_CPU_INT_STATUS_ENABLE_BIT_LSB = 473*5113495bSYour Name AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB, 474*5113495bSYour Name .d_CPU_INT_STATUS_ENABLE_BIT_MASK = 475*5113495bSYour Name AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK, 476*5113495bSYour Name .d_HOST_INT_STATUS_ADDRESS = AR9888_HOST_INT_STATUS_ADDRESS, 477*5113495bSYour Name .d_CPU_INT_STATUS_ADDRESS = AR9888_CPU_INT_STATUS_ADDRESS, 478*5113495bSYour Name .d_ERROR_INT_STATUS_ADDRESS = AR9888_ERROR_INT_STATUS_ADDRESS, 479*5113495bSYour Name .d_ERROR_INT_STATUS_WAKEUP_MASK = AR9888_ERROR_INT_STATUS_WAKEUP_MASK, 480*5113495bSYour Name .d_ERROR_INT_STATUS_WAKEUP_LSB = AR9888_ERROR_INT_STATUS_WAKEUP_LSB, 481*5113495bSYour Name .d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK = 482*5113495bSYour Name AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK, 483*5113495bSYour Name .d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB = 484*5113495bSYour Name AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB, 485*5113495bSYour Name .d_ERROR_INT_STATUS_TX_OVERFLOW_MASK = 486*5113495bSYour Name AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK, 487*5113495bSYour Name .d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = 488*5113495bSYour Name AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB, 489*5113495bSYour Name .d_COUNT_DEC_ADDRESS = AR9888_COUNT_DEC_ADDRESS, 490*5113495bSYour Name .d_HOST_INT_STATUS_CPU_MASK = AR9888_HOST_INT_STATUS_CPU_MASK, 491*5113495bSYour Name .d_HOST_INT_STATUS_CPU_LSB = AR9888_HOST_INT_STATUS_CPU_LSB, 492*5113495bSYour Name .d_HOST_INT_STATUS_ERROR_MASK = AR9888_HOST_INT_STATUS_ERROR_MASK, 493*5113495bSYour Name .d_HOST_INT_STATUS_ERROR_LSB = AR9888_HOST_INT_STATUS_ERROR_LSB, 494*5113495bSYour Name .d_HOST_INT_STATUS_COUNTER_MASK = AR9888_HOST_INT_STATUS_COUNTER_MASK, 495*5113495bSYour Name .d_HOST_INT_STATUS_COUNTER_LSB = AR9888_HOST_INT_STATUS_COUNTER_LSB, 496*5113495bSYour Name .d_RX_LOOKAHEAD_VALID_ADDRESS = AR9888_RX_LOOKAHEAD_VALID_ADDRESS, 497*5113495bSYour Name .d_WINDOW_DATA_ADDRESS = AR9888_WINDOW_DATA_ADDRESS, 498*5113495bSYour Name .d_WINDOW_READ_ADDR_ADDRESS = AR9888_WINDOW_READ_ADDR_ADDRESS, 499*5113495bSYour Name .d_WINDOW_WRITE_ADDR_ADDRESS = AR9888_WINDOW_WRITE_ADDR_ADDRESS, 500*5113495bSYour Name .d_SOC_GLOBAL_RESET_ADDRESS = AR9888_SOC_GLOBAL_RESET_ADDRESS, 501*5113495bSYour Name .d_RTC_STATE_ADDRESS = AR9888_RTC_STATE_ADDRESS, 502*5113495bSYour Name .d_RTC_STATE_COLD_RESET_MASK = AR9888_RTC_STATE_COLD_RESET_MASK, 503*5113495bSYour Name .d_RTC_STATE_V_MASK = AR9888_RTC_STATE_V_MASK, 504*5113495bSYour Name .d_RTC_STATE_V_LSB = AR9888_RTC_STATE_V_LSB, 505*5113495bSYour Name .d_FW_IND_EVENT_PENDING = AR9888_FW_IND_EVENT_PENDING, 506*5113495bSYour Name .d_FW_IND_INITIALIZED = AR9888_FW_IND_INITIALIZED, 507*5113495bSYour Name .d_RTC_STATE_V_ON = AR9888_RTC_STATE_V_ON, 508*5113495bSYour Name #if defined(SDIO_3_0) 509*5113495bSYour Name .d_HOST_INT_STATUS_MBOX_DATA_MASK = 510*5113495bSYour Name AR9888_HOST_INT_STATUS_MBOX_DATA_MASK, 511*5113495bSYour Name .d_HOST_INT_STATUS_MBOX_DATA_LSB = 512*5113495bSYour Name AR9888_HOST_INT_STATUS_MBOX_DATA_LSB, 513*5113495bSYour Name #endif 514*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 515*5113495bSYour Name .d_MUX_ID_MASK = AR9888_MUX_ID_MASK, 516*5113495bSYour Name .d_TRANSACTION_ID_MASK = AR9888_TRANSACTION_ID_MASK, 517*5113495bSYour Name .d_PCIE_LOCAL_BASE_ADDRESS = AR9888_PCIE_LOCAL_BASE_ADDRESS, 518*5113495bSYour Name .d_PCIE_SOC_WAKE_RESET = AR9888_PCIE_SOC_WAKE_RESET, 519*5113495bSYour Name .d_PCIE_SOC_WAKE_ADDRESS = AR9888_PCIE_SOC_WAKE_ADDRESS, 520*5113495bSYour Name .d_PCIE_SOC_WAKE_V_MASK = AR9888_PCIE_SOC_WAKE_V_MASK, 521*5113495bSYour Name .d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS, 522*5113495bSYour Name .d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK, 523*5113495bSYour Name .d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS, 524*5113495bSYour Name .d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS, 525*5113495bSYour Name .d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS, 526*5113495bSYour Name .d_HOST_CE_COUNT = 8, 527*5113495bSYour Name .d_ENABLE_MSI = 0, 528*5113495bSYour Name #endif 529*5113495bSYour Name }; 530*5113495bSYour Name 531*5113495bSYour Name #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 532*5113495bSYour Name struct ce_reg_def ar9888_ce_targetdef = { 533*5113495bSYour Name /* copy_engine.c */ 534*5113495bSYour Name .d_DST_WR_INDEX_ADDRESS = AR9888_DST_WR_INDEX_ADDRESS, 535*5113495bSYour Name .d_SRC_WATERMARK_ADDRESS = AR9888_SRC_WATERMARK_ADDRESS, 536*5113495bSYour Name .d_SRC_WATERMARK_LOW_MASK = AR9888_SRC_WATERMARK_LOW_MASK, 537*5113495bSYour Name .d_SRC_WATERMARK_HIGH_MASK = AR9888_SRC_WATERMARK_HIGH_MASK, 538*5113495bSYour Name .d_DST_WATERMARK_LOW_MASK = AR9888_DST_WATERMARK_LOW_MASK, 539*5113495bSYour Name .d_DST_WATERMARK_HIGH_MASK = AR9888_DST_WATERMARK_HIGH_MASK, 540*5113495bSYour Name .d_CURRENT_SRRI_ADDRESS = AR9888_CURRENT_SRRI_ADDRESS, 541*5113495bSYour Name .d_CURRENT_DRRI_ADDRESS = AR9888_CURRENT_DRRI_ADDRESS, 542*5113495bSYour Name .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = 543*5113495bSYour Name AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 544*5113495bSYour Name .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = 545*5113495bSYour Name AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 546*5113495bSYour Name .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = 547*5113495bSYour Name AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 548*5113495bSYour Name .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = 549*5113495bSYour Name AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK, 550*5113495bSYour Name .d_HOST_IS_ADDRESS = AR9888_HOST_IS_ADDRESS, 551*5113495bSYour Name .d_HOST_IS_COPY_COMPLETE_MASK = AR9888_HOST_IS_COPY_COMPLETE_MASK, 552*5113495bSYour Name .d_CE_WRAPPER_BASE_ADDRESS = AR9888_CE_WRAPPER_BASE_ADDRESS, 553*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = 554*5113495bSYour Name AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, 555*5113495bSYour Name .d_HOST_IE_ADDRESS = AR9888_HOST_IE_ADDRESS, 556*5113495bSYour Name .d_HOST_IE_COPY_COMPLETE_MASK = AR9888_HOST_IE_COPY_COMPLETE_MASK, 557*5113495bSYour Name .d_SR_BA_ADDRESS = AR9888_SR_BA_ADDRESS, 558*5113495bSYour Name .d_SR_SIZE_ADDRESS = AR9888_SR_SIZE_ADDRESS, 559*5113495bSYour Name .d_CE_CTRL1_ADDRESS = AR9888_CE_CTRL1_ADDRESS, 560*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_MASK = AR9888_CE_CTRL1_DMAX_LENGTH_MASK, 561*5113495bSYour Name .d_DR_BA_ADDRESS = AR9888_DR_BA_ADDRESS, 562*5113495bSYour Name .d_DR_SIZE_ADDRESS = AR9888_DR_SIZE_ADDRESS, 563*5113495bSYour Name .d_MISC_IE_ADDRESS = AR9888_MISC_IE_ADDRESS, 564*5113495bSYour Name .d_MISC_IS_AXI_ERR_MASK = AR9888_MISC_IS_AXI_ERR_MASK, 565*5113495bSYour Name .d_MISC_IS_DST_ADDR_ERR_MASK = AR9888_MISC_IS_DST_ADDR_ERR_MASK, 566*5113495bSYour Name .d_MISC_IS_SRC_LEN_ERR_MASK = AR9888_MISC_IS_SRC_LEN_ERR_MASK, 567*5113495bSYour Name .d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK, 568*5113495bSYour Name .d_MISC_IS_DST_RING_OVERFLOW_MASK = 569*5113495bSYour Name AR9888_MISC_IS_DST_RING_OVERFLOW_MASK, 570*5113495bSYour Name .d_MISC_IS_SRC_RING_OVERFLOW_MASK = 571*5113495bSYour Name AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK, 572*5113495bSYour Name .d_SRC_WATERMARK_LOW_LSB = AR9888_SRC_WATERMARK_LOW_LSB, 573*5113495bSYour Name .d_SRC_WATERMARK_HIGH_LSB = AR9888_SRC_WATERMARK_HIGH_LSB, 574*5113495bSYour Name .d_DST_WATERMARK_LOW_LSB = AR9888_DST_WATERMARK_LOW_LSB, 575*5113495bSYour Name .d_DST_WATERMARK_HIGH_LSB = AR9888_DST_WATERMARK_HIGH_LSB, 576*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = 577*5113495bSYour Name AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 578*5113495bSYour Name .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = 579*5113495bSYour Name AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 580*5113495bSYour Name .d_CE_CTRL1_DMAX_LENGTH_LSB = AR9888_CE_CTRL1_DMAX_LENGTH_LSB, 581*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = 582*5113495bSYour Name AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 583*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = 584*5113495bSYour Name AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 585*5113495bSYour Name .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = 586*5113495bSYour Name AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 587*5113495bSYour Name .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = 588*5113495bSYour Name AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 589*5113495bSYour Name .d_CE0_BASE_ADDRESS = AR9888_CE0_BASE_ADDRESS, 590*5113495bSYour Name .d_CE1_BASE_ADDRESS = AR9888_CE1_BASE_ADDRESS, 591*5113495bSYour Name 592*5113495bSYour Name }; 593*5113495bSYour Name #endif 594*5113495bSYour Name #endif 595