xref: /wlan-driver/qca-wifi-host-cmn/hif/src/ar9888def.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2011-2016, 2018 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef _AR9888DEF_H_
20 #define _AR9888DEF_H_
21 
22 /* Base Addresses */
23 #define AR9888_RTC_SOC_BASE_ADDRESS                     0x00004000
24 #define AR9888_RTC_WMAC_BASE_ADDRESS                    0x00005000
25 #define AR9888_MAC_COEX_BASE_ADDRESS                    0x00006000
26 #define AR9888_BT_COEX_BASE_ADDRESS                     0x00007000
27 #define AR9888_SOC_PCIE_BASE_ADDRESS                    0x00008000
28 #define AR9888_SOC_CORE_BASE_ADDRESS                    0x00009000
29 #define AR9888_WLAN_UART_BASE_ADDRESS                   0x0000c000
30 #define AR9888_WLAN_SI_BASE_ADDRESS                     0x00010000
31 #define AR9888_WLAN_GPIO_BASE_ADDRESS                   0x00014000
32 #define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS            0x0001c000
33 #define AR9888_WLAN_MAC_BASE_ADDRESS                    0x00020000
34 #define AR9888_EFUSE_BASE_ADDRESS                       0x00030000
35 #define AR9888_FPGA_REG_BASE_ADDRESS                    0x00039000
36 #define AR9888_WLAN_UART2_BASE_ADDRESS                  0x00054c00
37 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
38 #define AR9888_CE_WRAPPER_BASE_ADDRESS                  0x00057000
39 #define AR9888_CE0_BASE_ADDRESS                         0x00057400
40 #define AR9888_CE1_BASE_ADDRESS                         0x00057800
41 #define AR9888_CE2_BASE_ADDRESS                         0x00057c00
42 #define AR9888_CE3_BASE_ADDRESS                         0x00058000
43 #define AR9888_CE4_BASE_ADDRESS                         0x00058400
44 #define AR9888_CE5_BASE_ADDRESS                         0x00058800
45 #define AR9888_CE6_BASE_ADDRESS                         0x00058c00
46 #define AR9888_CE7_BASE_ADDRESS                         0x00059000
47 #define AR9888_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS       0x0006c000
48 #define AR9888_CE_CTRL1_ADDRESS                         0x0010
49 #define AR9888_CE_CTRL1_DMAX_LENGTH_MASK                0x0000ffff
50 #define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS     0x0000
51 #define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
52 #define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  8
53 #define AR9888_CE_CTRL1_DMAX_LENGTH_LSB                 0
54 #define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK      0x00010000
55 #define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK      0x00020000
56 #define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB       16
57 #define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB       17
58 #define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004
59 #define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB  2
60 #define AR9888_PCIE_SOC_WAKE_RESET                      0x00000000
61 #define AR9888_PCIE_SOC_WAKE_ADDRESS                    0x0004
62 #define AR9888_PCIE_SOC_WAKE_V_MASK                     0x00000001
63 #define AR9888_PCIE_INTR_ENABLE_ADDRESS                 0x0008
64 #define AR9888_PCIE_INTR_CLR_ADDRESS                    0x0014
65 #define AR9888_PCIE_INTR_FIRMWARE_MASK                  0x00000400
66 #define AR9888_PCIE_INTR_CE0_MASK                       0x00000800
67 #define AR9888_PCIE_INTR_CE_MASK_ALL                    0x0007f800
68 #define AR9888_PCIE_INTR_CAUSE_ADDRESS                  0x000c
69 #define AR9888_MUX_ID_MASK                              0x0000
70 #define AR9888_TRANSACTION_ID_MASK                      0x3fff
71 #define AR9888_PCIE_LOCAL_BASE_ADDRESS                  0x80000
72 #define AR9888_SOC_RESET_CONTROL_CE_RST_MASK            0x00040000
73 #define AR9888_PCIE_INTR_CE_MASK(n) (AR9888_PCIE_INTR_CE0_MASK << (n))
74 #endif
75 #define AR9888_DBI_BASE_ADDRESS                         0x00060000
76 #define AR9888_SCRATCH_3_ADDRESS                        0x0030
77 #define AR9888_TARG_DRAM_START                          0x00400000
78 #define AR9888_SOC_SYSTEM_SLEEP_OFFSET                  0x000000c4
79 #define AR9888_SOC_RESET_CONTROL_OFFSET                 0x00000000
80 #define AR9888_SOC_CLOCK_CONTROL_OFFSET                 0x00000028
81 #define AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
82 #define AR9888_SOC_RESET_CONTROL_SI0_RST_MASK           0x00000001
83 #define AR9888_WLAN_GPIO_BASE_ADDRESS                   0x00014000
84 #define AR9888_WLAN_GPIO_PIN0_ADDRESS                   0x00000028
85 #define AR9888_WLAN_GPIO_PIN1_ADDRESS                   0x0000002c
86 #define AR9888_WLAN_GPIO_PIN0_CONFIG_MASK               0x00007800
87 #define AR9888_WLAN_GPIO_PIN1_CONFIG_MASK               0x00007800
88 #define AR9888_WLAN_SI_BASE_ADDRESS                     0x00010000
89 #define AR9888_SOC_CPU_CLOCK_OFFSET                     0x00000020
90 #define AR9888_SOC_LPO_CAL_OFFSET                       0x000000e0
91 #define AR9888_WLAN_GPIO_PIN10_ADDRESS                  0x00000050
92 #define AR9888_WLAN_GPIO_PIN11_ADDRESS                  0x00000054
93 #define AR9888_WLAN_GPIO_PIN12_ADDRESS                  0x00000058
94 #define AR9888_WLAN_GPIO_PIN13_ADDRESS                  0x0000005c
95 #define AR9888_SOC_CPU_CLOCK_STANDARD_LSB               0
96 #define AR9888_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
97 #define AR9888_SOC_LPO_CAL_ENABLE_LSB                   20
98 #define AR9888_SOC_LPO_CAL_ENABLE_MASK                  0x00100000
99 #define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS            0x0001c000
100 
101 #define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
102 #define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
103 #define AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000008
104 #define AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000004
105 #define AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB              18
106 #define AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
107 #define AR9888_SI_CONFIG_I2C_LSB                        16
108 #define AR9888_SI_CONFIG_I2C_MASK                       0x00010000
109 #define AR9888_SI_CONFIG_POS_SAMPLE_LSB                 7
110 #define AR9888_SI_CONFIG_POS_SAMPLE_MASK                0x00000080
111 #define AR9888_SI_CONFIG_INACTIVE_CLK_LSB               4
112 #define AR9888_SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
113 #define AR9888_SI_CONFIG_INACTIVE_DATA_LSB              5
114 #define AR9888_SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
115 #define AR9888_SI_CONFIG_DIVIDER_LSB                    0
116 #define AR9888_SI_CONFIG_DIVIDER_MASK                   0x0000000f
117 #define AR9888_SI_CONFIG_OFFSET                         0x00000000
118 #define AR9888_SI_TX_DATA0_OFFSET                       0x00000008
119 #define AR9888_SI_TX_DATA1_OFFSET                       0x0000000c
120 #define AR9888_SI_RX_DATA0_OFFSET                       0x00000010
121 #define AR9888_SI_RX_DATA1_OFFSET                       0x00000014
122 #define AR9888_SI_CS_OFFSET                             0x00000004
123 #define AR9888_SI_CS_DONE_ERR_MASK                      0x00000400
124 #define AR9888_SI_CS_DONE_INT_MASK                      0x00000200
125 #define AR9888_SI_CS_START_LSB                          8
126 #define AR9888_SI_CS_START_MASK                         0x00000100
127 #define AR9888_SI_CS_RX_CNT_LSB                         4
128 #define AR9888_SI_CS_RX_CNT_MASK                        0x000000f0
129 #define AR9888_SI_CS_TX_CNT_LSB                         0
130 #define AR9888_SI_CS_TX_CNT_MASK                        0x0000000f
131 #define AR9888_CE_COUNT                                 8
132 #define AR9888_SR_WR_INDEX_ADDRESS                      0x003c
133 #define AR9888_DST_WATERMARK_ADDRESS                    0x0050
134 #define AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB             14
135 #define AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK            0x00004000
136 #define AR9888_RX_MPDU_START_0_SEQ_NUM_LSB              16
137 #define AR9888_RX_MPDU_START_0_SEQ_NUM_MASK             0x0fff0000
138 #define AR9888_RX_MPDU_START_2_PN_47_32_LSB             0
139 #define AR9888_RX_MPDU_START_2_PN_47_32_MASK            0x0000ffff
140 #define AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK            0x000000ff
141 #define AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB             0
142 #define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB      16
143 #define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK     0xffff0000
144 #define AR9888_RX_MSDU_END_4_LAST_MSDU_LSB              15
145 #define AR9888_RX_MSDU_END_4_LAST_MSDU_MASK             0x00008000
146 #define AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB           2
147 #define AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK          0x00000004
148 #define AR9888_RX_ATTENTION_0_FRAGMENT_LSB              13
149 #define AR9888_RX_ATTENTION_0_FRAGMENT_MASK             0x00002000
150 #define AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK      0x08000000
151 #define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB      16
152 #define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK     0x00ff0000
153 #define AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB          0
154 #define AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK         0x00003fff
155 #define AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET      0x00000008
156 #define AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB         8
157 #define AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK        0x00000300
158 #define AR9888_RX_MPDU_START_0_ENCRYPTED_LSB            13
159 #define AR9888_RX_MPDU_START_0_ENCRYPTED_MASK           0x00002000
160 #define AR9888_RX_ATTENTION_0_MORE_DATA_MASK            0x00000400
161 #define AR9888_RX_ATTENTION_0_MSDU_DONE_MASK            0x80000000
162 #define AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK  0x00040000
163 #define AR9888_DST_WR_INDEX_ADDRESS                     0x0040
164 #define AR9888_SRC_WATERMARK_ADDRESS                    0x004c
165 #define AR9888_SRC_WATERMARK_LOW_MASK                   0xffff0000
166 #define AR9888_SRC_WATERMARK_HIGH_MASK                  0x0000ffff
167 #define AR9888_DST_WATERMARK_LOW_MASK                   0xffff0000
168 #define AR9888_DST_WATERMARK_HIGH_MASK                  0x0000ffff
169 #define AR9888_CURRENT_SRRI_ADDRESS                     0x0044
170 #define AR9888_CURRENT_DRRI_ADDRESS                     0x0048
171 #define AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK     0x00000002
172 #define AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK      0x00000004
173 #define AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK     0x00000008
174 #define AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK      0x00000010
175 #define AR9888_HOST_IS_ADDRESS                          0x0030
176 #define AR9888_HOST_IS_COPY_COMPLETE_MASK               0x00000001
177 #define AR9888_HOST_IE_ADDRESS                          0x002c
178 #define AR9888_HOST_IE_COPY_COMPLETE_MASK               0x00000001
179 #define AR9888_SR_BA_ADDRESS                            0x0000
180 #define AR9888_SR_SIZE_ADDRESS                          0x0004
181 #define AR9888_DR_BA_ADDRESS                            0x0008
182 #define AR9888_DR_SIZE_ADDRESS                          0x000c
183 #define AR9888_MISC_IE_ADDRESS                          0x0034
184 #define AR9888_MISC_IS_AXI_ERR_MASK                     0x00000400
185 #define AR9888_MISC_IS_DST_ADDR_ERR_MASK                0x00000200
186 #define AR9888_MISC_IS_SRC_LEN_ERR_MASK                 0x00000100
187 #define AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK             0x00000080
188 #define AR9888_MISC_IS_DST_RING_OVERFLOW_MASK           0x00000040
189 #define AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK           0x00000020
190 #define AR9888_SRC_WATERMARK_LOW_LSB                    16
191 #define AR9888_SRC_WATERMARK_HIGH_LSB                   0
192 #define AR9888_DST_WATERMARK_LOW_LSB                    16
193 #define AR9888_DST_WATERMARK_HIGH_LSB                   0
194 #define AR9888_SOC_GLOBAL_RESET_ADDRESS                 0x0008
195 #define AR9888_RTC_STATE_ADDRESS                        0x0000
196 #define AR9888_RTC_STATE_COLD_RESET_MASK                0x00000400
197 
198 #define AR9888_RTC_STATE_V_MASK                         0x00000007
199 #define AR9888_RTC_STATE_V_LSB                          0
200 #define AR9888_RTC_STATE_V_ON                           3
201 #define AR9888_FW_IND_EVENT_PENDING                     1
202 #define AR9888_FW_IND_INITIALIZED                       2
203 #define AR9888_CPU_INTR_ADDRESS                         0x0010
204 #define AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
205 #define AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
206 #define AR9888_SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
207 #define AR9888_SOC_RESET_CONTROL_ADDRESS                0x00000000
208 #define AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
209 #define AR9888_CORE_CTRL_ADDRESS                        0x0000
210 #define AR9888_CORE_CTRL_CPU_INTR_MASK                  0x00002000
211 #define AR9888_LOCAL_SCRATCH_OFFSET                     0x18
212 #define AR9888_CLOCK_GPIO_OFFSET                        0xffffffff
213 #define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
214 #define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
215 
216 #define AR9888_FW_EVENT_PENDING_ADDRESS \
217 	(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)
218 #define AR9888_DRAM_BASE_ADDRESS AR9888_TARG_DRAM_START
219 #define AR9888_FW_INDICATOR_ADDRESS \
220 	(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)
221 #define AR9888_SYSTEM_SLEEP_OFFSET        AR9888_SOC_SYSTEM_SLEEP_OFFSET
222 #define AR9888_WLAN_SYSTEM_SLEEP_OFFSET   AR9888_SOC_SYSTEM_SLEEP_OFFSET
223 #define AR9888_WLAN_RESET_CONTROL_OFFSET  AR9888_SOC_RESET_CONTROL_OFFSET
224 #define AR9888_CLOCK_CONTROL_OFFSET       AR9888_SOC_CLOCK_CONTROL_OFFSET
225 #define AR9888_CLOCK_CONTROL_SI0_CLK_MASK AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK
226 #define AR9888_RESET_CONTROL_MBOX_RST_MASK MISSING
227 #define AR9888_RESET_CONTROL_SI0_RST_MASK AR9888_SOC_RESET_CONTROL_SI0_RST_MASK
228 #define AR9888_GPIO_BASE_ADDRESS          AR9888_WLAN_GPIO_BASE_ADDRESS
229 #define AR9888_GPIO_PIN0_OFFSET           AR9888_WLAN_GPIO_PIN0_ADDRESS
230 #define AR9888_GPIO_PIN1_OFFSET           AR9888_WLAN_GPIO_PIN1_ADDRESS
231 #define AR9888_GPIO_PIN0_CONFIG_MASK      AR9888_WLAN_GPIO_PIN0_CONFIG_MASK
232 #define AR9888_GPIO_PIN1_CONFIG_MASK      AR9888_WLAN_GPIO_PIN1_CONFIG_MASK
233 #define AR9888_SI_BASE_ADDRESS            AR9888_WLAN_SI_BASE_ADDRESS
234 #define AR9888_SCRATCH_BASE_ADDRESS       AR9888_SOC_CORE_BASE_ADDRESS
235 #define AR9888_CPU_CLOCK_OFFSET           AR9888_SOC_CPU_CLOCK_OFFSET
236 #define AR9888_LPO_CAL_OFFSET             AR9888_SOC_LPO_CAL_OFFSET
237 #define AR9888_GPIO_PIN10_OFFSET          AR9888_WLAN_GPIO_PIN10_ADDRESS
238 #define AR9888_GPIO_PIN11_OFFSET          AR9888_WLAN_GPIO_PIN11_ADDRESS
239 #define AR9888_GPIO_PIN12_OFFSET          AR9888_WLAN_GPIO_PIN12_ADDRESS
240 #define AR9888_GPIO_PIN13_OFFSET          AR9888_WLAN_GPIO_PIN13_ADDRESS
241 #define AR9888_CPU_CLOCK_STANDARD_LSB     AR9888_SOC_CPU_CLOCK_STANDARD_LSB
242 #define AR9888_CPU_CLOCK_STANDARD_MASK    AR9888_SOC_CPU_CLOCK_STANDARD_MASK
243 #define AR9888_LPO_CAL_ENABLE_LSB         AR9888_SOC_LPO_CAL_ENABLE_LSB
244 #define AR9888_LPO_CAL_ENABLE_MASK        AR9888_SOC_LPO_CAL_ENABLE_MASK
245 #define AR9888_ANALOG_INTF_BASE_ADDRESS   AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS
246 #define AR9888_MBOX_BASE_ADDRESS                       MISSING
247 #define AR9888_INT_STATUS_ENABLE_ERROR_LSB             MISSING
248 #define AR9888_INT_STATUS_ENABLE_ERROR_MASK            MISSING
249 #define AR9888_INT_STATUS_ENABLE_CPU_LSB               MISSING
250 #define AR9888_INT_STATUS_ENABLE_CPU_MASK              MISSING
251 #define AR9888_INT_STATUS_ENABLE_COUNTER_LSB           MISSING
252 #define AR9888_INT_STATUS_ENABLE_COUNTER_MASK          MISSING
253 #define AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
254 #define AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
255 #define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
256 #define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
257 #define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
258 #define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
259 #define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
260 #define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
261 #define AR9888_INT_STATUS_ENABLE_ADDRESS               MISSING
262 #define AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
263 #define AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
264 #define AR9888_HOST_INT_STATUS_ADDRESS                 MISSING
265 #define AR9888_CPU_INT_STATUS_ADDRESS                  MISSING
266 #define AR9888_ERROR_INT_STATUS_ADDRESS                MISSING
267 #define AR9888_ERROR_INT_STATUS_WAKEUP_MASK            MISSING
268 #define AR9888_ERROR_INT_STATUS_WAKEUP_LSB             MISSING
269 #define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
270 #define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
271 #define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
272 #define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
273 #define AR9888_COUNT_DEC_ADDRESS                       MISSING
274 #define AR9888_HOST_INT_STATUS_CPU_MASK                MISSING
275 #define AR9888_HOST_INT_STATUS_CPU_LSB                 MISSING
276 #define AR9888_HOST_INT_STATUS_ERROR_MASK              MISSING
277 #define AR9888_HOST_INT_STATUS_ERROR_LSB               MISSING
278 #define AR9888_HOST_INT_STATUS_COUNTER_MASK            MISSING
279 #define AR9888_HOST_INT_STATUS_COUNTER_LSB             MISSING
280 #define AR9888_RX_LOOKAHEAD_VALID_ADDRESS              MISSING
281 #define AR9888_WINDOW_DATA_ADDRESS                     MISSING
282 #define AR9888_WINDOW_READ_ADDR_ADDRESS                MISSING
283 #define AR9888_WINDOW_WRITE_ADDR_ADDRESS               MISSING
284 #define AR9888_HOST_INT_STATUS_MBOX_DATA_MASK          0x0f
285 #define AR9888_HOST_INT_STATUS_MBOX_DATA_LSB           0
286 
287 struct targetdef_s ar9888_targetdef = {
288 	.d_RTC_SOC_BASE_ADDRESS = AR9888_RTC_SOC_BASE_ADDRESS,
289 	.d_RTC_WMAC_BASE_ADDRESS = AR9888_RTC_WMAC_BASE_ADDRESS,
290 	.d_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,
291 	.d_WLAN_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,
292 	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
293 		AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
294 	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
295 		AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
296 	.d_CLOCK_CONTROL_OFFSET = AR9888_CLOCK_CONTROL_OFFSET,
297 	.d_CLOCK_CONTROL_SI0_CLK_MASK = AR9888_CLOCK_CONTROL_SI0_CLK_MASK,
298 	.d_RESET_CONTROL_OFFSET = AR9888_SOC_RESET_CONTROL_OFFSET,
299 	.d_RESET_CONTROL_MBOX_RST_MASK = AR9888_RESET_CONTROL_MBOX_RST_MASK,
300 	.d_RESET_CONTROL_SI0_RST_MASK = AR9888_RESET_CONTROL_SI0_RST_MASK,
301 	.d_WLAN_RESET_CONTROL_OFFSET = AR9888_WLAN_RESET_CONTROL_OFFSET,
302 	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
303 		AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK,
304 	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
305 		AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK,
306 	.d_GPIO_BASE_ADDRESS = AR9888_GPIO_BASE_ADDRESS,
307 	.d_GPIO_PIN0_OFFSET = AR9888_GPIO_PIN0_OFFSET,
308 	.d_GPIO_PIN1_OFFSET = AR9888_GPIO_PIN1_OFFSET,
309 	.d_GPIO_PIN0_CONFIG_MASK = AR9888_GPIO_PIN0_CONFIG_MASK,
310 	.d_GPIO_PIN1_CONFIG_MASK = AR9888_GPIO_PIN1_CONFIG_MASK,
311 	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB,
312 	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK,
313 	.d_SI_CONFIG_I2C_LSB = AR9888_SI_CONFIG_I2C_LSB,
314 	.d_SI_CONFIG_I2C_MASK = AR9888_SI_CONFIG_I2C_MASK,
315 	.d_SI_CONFIG_POS_SAMPLE_LSB = AR9888_SI_CONFIG_POS_SAMPLE_LSB,
316 	.d_SI_CONFIG_POS_SAMPLE_MASK = AR9888_SI_CONFIG_POS_SAMPLE_MASK,
317 	.d_SI_CONFIG_INACTIVE_CLK_LSB = AR9888_SI_CONFIG_INACTIVE_CLK_LSB,
318 	.d_SI_CONFIG_INACTIVE_CLK_MASK = AR9888_SI_CONFIG_INACTIVE_CLK_MASK,
319 	.d_SI_CONFIG_INACTIVE_DATA_LSB = AR9888_SI_CONFIG_INACTIVE_DATA_LSB,
320 	.d_SI_CONFIG_INACTIVE_DATA_MASK = AR9888_SI_CONFIG_INACTIVE_DATA_MASK,
321 	.d_SI_CONFIG_DIVIDER_LSB = AR9888_SI_CONFIG_DIVIDER_LSB,
322 	.d_SI_CONFIG_DIVIDER_MASK = AR9888_SI_CONFIG_DIVIDER_MASK,
323 	.d_SI_BASE_ADDRESS = AR9888_SI_BASE_ADDRESS,
324 	.d_SI_CONFIG_OFFSET = AR9888_SI_CONFIG_OFFSET,
325 	.d_SI_TX_DATA0_OFFSET = AR9888_SI_TX_DATA0_OFFSET,
326 	.d_SI_TX_DATA1_OFFSET = AR9888_SI_TX_DATA1_OFFSET,
327 	.d_SI_RX_DATA0_OFFSET = AR9888_SI_RX_DATA0_OFFSET,
328 	.d_SI_RX_DATA1_OFFSET = AR9888_SI_RX_DATA1_OFFSET,
329 	.d_SI_CS_OFFSET = AR9888_SI_CS_OFFSET,
330 	.d_SI_CS_DONE_ERR_MASK = AR9888_SI_CS_DONE_ERR_MASK,
331 	.d_SI_CS_DONE_INT_MASK = AR9888_SI_CS_DONE_INT_MASK,
332 	.d_SI_CS_START_LSB = AR9888_SI_CS_START_LSB,
333 	.d_SI_CS_START_MASK = AR9888_SI_CS_START_MASK,
334 	.d_SI_CS_RX_CNT_LSB = AR9888_SI_CS_RX_CNT_LSB,
335 	.d_SI_CS_RX_CNT_MASK = AR9888_SI_CS_RX_CNT_MASK,
336 	.d_SI_CS_TX_CNT_LSB = AR9888_SI_CS_TX_CNT_LSB,
337 	.d_SI_CS_TX_CNT_MASK = AR9888_SI_CS_TX_CNT_MASK,
338 	.d_BOARD_DATA_SZ = AR9888_BOARD_DATA_SZ,
339 	.d_BOARD_EXT_DATA_SZ = AR9888_BOARD_EXT_DATA_SZ,
340 	.d_MBOX_BASE_ADDRESS = AR9888_MBOX_BASE_ADDRESS,
341 	.d_LOCAL_SCRATCH_OFFSET = AR9888_LOCAL_SCRATCH_OFFSET,
342 	.d_CPU_CLOCK_OFFSET = AR9888_CPU_CLOCK_OFFSET,
343 	.d_LPO_CAL_OFFSET = AR9888_LPO_CAL_OFFSET,
344 	.d_GPIO_PIN10_OFFSET = AR9888_GPIO_PIN10_OFFSET,
345 	.d_GPIO_PIN11_OFFSET = AR9888_GPIO_PIN11_OFFSET,
346 	.d_GPIO_PIN12_OFFSET = AR9888_GPIO_PIN12_OFFSET,
347 	.d_GPIO_PIN13_OFFSET = AR9888_GPIO_PIN13_OFFSET,
348 	.d_CLOCK_GPIO_OFFSET = AR9888_CLOCK_GPIO_OFFSET,
349 	.d_CPU_CLOCK_STANDARD_LSB = AR9888_CPU_CLOCK_STANDARD_LSB,
350 	.d_CPU_CLOCK_STANDARD_MASK = AR9888_CPU_CLOCK_STANDARD_MASK,
351 	.d_LPO_CAL_ENABLE_LSB = AR9888_LPO_CAL_ENABLE_LSB,
352 	.d_LPO_CAL_ENABLE_MASK = AR9888_LPO_CAL_ENABLE_MASK,
353 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
354 	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
355 		AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
356 	.d_ANALOG_INTF_BASE_ADDRESS = AR9888_ANALOG_INTF_BASE_ADDRESS,
357 	.d_WLAN_MAC_BASE_ADDRESS = AR9888_WLAN_MAC_BASE_ADDRESS,
358 	.d_FW_INDICATOR_ADDRESS = AR9888_FW_INDICATOR_ADDRESS,
359 	.d_DRAM_BASE_ADDRESS = AR9888_DRAM_BASE_ADDRESS,
360 	.d_SOC_CORE_BASE_ADDRESS = AR9888_SOC_CORE_BASE_ADDRESS,
361 	.d_CORE_CTRL_ADDRESS = AR9888_CORE_CTRL_ADDRESS,
362 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
363 	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
364 	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
365 #endif
366 	.d_CORE_CTRL_CPU_INTR_MASK = AR9888_CORE_CTRL_CPU_INTR_MASK,
367 	.d_SR_WR_INDEX_ADDRESS = AR9888_SR_WR_INDEX_ADDRESS,
368 	.d_DST_WATERMARK_ADDRESS = AR9888_DST_WATERMARK_ADDRESS,
369 	/* htt_rx.c */
370 	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
371 		AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK,
372 	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB,
373 	.d_RX_MPDU_START_0_SEQ_NUM_MASK = AR9888_RX_MPDU_START_0_SEQ_NUM_MASK,
374 	.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR9888_RX_MPDU_START_0_SEQ_NUM_LSB,
375 	.d_RX_MPDU_START_2_PN_47_32_LSB = AR9888_RX_MPDU_START_2_PN_47_32_LSB,
376 	.d_RX_MPDU_START_2_PN_47_32_MASK =
377 		AR9888_RX_MPDU_START_2_PN_47_32_MASK,
378 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
379 		AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
380 	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
381 		AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
382 	.d_RX_MSDU_END_1_KEY_ID_OCT_MASK =
383 		AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK,
384 	.d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB,
385 	.d_RX_MSDU_END_4_LAST_MSDU_MASK = AR9888_RX_MSDU_END_4_LAST_MSDU_MASK,
386 	.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR9888_RX_MSDU_END_4_LAST_MSDU_LSB,
387 	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
388 		AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK,
389 	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
390 		AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB,
391 	.d_RX_ATTENTION_0_FRAGMENT_MASK = AR9888_RX_ATTENTION_0_FRAGMENT_MASK,
392 	.d_RX_ATTENTION_0_FRAGMENT_LSB = AR9888_RX_ATTENTION_0_FRAGMENT_LSB,
393 	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
394 		AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
395 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
396 		AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
397 	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
398 		AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
399 	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
400 		AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK,
401 	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
402 		AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB,
403 	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
404 		AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
405 	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
406 		AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK,
407 	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
408 		AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB,
409 	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
410 		AR9888_RX_MPDU_START_0_ENCRYPTED_MASK,
411 	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
412 		AR9888_RX_MPDU_START_0_ENCRYPTED_LSB,
413 	.d_RX_ATTENTION_0_MORE_DATA_MASK =
414 		AR9888_RX_ATTENTION_0_MORE_DATA_MASK,
415 	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
416 		AR9888_RX_ATTENTION_0_MSDU_DONE_MASK,
417 	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
418 		AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
419 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
420 	.d_CE_COUNT = AR9888_CE_COUNT,
421 	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
422 	.d_PCIE_INTR_ENABLE_ADDRESS = AR9888_PCIE_INTR_ENABLE_ADDRESS,
423 	.d_PCIE_INTR_CLR_ADDRESS = AR9888_PCIE_INTR_CLR_ADDRESS,
424 	.d_PCIE_INTR_FIRMWARE_MASK = AR9888_PCIE_INTR_FIRMWARE_MASK,
425 	.d_PCIE_INTR_CE_MASK_ALL = AR9888_PCIE_INTR_CE_MASK_ALL,
426 	.d_PCIE_INTR_CAUSE_ADDRESS = AR9888_PCIE_INTR_CAUSE_ADDRESS,
427 	.d_SOC_RESET_CONTROL_ADDRESS = AR9888_SOC_RESET_CONTROL_ADDRESS,
428 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
429 		AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
430 	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
431 		AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
432 	.d_SOC_RESET_CONTROL_CE_RST_MASK =
433 		AR9888_SOC_RESET_CONTROL_CE_RST_MASK,
434 #endif
435 	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
436 		AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
437 	.d_CPU_INTR_ADDRESS = AR9888_CPU_INTR_ADDRESS,
438 	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
439 		AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS,
440 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
441 		AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
442 	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
443 		AR9888_SOC_LF_TIMER_STATUS0_ADDRESS,
444 };
445 
446 struct hostdef_s ar9888_hostdef = {
447 	.d_INT_STATUS_ENABLE_ERROR_LSB = AR9888_INT_STATUS_ENABLE_ERROR_LSB,
448 	.d_INT_STATUS_ENABLE_ERROR_MASK = AR9888_INT_STATUS_ENABLE_ERROR_MASK,
449 	.d_INT_STATUS_ENABLE_CPU_LSB = AR9888_INT_STATUS_ENABLE_CPU_LSB,
450 	.d_INT_STATUS_ENABLE_CPU_MASK = AR9888_INT_STATUS_ENABLE_CPU_MASK,
451 	.d_INT_STATUS_ENABLE_COUNTER_LSB =
452 		AR9888_INT_STATUS_ENABLE_COUNTER_LSB,
453 	.d_INT_STATUS_ENABLE_COUNTER_MASK =
454 		AR9888_INT_STATUS_ENABLE_COUNTER_MASK,
455 	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
456 		AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB,
457 	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
458 		AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK,
459 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
460 		AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
461 	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
462 		AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
463 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
464 		AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
465 	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
466 		AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
467 	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
468 		AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
469 	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
470 		AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
471 	.d_INT_STATUS_ENABLE_ADDRESS = AR9888_INT_STATUS_ENABLE_ADDRESS,
472 	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
473 		AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB,
474 	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
475 		AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK,
476 	.d_HOST_INT_STATUS_ADDRESS = AR9888_HOST_INT_STATUS_ADDRESS,
477 	.d_CPU_INT_STATUS_ADDRESS = AR9888_CPU_INT_STATUS_ADDRESS,
478 	.d_ERROR_INT_STATUS_ADDRESS = AR9888_ERROR_INT_STATUS_ADDRESS,
479 	.d_ERROR_INT_STATUS_WAKEUP_MASK = AR9888_ERROR_INT_STATUS_WAKEUP_MASK,
480 	.d_ERROR_INT_STATUS_WAKEUP_LSB = AR9888_ERROR_INT_STATUS_WAKEUP_LSB,
481 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
482 		AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
483 	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
484 		AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
485 	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
486 		AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
487 	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
488 		AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
489 	.d_COUNT_DEC_ADDRESS = AR9888_COUNT_DEC_ADDRESS,
490 	.d_HOST_INT_STATUS_CPU_MASK = AR9888_HOST_INT_STATUS_CPU_MASK,
491 	.d_HOST_INT_STATUS_CPU_LSB = AR9888_HOST_INT_STATUS_CPU_LSB,
492 	.d_HOST_INT_STATUS_ERROR_MASK = AR9888_HOST_INT_STATUS_ERROR_MASK,
493 	.d_HOST_INT_STATUS_ERROR_LSB = AR9888_HOST_INT_STATUS_ERROR_LSB,
494 	.d_HOST_INT_STATUS_COUNTER_MASK = AR9888_HOST_INT_STATUS_COUNTER_MASK,
495 	.d_HOST_INT_STATUS_COUNTER_LSB = AR9888_HOST_INT_STATUS_COUNTER_LSB,
496 	.d_RX_LOOKAHEAD_VALID_ADDRESS = AR9888_RX_LOOKAHEAD_VALID_ADDRESS,
497 	.d_WINDOW_DATA_ADDRESS = AR9888_WINDOW_DATA_ADDRESS,
498 	.d_WINDOW_READ_ADDR_ADDRESS = AR9888_WINDOW_READ_ADDR_ADDRESS,
499 	.d_WINDOW_WRITE_ADDR_ADDRESS = AR9888_WINDOW_WRITE_ADDR_ADDRESS,
500 	.d_SOC_GLOBAL_RESET_ADDRESS = AR9888_SOC_GLOBAL_RESET_ADDRESS,
501 	.d_RTC_STATE_ADDRESS = AR9888_RTC_STATE_ADDRESS,
502 	.d_RTC_STATE_COLD_RESET_MASK = AR9888_RTC_STATE_COLD_RESET_MASK,
503 	.d_RTC_STATE_V_MASK = AR9888_RTC_STATE_V_MASK,
504 	.d_RTC_STATE_V_LSB = AR9888_RTC_STATE_V_LSB,
505 	.d_FW_IND_EVENT_PENDING = AR9888_FW_IND_EVENT_PENDING,
506 	.d_FW_IND_INITIALIZED = AR9888_FW_IND_INITIALIZED,
507 	.d_RTC_STATE_V_ON = AR9888_RTC_STATE_V_ON,
508 #if defined(SDIO_3_0)
509 	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
510 		AR9888_HOST_INT_STATUS_MBOX_DATA_MASK,
511 	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
512 		AR9888_HOST_INT_STATUS_MBOX_DATA_LSB,
513 #endif
514 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
515 	.d_MUX_ID_MASK = AR9888_MUX_ID_MASK,
516 	.d_TRANSACTION_ID_MASK = AR9888_TRANSACTION_ID_MASK,
517 	.d_PCIE_LOCAL_BASE_ADDRESS = AR9888_PCIE_LOCAL_BASE_ADDRESS,
518 	.d_PCIE_SOC_WAKE_RESET = AR9888_PCIE_SOC_WAKE_RESET,
519 	.d_PCIE_SOC_WAKE_ADDRESS = AR9888_PCIE_SOC_WAKE_ADDRESS,
520 	.d_PCIE_SOC_WAKE_V_MASK = AR9888_PCIE_SOC_WAKE_V_MASK,
521 	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
522 	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
523 	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
524 	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
525 	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
526 	.d_HOST_CE_COUNT = 8,
527 	.d_ENABLE_MSI = 0,
528 #endif
529 };
530 
531 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
532 struct ce_reg_def ar9888_ce_targetdef = {
533 	/* copy_engine.c  */
534 	.d_DST_WR_INDEX_ADDRESS = AR9888_DST_WR_INDEX_ADDRESS,
535 	.d_SRC_WATERMARK_ADDRESS = AR9888_SRC_WATERMARK_ADDRESS,
536 	.d_SRC_WATERMARK_LOW_MASK = AR9888_SRC_WATERMARK_LOW_MASK,
537 	.d_SRC_WATERMARK_HIGH_MASK = AR9888_SRC_WATERMARK_HIGH_MASK,
538 	.d_DST_WATERMARK_LOW_MASK = AR9888_DST_WATERMARK_LOW_MASK,
539 	.d_DST_WATERMARK_HIGH_MASK = AR9888_DST_WATERMARK_HIGH_MASK,
540 	.d_CURRENT_SRRI_ADDRESS = AR9888_CURRENT_SRRI_ADDRESS,
541 	.d_CURRENT_DRRI_ADDRESS = AR9888_CURRENT_DRRI_ADDRESS,
542 	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
543 		AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
544 	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
545 		AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
546 	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
547 		AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
548 	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
549 		AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
550 	.d_HOST_IS_ADDRESS = AR9888_HOST_IS_ADDRESS,
551 	.d_HOST_IS_COPY_COMPLETE_MASK = AR9888_HOST_IS_COPY_COMPLETE_MASK,
552 	.d_CE_WRAPPER_BASE_ADDRESS = AR9888_CE_WRAPPER_BASE_ADDRESS,
553 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
554 		AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
555 	.d_HOST_IE_ADDRESS = AR9888_HOST_IE_ADDRESS,
556 	.d_HOST_IE_COPY_COMPLETE_MASK = AR9888_HOST_IE_COPY_COMPLETE_MASK,
557 	.d_SR_BA_ADDRESS = AR9888_SR_BA_ADDRESS,
558 	.d_SR_SIZE_ADDRESS = AR9888_SR_SIZE_ADDRESS,
559 	.d_CE_CTRL1_ADDRESS = AR9888_CE_CTRL1_ADDRESS,
560 	.d_CE_CTRL1_DMAX_LENGTH_MASK = AR9888_CE_CTRL1_DMAX_LENGTH_MASK,
561 	.d_DR_BA_ADDRESS = AR9888_DR_BA_ADDRESS,
562 	.d_DR_SIZE_ADDRESS = AR9888_DR_SIZE_ADDRESS,
563 	.d_MISC_IE_ADDRESS = AR9888_MISC_IE_ADDRESS,
564 	.d_MISC_IS_AXI_ERR_MASK = AR9888_MISC_IS_AXI_ERR_MASK,
565 	.d_MISC_IS_DST_ADDR_ERR_MASK = AR9888_MISC_IS_DST_ADDR_ERR_MASK,
566 	.d_MISC_IS_SRC_LEN_ERR_MASK = AR9888_MISC_IS_SRC_LEN_ERR_MASK,
567 	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK,
568 	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
569 		AR9888_MISC_IS_DST_RING_OVERFLOW_MASK,
570 	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
571 		AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK,
572 	.d_SRC_WATERMARK_LOW_LSB = AR9888_SRC_WATERMARK_LOW_LSB,
573 	.d_SRC_WATERMARK_HIGH_LSB = AR9888_SRC_WATERMARK_HIGH_LSB,
574 	.d_DST_WATERMARK_LOW_LSB = AR9888_DST_WATERMARK_LOW_LSB,
575 	.d_DST_WATERMARK_HIGH_LSB = AR9888_DST_WATERMARK_HIGH_LSB,
576 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
577 		AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
578 	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
579 		AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
580 	.d_CE_CTRL1_DMAX_LENGTH_LSB = AR9888_CE_CTRL1_DMAX_LENGTH_LSB,
581 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
582 		AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
583 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
584 		AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
585 	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
586 		AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
587 	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
588 		AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
589 	.d_CE0_BASE_ADDRESS = AR9888_CE0_BASE_ADDRESS,
590 	.d_CE1_BASE_ADDRESS = AR9888_CE1_BASE_ADDRESS,
591 
592 };
593 #endif
594 #endif
595