1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * Copyright (c) 2021,2023 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name struct hif_softc; 21*5113495bSYour Name struct hif_exec_context; 22*5113495bSYour Name 23*5113495bSYour Name void hif_dummy_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 24*5113495bSYour Name void hif_dummy_reset_soc(struct hif_softc *scn); 25*5113495bSYour Name int hif_dummy_bus_suspend(struct hif_softc *hif_ctx); 26*5113495bSYour Name int hif_dummy_bus_resume(struct hif_softc *hif_ctx); 27*5113495bSYour Name int hif_dummy_bus_suspend_noirq(struct hif_softc *hif_ctx); 28*5113495bSYour Name int hif_dummy_bus_resume_noirq(struct hif_softc *hif_ctx); 29*5113495bSYour Name int hif_dummy_target_sleep_state_adjust(struct hif_softc *scn, 30*5113495bSYour Name bool sleep_ok, bool wait_for_it); 31*5113495bSYour Name void hif_dummy_enable_power_management(struct hif_softc *hif_ctx, 32*5113495bSYour Name bool is_packet_log_enabled); 33*5113495bSYour Name void hif_dummy_disable_power_management(struct hif_softc *hif_ctx); 34*5113495bSYour Name void hif_dummy_disable_isr(struct hif_softc *scn); 35*5113495bSYour Name void hif_dummy_nointrs(struct hif_softc *hif_sc); 36*5113495bSYour Name int hif_dummy_bus_configure(struct hif_softc *hif_sc); 37*5113495bSYour Name QDF_STATUS hif_dummy_get_config_item(struct hif_softc *hif_sc, 38*5113495bSYour Name int opcode, void *config, uint32_t config_len); 39*5113495bSYour Name void hif_dummy_set_mailbox_swap(struct hif_softc *hif_sc); 40*5113495bSYour Name void hif_dummy_claim_device(struct hif_softc *hif_sc); 41*5113495bSYour Name void hif_dummy_cancel_deferred_target_sleep(struct hif_softc *hif_sc); 42*5113495bSYour Name void hif_dummy_irq_enable(struct hif_softc *hif_sc, int irq_id); 43*5113495bSYour Name void hif_dummy_irq_disable(struct hif_softc *hif_sc, int irq_id); 44*5113495bSYour Name void hif_dummy_grp_irq_enable(struct hif_softc *hif_sc, uint32_t grp_id); 45*5113495bSYour Name void hif_dummy_grp_irq_disable(struct hif_softc *hif_sc, uint32_t grp_id); 46*5113495bSYour Name int hif_dummy_grp_irq_configure(struct hif_softc *hif_sc, 47*5113495bSYour Name struct hif_exec_context *exec); 48*5113495bSYour Name void hif_dummy_grp_irq_deconfigure(struct hif_softc *hif_sc); 49*5113495bSYour Name int hif_dummy_dump_registers(struct hif_softc *hif_sc); 50*5113495bSYour Name void hif_dummy_dump_target_memory(struct hif_softc *hif_sc, void *ramdump_base, 51*5113495bSYour Name uint32_t address, uint32_t size); 52*5113495bSYour Name 53*5113495bSYour Name /** 54*5113495bSYour Name * hif_dummy_bus_reg_read32() - Read register in 32bits 55*5113495bSYour Name * @hif_sc: PCIe control struct 56*5113495bSYour Name * @offset: The register offset 57*5113495bSYour Name * 58*5113495bSYour Name * This function will read register in 32bits 59*5113495bSYour Name * 60*5113495bSYour Name * Return: return value for register with specified offset 61*5113495bSYour Name */ 62*5113495bSYour Name uint32_t hif_dummy_bus_reg_read32(struct hif_softc *hif_sc, 63*5113495bSYour Name uint32_t offset); 64*5113495bSYour Name 65*5113495bSYour Name /** 66*5113495bSYour Name * hif_dummy_bus_reg_write32() - Write register in 32bits 67*5113495bSYour Name * @hif_sc: PCIe control struct 68*5113495bSYour Name * @offset: The register offset 69*5113495bSYour Name * @value: The value need to be written 70*5113495bSYour Name * 71*5113495bSYour Name * This function will write register in 32bits 72*5113495bSYour Name * 73*5113495bSYour Name * Return: None 74*5113495bSYour Name */ 75*5113495bSYour Name void hif_dummy_bus_reg_write32(struct hif_softc *hif_sc, 76*5113495bSYour Name uint32_t offset, 77*5113495bSYour Name uint32_t value); 78*5113495bSYour Name 79*5113495bSYour Name void hif_dummy_ipa_get_ce_resource(struct hif_softc *hif_sc, 80*5113495bSYour Name qdf_shared_mem_t **ce_sr, 81*5113495bSYour Name uint32_t *sr_ring_size, 82*5113495bSYour Name qdf_dma_addr_t *reg_paddr); 83*5113495bSYour Name void hif_dummy_mask_interrupt_call(struct hif_softc *hif_sc); 84*5113495bSYour Name void hif_dummy_display_stats(struct hif_softc *hif_ctx); 85*5113495bSYour Name void hif_dummy_clear_stats(struct hif_softc *hif_ctx); 86*5113495bSYour Name void hif_dummy_set_bundle_mode(struct hif_softc *hif_ctx, 87*5113495bSYour Name bool enabled, int rx_bundle_cnt); 88*5113495bSYour Name int hif_dummy_bus_reset_resume(struct hif_softc *hif_ctx); 89*5113495bSYour Name int hif_dummy_map_ce_to_irq(struct hif_softc *scn, int ce_id); 90*5113495bSYour Name int hif_dummy_addr_in_boundary(struct hif_softc *scn, uint32_t offset); 91*5113495bSYour Name void hif_dummy_config_irq_affinity(struct hif_softc *scn); 92*5113495bSYour Name int hif_dummy_config_irq_by_ceid(struct hif_softc *scn, int ce_id); 93*5113495bSYour Name bool hif_dummy_log_bus_info(struct hif_softc *scn, uint8_t *data, 94*5113495bSYour Name unsigned int *offset); 95*5113495bSYour Name int hif_dummy_enable_grp_irqs(struct hif_softc *scn); 96*5113495bSYour Name int hif_dummy_disable_grp_irqs(struct hif_softc *scn); 97*5113495bSYour Name void hif_dummy_config_irq_clear_cpu_affinity(struct hif_softc *scn, 98*5113495bSYour Name int intr_ctxt_id, int cpu); 99*5113495bSYour Name #ifdef FEATURE_IRQ_AFFINITY 100*5113495bSYour Name void hif_dummy_set_grp_intr_affinity(struct hif_softc *scn, 101*5113495bSYour Name uint32_t grp_intr_bitmask, bool perf); 102*5113495bSYour Name #endif 103*5113495bSYour Name void hif_dummy_affinity_mgr_set_affinity(struct hif_softc *scn); 104