1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any
6*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above
7*5113495bSYour Name * copyright notice and this permission notice appear in all copies.
8*5113495bSYour Name
9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*5113495bSYour Name */
17*5113495bSYour Name
18*5113495bSYour Name #ifndef __ATH_IPCI_H__
19*5113495bSYour Name #define __ATH_IPCI_H__
20*5113495bSYour Name
21*5113495bSYour Name #include <linux/version.h>
22*5113495bSYour Name #include <linux/semaphore.h>
23*5113495bSYour Name #include <linux/interrupt.h>
24*5113495bSYour Name
25*5113495bSYour Name #define ATH_DBG_DEFAULT 0
26*5113495bSYour Name #define DRAM_SIZE 0x000a8000
27*5113495bSYour Name #include "hif.h"
28*5113495bSYour Name #include "cepci.h"
29*5113495bSYour Name #include "ce_main.h"
30*5113495bSYour Name #include "hif_runtime_pm.h"
31*5113495bSYour Name
32*5113495bSYour Name #ifdef FORCE_WAKE
33*5113495bSYour Name /**
34*5113495bSYour Name * struct hif_ipci_stats - Account for hif pci based statistics
35*5113495bSYour Name * @mhi_force_wake_request_vote: vote for mhi
36*5113495bSYour Name * @mhi_force_wake_failure: mhi force wake failure
37*5113495bSYour Name * @mhi_force_wake_success: mhi force wake success
38*5113495bSYour Name * @soc_force_wake_register_write_success: write to soc wake
39*5113495bSYour Name * @soc_force_wake_failure: soc force wake failure
40*5113495bSYour Name * @soc_force_wake_success: soc force wake success
41*5113495bSYour Name * @mhi_force_wake_release_failure: mhi force wake release failure
42*5113495bSYour Name * @mhi_force_wake_release_success: mhi force wake release success
43*5113495bSYour Name * @soc_force_wake_release_success: soc force wake release
44*5113495bSYour Name */
45*5113495bSYour Name struct hif_ipci_stats {
46*5113495bSYour Name uint32_t mhi_force_wake_request_vote;
47*5113495bSYour Name uint32_t mhi_force_wake_failure;
48*5113495bSYour Name uint32_t mhi_force_wake_success;
49*5113495bSYour Name uint32_t soc_force_wake_register_write_success;
50*5113495bSYour Name uint32_t soc_force_wake_failure;
51*5113495bSYour Name uint32_t soc_force_wake_success;
52*5113495bSYour Name uint32_t mhi_force_wake_release_failure;
53*5113495bSYour Name uint32_t mhi_force_wake_release_success;
54*5113495bSYour Name uint32_t soc_force_wake_release_success;
55*5113495bSYour Name };
56*5113495bSYour Name
57*5113495bSYour Name /* Register offset to wake the UMAC from power collapse */
58*5113495bSYour Name #define PCIE_REG_WAKE_UMAC_OFFSET 0x3004
59*5113495bSYour Name /* Register to wake the UMAC from power collapse */
60*5113495bSYour Name #define PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG (0x01E04000 + 0x40)
61*5113495bSYour Name
62*5113495bSYour Name /* Timeout duration to validate UMAC wake status */
63*5113495bSYour Name #define FORCE_WAKE_DELAY_TIMEOUT_MS 1000
64*5113495bSYour Name
65*5113495bSYour Name /* Validate UMAC status every 5ms */
66*5113495bSYour Name #define FORCE_WAKE_DELAY_MS 5
67*5113495bSYour Name #endif /* FORCE_WAKE */
68*5113495bSYour Name
69*5113495bSYour Name #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
70*5113495bSYour Name defined(FEATURE_HIF_DELAYED_REG_WRITE)
71*5113495bSYour Name #define EP_VOTE_POLL_TIME_US 50
72*5113495bSYour Name #define EP_VOTE_POLL_TIME_CNT 3
73*5113495bSYour Name #ifdef HAL_CONFIG_SLUB_DEBUG_ON
74*5113495bSYour Name #define EP_WAKE_RESET_DELAY_TIMEOUT_MS 3
75*5113495bSYour Name #else
76*5113495bSYour Name #define EP_WAKE_RESET_DELAY_TIMEOUT_MS 10
77*5113495bSYour Name #endif
78*5113495bSYour Name #define EP_WAKE_DELAY_TIMEOUT_MS 10
79*5113495bSYour Name #define EP_WAKE_RESET_DELAY_US 50
80*5113495bSYour Name #define EP_WAKE_DELAY_US 200
81*5113495bSYour Name #endif
82*5113495bSYour Name
83*5113495bSYour Name #if defined(QCA_WIFI_WCN6450)
84*5113495bSYour Name #define HIF_IPCI_DEVICE_ID WCN6450_DEVICE_ID
85*5113495bSYour Name #elif defined(QCA_WIFI_QCA6750)
86*5113495bSYour Name #define HIF_IPCI_DEVICE_ID QCA6750_DEVICE_ID
87*5113495bSYour Name #else
88*5113495bSYour Name #define HIF_IPCI_DEVICE_ID 0
89*5113495bSYour Name #endif
90*5113495bSYour Name
91*5113495bSYour Name struct hif_ipci_softc {
92*5113495bSYour Name struct HIF_CE_state ce_sc;
93*5113495bSYour Name void __iomem *mem; /* PCI address. */
94*5113495bSYour Name
95*5113495bSYour Name struct device *dev; /* For efficiency, should be first in struct */
96*5113495bSYour Name struct tasklet_struct intr_tq; /* tasklet */
97*5113495bSYour Name int ce_msi_irq_num[CE_COUNT_MAX];
98*5113495bSYour Name bool use_register_windowing;
99*5113495bSYour Name uint32_t register_window;
100*5113495bSYour Name qdf_spinlock_t register_access_lock;
101*5113495bSYour Name qdf_spinlock_t irq_lock;
102*5113495bSYour Name bool grp_irqs_disabled;
103*5113495bSYour Name
104*5113495bSYour Name void (*hif_ipci_get_soc_info)(struct hif_ipci_softc *sc,
105*5113495bSYour Name struct device *dev);
106*5113495bSYour Name #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
107*5113495bSYour Name defined(FEATURE_HIF_DELAYED_REG_WRITE)
108*5113495bSYour Name uint32_t ep_awake_reset_fail;
109*5113495bSYour Name uint32_t prevent_l1_fail;
110*5113495bSYour Name uint32_t ep_awake_set_fail;
111*5113495bSYour Name bool prevent_l1;
112*5113495bSYour Name #endif
113*5113495bSYour Name #ifdef FORCE_WAKE
114*5113495bSYour Name struct hif_ipci_stats stats;
115*5113495bSYour Name #endif
116*5113495bSYour Name #ifdef HIF_CPU_PERF_AFFINE_MASK
117*5113495bSYour Name /* Stores the affinity hint mask for each CE IRQ */
118*5113495bSYour Name qdf_cpu_mask ce_irq_cpu_mask[CE_COUNT_MAX];
119*5113495bSYour Name #endif
120*5113495bSYour Name };
121*5113495bSYour Name
122*5113495bSYour Name int hif_configure_irq(struct hif_softc *sc);
123*5113495bSYour Name
124*5113495bSYour Name /*
125*5113495bSYour Name * There may be some pending tx frames during platform suspend.
126*5113495bSYour Name * Suspend operation should be delayed until those tx frames are
127*5113495bSYour Name * transferred from the host to target. This macro specifies how
128*5113495bSYour Name * long suspend thread has to sleep before checking pending tx
129*5113495bSYour Name * frame count.
130*5113495bSYour Name */
131*5113495bSYour Name #define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */
132*5113495bSYour Name
133*5113495bSYour Name #ifdef FORCE_WAKE
134*5113495bSYour Name /**
135*5113495bSYour Name * hif_print_ipci_stats() - Display HIF IPCI stats
136*5113495bSYour Name * @ipci_scn: HIF ipci handle
137*5113495bSYour Name *
138*5113495bSYour Name * Return: None
139*5113495bSYour Name */
140*5113495bSYour Name void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn);
141*5113495bSYour Name #else
142*5113495bSYour Name static inline
hif_print_ipci_stats(struct hif_ipci_softc * ipci_scn)143*5113495bSYour Name void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn)
144*5113495bSYour Name {
145*5113495bSYour Name }
146*5113495bSYour Name #endif /* FORCE_WAKE */
147*5113495bSYour Name
148*5113495bSYour Name #endif /* __IATH_PCI_H__ */
149