1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name #ifndef __HIF_IO32_PCI_H__ 21*5113495bSYour Name #define __HIF_IO32_PCI_H__ 22*5113495bSYour Name 23*5113495bSYour Name #ifdef HIF_PCI 24*5113495bSYour Name 25*5113495bSYour Name #include "hif_main.h" 26*5113495bSYour Name #include "regtable.h" 27*5113495bSYour Name #include "ce_reg.h" 28*5113495bSYour Name #include "qdf_atomic.h" 29*5113495bSYour Name #include "if_pci.h" 30*5113495bSYour Name /* 31*5113495bSYour Name * For maximum performance and no power management, set this to 1. 32*5113495bSYour Name * For power management at the cost of performance, set this to 0. 33*5113495bSYour Name */ 34*5113495bSYour Name #ifndef CONFIG_ATH_PCIE_MAX_PERF 35*5113495bSYour Name #define CONFIG_ATH_PCIE_MAX_PERF 0 36*5113495bSYour Name #endif 37*5113495bSYour Name 38*5113495bSYour Name /* 39*5113495bSYour Name * For keeping the target awake till the driver is 40*5113495bSYour Name * loaded, set this to 1 41*5113495bSYour Name */ 42*5113495bSYour Name #ifndef CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 43*5113495bSYour Name #define CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 1 44*5113495bSYour Name #endif 45*5113495bSYour Name 46*5113495bSYour Name /* 47*5113495bSYour Name * PCI-E L1 ASPPM sub-states 48*5113495bSYour Name * To enable clock gating in L1 state, set this to 1. 49*5113495bSYour Name * (less power, slightly more wakeup latency) 50*5113495bSYour Name * To disable clock gating in L1 state, set this to 0. (slightly more power) 51*5113495bSYour Name */ 52*5113495bSYour Name #define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 1 53*5113495bSYour Name 54*5113495bSYour Name /* 55*5113495bSYour Name * PCIE_ACCESS_LOG_NUM specifies the number of 56*5113495bSYour Name * read/write records to store 57*5113495bSYour Name */ 58*5113495bSYour Name #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 59*5113495bSYour Name #define PCIE_ACCESS_LOG_NUM 500 60*5113495bSYour Name #endif 61*5113495bSYour Name 62*5113495bSYour Name /* 64-bit MSI support */ 63*5113495bSYour Name #define CONFIG_PCIE_64BIT_MSI 0 64*5113495bSYour Name 65*5113495bSYour Name /* BAR0 ready checking for AR6320v2 */ 66*5113495bSYour Name #define PCIE_BAR0_READY_CHECKING 0 67*5113495bSYour Name 68*5113495bSYour Name /* AXI gating when L1, L2 to reduce power consumption */ 69*5113495bSYour Name #define CONFIG_PCIE_ENABLE_AXI_CLK_GATE 0 70*5113495bSYour Name 71*5113495bSYour Name irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 72*5113495bSYour Name #endif /* HIF_PCI */ 73*5113495bSYour Name #endif /* __HIF_IO32_PCI_H__ */ 74