1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2015-2016, 2018-2020 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef __IF_PCI_INTERNAL_H__ 20*5113495bSYour Name #define __IF_PCI_INTERNAL_H__ 21*5113495bSYour Name 22*5113495bSYour Name #ifdef DISABLE_L1SS_STATES 23*5113495bSYour Name #define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr) \ 24*5113495bSYour Name { \ 25*5113495bSYour Name uint32_t lcr_val; \ 26*5113495bSYour Name pfrm_read_config_dword(pdev, addr, &lcr_val); \ 27*5113495bSYour Name pfrm_write_config_dword(pdev, addr, (lcr_val & ~0x0000000f)); \ 28*5113495bSYour Name } 29*5113495bSYour Name #else 30*5113495bSYour Name #define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr) 31*5113495bSYour Name #endif 32*5113495bSYour Name 33*5113495bSYour Name #ifdef QCA_WIFI_3_0 34*5113495bSYour Name #define PCI_CLR_CAUSE0_REGISTER(sc) \ 35*5113495bSYour Name { \ 36*5113495bSYour Name uint32_t tmp_cause0; \ 37*5113495bSYour Name tmp_cause0 = hif_read32_mb(sc, sc->mem + PCIE_INTR_CAUSE_ADDRESS); \ 38*5113495bSYour Name hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, \ 39*5113495bSYour Name PCIE_INTR_FIRMWARE_MASK | tmp_cause0); \ 40*5113495bSYour Name hif_read32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS); \ 41*5113495bSYour Name hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, 0); \ 42*5113495bSYour Name hif_read32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS); \ 43*5113495bSYour Name } 44*5113495bSYour Name #else 45*5113495bSYour Name #define PCI_CLR_CAUSE0_REGISTER(sc) 46*5113495bSYour Name #endif 47*5113495bSYour Name #endif /* __IF_PCI_INTERNAL_H__ */ 48