1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2015,2016,2018 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name #include "qdf_module.h" 19*5113495bSYour Name 20*5113495bSYour Name #if defined(QCA9888_HEADERS_DEF) 21*5113495bSYour Name #define QCA9888 1 22*5113495bSYour Name 23*5113495bSYour Name #define WLAN_HEADERS 1 24*5113495bSYour Name #include "common_drv.h" 25*5113495bSYour Name #include "QCA9888/v2/soc_addrs.h" 26*5113495bSYour Name #include "QCA9888/v2/extra/hw/apb_map.h" 27*5113495bSYour Name #include "QCA9888/v2/hw/gpio_athr_wlan_reg.h" 28*5113495bSYour Name #ifdef WLAN_HEADERS 29*5113495bSYour Name 30*5113495bSYour Name #include "QCA9888/v2/extra/hw/wifi_top_reg_map.h" 31*5113495bSYour Name #include "QCA9888/v2/hw/rtc_soc_reg.h" 32*5113495bSYour Name 33*5113495bSYour Name #endif 34*5113495bSYour Name #include "QCA9888/v2/hw/si_reg.h" 35*5113495bSYour Name #include "QCA9888/v2/extra/hw/pcie_local_reg.h" 36*5113495bSYour Name #include "QCA9888/v2/hw/ce_wrapper_reg_csr.h" 37*5113495bSYour Name 38*5113495bSYour Name #include "QCA9888/v2/extra/hw/soc_core_reg.h" 39*5113495bSYour Name #include "QCA9888/v2/hw/soc_pcie_reg.h" 40*5113495bSYour Name #include "QCA9888/v2/extra/hw/ce_reg_csr.h" 41*5113495bSYour Name #include <QCA9888/v2/hw/interface/rx_location_info.h> 42*5113495bSYour Name #include <QCA9888/v2/hw/interface/rx_pkt_end.h> 43*5113495bSYour Name #include <QCA9888/v2/hw/interface/rx_phy_ppdu_end.h> 44*5113495bSYour Name #include <QCA9888/v2/hw/interface/rx_timing_offset.h> 45*5113495bSYour Name #include <QCA9888/v2/hw/interface/rx_location_info.h> 46*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_ppdu_start.h> 47*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_ppdu_end.h> 48*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_mpdu_start.h> 49*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_mpdu_end.h> 50*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_msdu_start.h> 51*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_msdu_end.h> 52*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_attention.h> 53*5113495bSYour Name #include <QCA9888/v2/hw/tlv/rx_frag_info.h> 54*5113495bSYour Name #include <QCA9888/v2/hw/datastruct/msdu_link_ext.h> 55*5113495bSYour Name #include <QCA9888/v2/hw/emu_phy_reg.h> 56*5113495bSYour Name 57*5113495bSYour Name /* Base address is defined in pcie_local_reg.h. Macros which access the 58*5113495bSYour Name * registers include the base address in their definition. 59*5113495bSYour Name */ 60*5113495bSYour Name #define PCIE_LOCAL_BASE_ADDRESS 0 61*5113495bSYour Name 62*5113495bSYour Name #define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS) 63*5113495bSYour Name #define DRAM_BASE_ADDRESS TARG_DRAM_START 64*5113495bSYour Name 65*5113495bSYour Name /* Backwards compatibility -- TBDXXX */ 66*5113495bSYour Name 67*5113495bSYour Name #define MISSING 0 68*5113495bSYour Name 69*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB 70*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK 71*5113495bSYour Name #define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK 72*5113495bSYour Name #define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK 73*5113495bSYour Name #define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS 74*5113495bSYour Name #define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS 75*5113495bSYour Name #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS 76*5113495bSYour Name #define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS 77*5113495bSYour Name #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK 78*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS 79*5113495bSYour Name #define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS 80*5113495bSYour Name #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 81*5113495bSYour Name #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 82*5113495bSYour Name #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 83*5113495bSYour Name #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 84*5113495bSYour Name #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 85*5113495bSYour Name #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 86*5113495bSYour Name #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 87*5113495bSYour Name #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 88*5113495bSYour Name #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 89*5113495bSYour Name #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 90*5113495bSYour Name #define LOCAL_SCRATCH_OFFSET 0x18 91*5113495bSYour Name #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 92*5113495bSYour Name #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 93*5113495bSYour Name #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 94*5113495bSYour Name #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 95*5113495bSYour Name #define SI_CONFIG_OFFSET SI_CONFIG_ADDRESS 96*5113495bSYour Name #define SI_TX_DATA0_OFFSET SI_TX_DATA0_ADDRESS 97*5113495bSYour Name #define SI_TX_DATA1_OFFSET SI_TX_DATA1_ADDRESS 98*5113495bSYour Name #define SI_RX_DATA0_OFFSET SI_RX_DATA0_ADDRESS 99*5113495bSYour Name #define SI_RX_DATA1_OFFSET SI_RX_DATA1_ADDRESS 100*5113495bSYour Name #define SI_CS_OFFSET SI_CS_ADDRESS 101*5113495bSYour Name #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 102*5113495bSYour Name #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 103*5113495bSYour Name #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 104*5113495bSYour Name #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 105*5113495bSYour Name #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 106*5113495bSYour Name #define MBOX_BASE_ADDRESS MISSING 107*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_LSB MISSING 108*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_MASK MISSING 109*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_LSB MISSING 110*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_MASK MISSING 111*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 112*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 113*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 114*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 115*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 116*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 117*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 118*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 119*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 120*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 121*5113495bSYour Name #define INT_STATUS_ENABLE_ADDRESS MISSING 122*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 123*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 124*5113495bSYour Name #define HOST_INT_STATUS_ADDRESS MISSING 125*5113495bSYour Name #define CPU_INT_STATUS_ADDRESS MISSING 126*5113495bSYour Name #define ERROR_INT_STATUS_ADDRESS MISSING 127*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 128*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 129*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 130*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 131*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 132*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 133*5113495bSYour Name #define COUNT_DEC_ADDRESS MISSING 134*5113495bSYour Name #define HOST_INT_STATUS_CPU_MASK MISSING 135*5113495bSYour Name #define HOST_INT_STATUS_CPU_LSB MISSING 136*5113495bSYour Name #define HOST_INT_STATUS_ERROR_MASK MISSING 137*5113495bSYour Name #define HOST_INT_STATUS_ERROR_LSB MISSING 138*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_MASK MISSING 139*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_LSB MISSING 140*5113495bSYour Name #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 141*5113495bSYour Name #define WINDOW_DATA_ADDRESS MISSING 142*5113495bSYour Name #define WINDOW_READ_ADDR_ADDRESS MISSING 143*5113495bSYour Name #define WINDOW_WRITE_ADDR_ADDRESS MISSING 144*5113495bSYour Name /* MAC Descriptor */ 145*5113495bSYour Name #define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2) 146*5113495bSYour Name /* GPIO Register */ 147*5113495bSYour Name #define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS 148*5113495bSYour Name #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 149*5113495bSYour Name #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 150*5113495bSYour Name #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 151*5113495bSYour Name /* CE descriptor */ 152*5113495bSYour Name #define CE_SRC_DESC_SIZE_DWORD 2 153*5113495bSYour Name #define CE_DEST_DESC_SIZE_DWORD 2 154*5113495bSYour Name #define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 155*5113495bSYour Name #define CE_SRC_DESC_INFO_OFFSET_DWORD 1 156*5113495bSYour Name #define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 157*5113495bSYour Name #define CE_DEST_DESC_INFO_OFFSET_DWORD 1 158*5113495bSYour Name #if _BYTE_ORDER == _BIG_ENDIAN 159*5113495bSYour Name #define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 160*5113495bSYour Name #define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 161*5113495bSYour Name #define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 162*5113495bSYour Name #define CE_SRC_DESC_INFO_GATHER_SHIFT 15 163*5113495bSYour Name #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 164*5113495bSYour Name #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 165*5113495bSYour Name #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 166*5113495bSYour Name #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 167*5113495bSYour Name #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 168*5113495bSYour Name #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 169*5113495bSYour Name #define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF 170*5113495bSYour Name #define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 171*5113495bSYour Name #else 172*5113495bSYour Name #define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF 173*5113495bSYour Name #define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 174*5113495bSYour Name #define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 175*5113495bSYour Name #define CE_SRC_DESC_INFO_GATHER_SHIFT 16 176*5113495bSYour Name #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 177*5113495bSYour Name #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 178*5113495bSYour Name #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 179*5113495bSYour Name #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 180*5113495bSYour Name #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 181*5113495bSYour Name #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 182*5113495bSYour Name #define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000 183*5113495bSYour Name #define CE_SRC_DESC_INFO_META_DATA_SHIFT 20 184*5113495bSYour Name #endif 185*5113495bSYour Name #if _BYTE_ORDER == _BIG_ENDIAN 186*5113495bSYour Name #define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 187*5113495bSYour Name #define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 188*5113495bSYour Name #define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 189*5113495bSYour Name #define CE_DEST_DESC_INFO_GATHER_SHIFT 15 190*5113495bSYour Name #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 191*5113495bSYour Name #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 192*5113495bSYour Name #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 193*5113495bSYour Name #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 194*5113495bSYour Name #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 195*5113495bSYour Name #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 196*5113495bSYour Name #define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF 197*5113495bSYour Name #define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 198*5113495bSYour Name #else 199*5113495bSYour Name #define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF 200*5113495bSYour Name #define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 201*5113495bSYour Name #define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 202*5113495bSYour Name #define CE_DEST_DESC_INFO_GATHER_SHIFT 16 203*5113495bSYour Name #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 204*5113495bSYour Name #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 205*5113495bSYour Name #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 206*5113495bSYour Name #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 207*5113495bSYour Name #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 208*5113495bSYour Name #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 209*5113495bSYour Name #define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000 210*5113495bSYour Name #define CE_DEST_DESC_INFO_META_DATA_SHIFT 20 211*5113495bSYour Name #endif 212*5113495bSYour Name 213*5113495bSYour Name #define MY_TARGET_DEF QCA9888_TARGETdef 214*5113495bSYour Name #define MY_HOST_DEF QCA9888_HOSTdef 215*5113495bSYour Name #define MY_CEREG_DEF QCA9888_CE_TARGETdef 216*5113495bSYour Name #define MY_TARGET_BOARD_DATA_SZ QCA9888_BOARD_DATA_SZ 217*5113495bSYour Name #define MY_TARGET_BOARD_EXT_DATA_SZ QCA9888_BOARD_EXT_DATA_SZ 218*5113495bSYour Name #include "targetdef.h" 219*5113495bSYour Name #include "hostdef.h" 220*5113495bSYour Name qdf_export_symbol(QCA9888_CE_TARGETdef); 221*5113495bSYour Name #else 222*5113495bSYour Name #include "common_drv.h" 223*5113495bSYour Name #include "targetdef.h" 224*5113495bSYour Name #include "hostdef.h" 225*5113495bSYour Name struct targetdef_s *QCA9888_TARGETdef; 226*5113495bSYour Name struct hostdef_s *QCA9888_HOSTdef; 227*5113495bSYour Name #endif /* QCA9888_HEADERS_DEF */ 228*5113495bSYour Name qdf_export_symbol(QCA9888_TARGETdef); 229*5113495bSYour Name qdf_export_symbol(QCA9888_HOSTdef); 230