xref: /wlan-driver/qca-wifi-host-cmn/hif/src/qca9888def.c (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2015,2016,2018 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 #include "qdf_module.h"
19 
20 #if defined(QCA9888_HEADERS_DEF)
21 #define QCA9888 1
22 
23 #define WLAN_HEADERS 1
24 #include "common_drv.h"
25 #include "QCA9888/v2/soc_addrs.h"
26 #include "QCA9888/v2/extra/hw/apb_map.h"
27 #include "QCA9888/v2/hw/gpio_athr_wlan_reg.h"
28 #ifdef WLAN_HEADERS
29 
30 #include "QCA9888/v2/extra/hw/wifi_top_reg_map.h"
31 #include "QCA9888/v2/hw/rtc_soc_reg.h"
32 
33 #endif
34 #include "QCA9888/v2/hw/si_reg.h"
35 #include "QCA9888/v2/extra/hw/pcie_local_reg.h"
36 #include "QCA9888/v2/hw/ce_wrapper_reg_csr.h"
37 
38 #include "QCA9888/v2/extra/hw/soc_core_reg.h"
39 #include "QCA9888/v2/hw/soc_pcie_reg.h"
40 #include "QCA9888/v2/extra/hw/ce_reg_csr.h"
41 #include <QCA9888/v2/hw/interface/rx_location_info.h>
42 #include <QCA9888/v2/hw/interface/rx_pkt_end.h>
43 #include <QCA9888/v2/hw/interface/rx_phy_ppdu_end.h>
44 #include <QCA9888/v2/hw/interface/rx_timing_offset.h>
45 #include <QCA9888/v2/hw/interface/rx_location_info.h>
46 #include <QCA9888/v2/hw/tlv/rx_ppdu_start.h>
47 #include <QCA9888/v2/hw/tlv/rx_ppdu_end.h>
48 #include <QCA9888/v2/hw/tlv/rx_mpdu_start.h>
49 #include <QCA9888/v2/hw/tlv/rx_mpdu_end.h>
50 #include <QCA9888/v2/hw/tlv/rx_msdu_start.h>
51 #include <QCA9888/v2/hw/tlv/rx_msdu_end.h>
52 #include <QCA9888/v2/hw/tlv/rx_attention.h>
53 #include <QCA9888/v2/hw/tlv/rx_frag_info.h>
54 #include <QCA9888/v2/hw/datastruct/msdu_link_ext.h>
55 #include <QCA9888/v2/hw/emu_phy_reg.h>
56 
57 /* Base address is defined in pcie_local_reg.h. Macros which access the
58  * registers include the base address in their definition.
59  */
60 #define PCIE_LOCAL_BASE_ADDRESS 0
61 
62 #define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS)
63 #define DRAM_BASE_ADDRESS TARG_DRAM_START
64 
65 /* Backwards compatibility -- TBDXXX */
66 
67 #define MISSING 0
68 
69 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB           WIFI_SYSTEM_SLEEP_DISABLE_LSB
70 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK          WIFI_SYSTEM_SLEEP_DISABLE_MASK
71 #define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK
72 #define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK
73 #define SOC_CLOCK_CONTROL_OFFSET                SOC_CLOCK_CONTROL_ADDRESS
74 #define SOC_RESET_CONTROL_OFFSET                SOC_RESET_CONTROL_ADDRESS
75 #define CPU_CLOCK_OFFSET                        SOC_CPU_CLOCK_ADDRESS
76 #define SOC_LPO_CAL_OFFSET                      SOC_LPO_CAL_ADDRESS
77 #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK
78 #define WLAN_SYSTEM_SLEEP_OFFSET                WIFI_SYSTEM_SLEEP_ADDRESS
79 #define WLAN_RESET_CONTROL_OFFSET               WIFI_RESET_CONTROL_ADDRESS
80 #define CLOCK_CONTROL_OFFSET                    SOC_CLOCK_CONTROL_OFFSET
81 #define CLOCK_CONTROL_SI0_CLK_MASK              SOC_CLOCK_CONTROL_SI0_CLK_MASK
82 #define RESET_CONTROL_SI0_RST_MASK              SOC_RESET_CONTROL_SI0_RST_MASK
83 #define GPIO_BASE_ADDRESS                       WLAN_GPIO_BASE_ADDRESS
84 #define GPIO_PIN0_OFFSET                        WLAN_GPIO_PIN0_ADDRESS
85 #define GPIO_PIN1_OFFSET                        WLAN_GPIO_PIN1_ADDRESS
86 #define GPIO_PIN0_CONFIG_MASK                   WLAN_GPIO_PIN0_CONFIG_MASK
87 #define GPIO_PIN1_CONFIG_MASK                   WLAN_GPIO_PIN1_CONFIG_MASK
88 #define SI_BASE_ADDRESS                         WLAN_SI_BASE_ADDRESS
89 #define SCRATCH_BASE_ADDRESS                    SOC_CORE_BASE_ADDRESS
90 #define LOCAL_SCRATCH_OFFSET                    0x18
91 #define GPIO_PIN10_OFFSET                       WLAN_GPIO_PIN10_ADDRESS
92 #define GPIO_PIN11_OFFSET                       WLAN_GPIO_PIN11_ADDRESS
93 #define GPIO_PIN12_OFFSET                       WLAN_GPIO_PIN12_ADDRESS
94 #define GPIO_PIN13_OFFSET                       WLAN_GPIO_PIN13_ADDRESS
95 #define SI_CONFIG_OFFSET                        SI_CONFIG_ADDRESS
96 #define SI_TX_DATA0_OFFSET                      SI_TX_DATA0_ADDRESS
97 #define SI_TX_DATA1_OFFSET                      SI_TX_DATA1_ADDRESS
98 #define SI_RX_DATA0_OFFSET                      SI_RX_DATA0_ADDRESS
99 #define SI_RX_DATA1_OFFSET                      SI_RX_DATA1_ADDRESS
100 #define SI_CS_OFFSET                            SI_CS_ADDRESS
101 #define CPU_CLOCK_STANDARD_LSB                  SOC_CPU_CLOCK_STANDARD_LSB
102 #define CPU_CLOCK_STANDARD_MASK                 SOC_CPU_CLOCK_STANDARD_MASK
103 #define LPO_CAL_ENABLE_LSB                      SOC_LPO_CAL_ENABLE_LSB
104 #define LPO_CAL_ENABLE_MASK                     SOC_LPO_CAL_ENABLE_MASK
105 #define ANALOG_INTF_BASE_ADDRESS                WLAN_ANALOG_INTF_BASE_ADDRESS
106 #define MBOX_BASE_ADDRESS                       MISSING
107 #define INT_STATUS_ENABLE_ERROR_LSB             MISSING
108 #define INT_STATUS_ENABLE_ERROR_MASK            MISSING
109 #define INT_STATUS_ENABLE_CPU_LSB               MISSING
110 #define INT_STATUS_ENABLE_CPU_MASK              MISSING
111 #define INT_STATUS_ENABLE_COUNTER_LSB           MISSING
112 #define INT_STATUS_ENABLE_COUNTER_MASK          MISSING
113 #define INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
114 #define INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
115 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
116 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
117 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
118 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
119 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
120 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
121 #define INT_STATUS_ENABLE_ADDRESS               MISSING
122 #define CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
123 #define CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
124 #define HOST_INT_STATUS_ADDRESS                 MISSING
125 #define CPU_INT_STATUS_ADDRESS                  MISSING
126 #define ERROR_INT_STATUS_ADDRESS                MISSING
127 #define ERROR_INT_STATUS_WAKEUP_MASK            MISSING
128 #define ERROR_INT_STATUS_WAKEUP_LSB             MISSING
129 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
130 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
131 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
132 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
133 #define COUNT_DEC_ADDRESS                       MISSING
134 #define HOST_INT_STATUS_CPU_MASK                MISSING
135 #define HOST_INT_STATUS_CPU_LSB                 MISSING
136 #define HOST_INT_STATUS_ERROR_MASK              MISSING
137 #define HOST_INT_STATUS_ERROR_LSB               MISSING
138 #define HOST_INT_STATUS_COUNTER_MASK            MISSING
139 #define HOST_INT_STATUS_COUNTER_LSB             MISSING
140 #define RX_LOOKAHEAD_VALID_ADDRESS              MISSING
141 #define WINDOW_DATA_ADDRESS                     MISSING
142 #define WINDOW_READ_ADDR_ADDRESS                MISSING
143 #define WINDOW_WRITE_ADDR_ADDRESS               MISSING
144 /* MAC Descriptor */
145 #define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2)
146 /* GPIO Register */
147 #define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS
148 #define GPIO_PIN0_CONFIG_LSB                    WLAN_GPIO_PIN0_CONFIG_LSB
149 #define GPIO_PIN0_PAD_PULL_LSB                  WLAN_GPIO_PIN0_PAD_PULL_LSB
150 #define GPIO_PIN0_PAD_PULL_MASK                 WLAN_GPIO_PIN0_PAD_PULL_MASK
151 /* CE descriptor */
152 #define CE_SRC_DESC_SIZE_DWORD         2
153 #define CE_DEST_DESC_SIZE_DWORD        2
154 #define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD    0
155 #define CE_SRC_DESC_INFO_OFFSET_DWORD       1
156 #define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD  0
157 #define CE_DEST_DESC_INFO_OFFSET_DWORD      1
158 #if _BYTE_ORDER == _BIG_ENDIAN
159 #define CE_SRC_DESC_INFO_NBYTES_MASK               0xFFFF0000
160 #define CE_SRC_DESC_INFO_NBYTES_SHIFT              16
161 #define CE_SRC_DESC_INFO_GATHER_MASK               0x00008000
162 #define CE_SRC_DESC_INFO_GATHER_SHIFT              15
163 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK            0x00004000
164 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT           14
165 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK     0x00002000
166 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT    13
167 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK   0x00001000
168 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT  12
169 #define CE_SRC_DESC_INFO_META_DATA_MASK            0x00000FFF
170 #define CE_SRC_DESC_INFO_META_DATA_SHIFT           0
171 #else
172 #define CE_SRC_DESC_INFO_NBYTES_MASK               0x0000FFFF
173 #define CE_SRC_DESC_INFO_NBYTES_SHIFT              0
174 #define CE_SRC_DESC_INFO_GATHER_MASK               0x00010000
175 #define CE_SRC_DESC_INFO_GATHER_SHIFT              16
176 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK            0x00020000
177 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT           17
178 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK     0x00040000
179 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT    18
180 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK   0x00080000
181 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT  19
182 #define CE_SRC_DESC_INFO_META_DATA_MASK            0xFFF00000
183 #define CE_SRC_DESC_INFO_META_DATA_SHIFT           20
184 #endif
185 #if _BYTE_ORDER == _BIG_ENDIAN
186 #define CE_DEST_DESC_INFO_NBYTES_MASK              0xFFFF0000
187 #define CE_DEST_DESC_INFO_NBYTES_SHIFT             16
188 #define CE_DEST_DESC_INFO_GATHER_MASK              0x00008000
189 #define CE_DEST_DESC_INFO_GATHER_SHIFT             15
190 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK           0x00004000
191 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT          14
192 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK    0x00002000
193 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT   13
194 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK  0x00001000
195 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12
196 #define CE_DEST_DESC_INFO_META_DATA_MASK           0x00000FFF
197 #define CE_DEST_DESC_INFO_META_DATA_SHIFT          0
198 #else
199 #define CE_DEST_DESC_INFO_NBYTES_MASK              0x0000FFFF
200 #define CE_DEST_DESC_INFO_NBYTES_SHIFT             0
201 #define CE_DEST_DESC_INFO_GATHER_MASK              0x00010000
202 #define CE_DEST_DESC_INFO_GATHER_SHIFT             16
203 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK           0x00020000
204 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT          17
205 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK    0x00040000
206 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT   18
207 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK  0x00080000
208 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19
209 #define CE_DEST_DESC_INFO_META_DATA_MASK           0xFFF00000
210 #define CE_DEST_DESC_INFO_META_DATA_SHIFT          20
211 #endif
212 
213 #define MY_TARGET_DEF QCA9888_TARGETdef
214 #define MY_HOST_DEF QCA9888_HOSTdef
215 #define MY_CEREG_DEF QCA9888_CE_TARGETdef
216 #define MY_TARGET_BOARD_DATA_SZ QCA9888_BOARD_DATA_SZ
217 #define MY_TARGET_BOARD_EXT_DATA_SZ QCA9888_BOARD_EXT_DATA_SZ
218 #include "targetdef.h"
219 #include "hostdef.h"
220 qdf_export_symbol(QCA9888_CE_TARGETdef);
221 #else
222 #include "common_drv.h"
223 #include "targetdef.h"
224 #include "hostdef.h"
225 struct targetdef_s *QCA9888_TARGETdef;
226 struct hostdef_s *QCA9888_HOSTdef;
227 #endif /* QCA9888_HEADERS_DEF */
228 qdf_export_symbol(QCA9888_TARGETdef);
229 qdf_export_symbol(QCA9888_HOSTdef);
230