xref: /wlan-driver/qca-wifi-host-cmn/hif/src/qcn9224def.c (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #include "qdf_module.h"
20 
21 #if defined(QCN9224_HEADERS_DEF)
22 
23 #undef UMAC
24 #define WLAN_HEADERS 1
25 
26 #include "wcss_version.h"
27 #include "wcss_seq_hwiobase.h"
28 #include "wfss_ce_reg_seq_hwioreg.h"
29 
30 #define MISSING 0
31 
32 #define SOC_RESET_CONTROL_OFFSET MISSING
33 #define GPIO_PIN0_OFFSET                        MISSING
34 #define GPIO_PIN1_OFFSET                        MISSING
35 #define GPIO_PIN0_CONFIG_MASK                   MISSING
36 #define GPIO_PIN1_CONFIG_MASK                   MISSING
37 #define LOCAL_SCRATCH_OFFSET 0x18
38 #define GPIO_PIN10_OFFSET MISSING
39 #define GPIO_PIN11_OFFSET MISSING
40 #define GPIO_PIN12_OFFSET MISSING
41 #define GPIO_PIN13_OFFSET MISSING
42 #define MBOX_BASE_ADDRESS MISSING
43 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
44 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
45 #define INT_STATUS_ENABLE_CPU_LSB MISSING
46 #define INT_STATUS_ENABLE_CPU_MASK MISSING
47 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
48 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
49 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
50 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
51 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
52 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
53 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
54 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
55 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
56 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
57 #define INT_STATUS_ENABLE_ADDRESS MISSING
58 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
59 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
60 #define HOST_INT_STATUS_ADDRESS MISSING
61 #define CPU_INT_STATUS_ADDRESS MISSING
62 #define ERROR_INT_STATUS_ADDRESS MISSING
63 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
64 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
65 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
66 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
67 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
68 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
69 #define COUNT_DEC_ADDRESS MISSING
70 #define HOST_INT_STATUS_CPU_MASK MISSING
71 #define HOST_INT_STATUS_CPU_LSB MISSING
72 #define HOST_INT_STATUS_ERROR_MASK MISSING
73 #define HOST_INT_STATUS_ERROR_LSB MISSING
74 #define HOST_INT_STATUS_COUNTER_MASK MISSING
75 #define HOST_INT_STATUS_COUNTER_LSB MISSING
76 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
77 #define WINDOW_DATA_ADDRESS MISSING
78 #define WINDOW_READ_ADDR_ADDRESS MISSING
79 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
80 /* GPIO Register */
81 #define GPIO_ENABLE_W1TS_LOW_ADDRESS            MISSING
82 #define GPIO_PIN0_CONFIG_LSB                    MISSING
83 #define GPIO_PIN0_PAD_PULL_LSB                  MISSING
84 #define GPIO_PIN0_PAD_PULL_MASK                 MISSING
85 /* SI reg */
86 #define SI_CONFIG_ERR_INT_MASK                  MISSING
87 #define SI_CONFIG_ERR_INT_LSB                   MISSING
88 
89 #define RTC_SOC_BASE_ADDRESS MISSING
90 #define RTC_WMAC_BASE_ADDRESS MISSING
91 #define SOC_CORE_BASE_ADDRESS MISSING
92 #define WLAN_MAC_BASE_ADDRESS MISSING
93 #define GPIO_BASE_ADDRESS MISSING
94 #define ANALOG_INTF_BASE_ADDRESS MISSING
95 #define CE0_BASE_ADDRESS MISSING
96 #define CE1_BASE_ADDRESS MISSING
97 #define CE_COUNT 16
98 #define CE_WRAPPER_BASE_ADDRESS MISSING
99 #define SI_BASE_ADDRESS MISSING
100 #define DRAM_BASE_ADDRESS MISSING
101 
102 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
103 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
104 #define CLOCK_CONTROL_OFFSET MISSING
105 #define CLOCK_CONTROL_SI0_CLK_MASK MISSING
106 #define RESET_CONTROL_SI0_RST_MASK MISSING
107 #define WLAN_RESET_CONTROL_OFFSET MISSING
108 #define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
109 #define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
110 #define CPU_CLOCK_OFFSET MISSING
111 
112 #define CPU_CLOCK_STANDARD_LSB MISSING
113 #define CPU_CLOCK_STANDARD_MASK MISSING
114 #define LPO_CAL_ENABLE_LSB MISSING
115 #define LPO_CAL_ENABLE_MASK MISSING
116 #define WLAN_SYSTEM_SLEEP_OFFSET MISSING
117 
118 #define SOC_CHIP_ID_ADDRESS	  MISSING
119 #define SOC_CHIP_ID_REVISION_MASK MISSING
120 #define SOC_CHIP_ID_REVISION_LSB  MISSING
121 #define SOC_CHIP_ID_REVISION_MSB  MISSING
122 
123 #define FW_IND_EVENT_PENDING MISSING
124 #define FW_IND_INITIALIZED MISSING
125 
126 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
127 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
128 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
129 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
130 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
131 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
132 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
133 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
134 
135 #define SR_WR_INDEX_ADDRESS MISSING
136 #define DST_WATERMARK_ADDRESS MISSING
137 
138 #define DST_WR_INDEX_ADDRESS MISSING
139 #define SRC_WATERMARK_ADDRESS MISSING
140 #define SRC_WATERMARK_LOW_MASK MISSING
141 #define SRC_WATERMARK_HIGH_MASK MISSING
142 #define DST_WATERMARK_LOW_MASK MISSING
143 #define DST_WATERMARK_HIGH_MASK MISSING
144 #define CURRENT_SRRI_ADDRESS MISSING
145 #define CURRENT_DRRI_ADDRESS MISSING
146 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
147 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
148 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
149 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
150 #define HOST_IS_ADDRESS MISSING
151 #define MISC_IS_ADDRESS MISSING
152 #define HOST_IS_COPY_COMPLETE_MASK MISSING
153 #define CE_WRAPPER_BASE_ADDRESS MISSING
154 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
155 #define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
156 #define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
157 
158 #define HOST_IE_ADDRESS \
159 	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
160 		WFSS_CE_COMMON_REG_REG_BASE)
161 #define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
162 #define HOST_IE_ADDRESS_2 \
163 	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
164 		WFSS_CE_COMMON_REG_REG_BASE)
165 #define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
166 #define HOST_IE_ADDRESS_3 \
167 	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
168 		WFSS_CE_COMMON_REG_REG_BASE)
169 #define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
170 
171 #define HOST_IE_COPY_COMPLETE_MASK MISSING
172 #define SR_BA_ADDRESS MISSING
173 #define SR_BA_ADDRESS_HIGH MISSING
174 #define SR_SIZE_ADDRESS MISSING
175 #define CE_CTRL1_ADDRESS MISSING
176 #define CE_CTRL1_DMAX_LENGTH_MASK MISSING
177 #define DR_BA_ADDRESS MISSING
178 #define DR_BA_ADDRESS_HIGH MISSING
179 #define DR_SIZE_ADDRESS MISSING
180 #define CE_CMD_REGISTER MISSING
181 #define CE_MSI_ADDRESS MISSING
182 #define CE_MSI_ADDRESS_HIGH MISSING
183 #define CE_MSI_DATA MISSING
184 #define CE_MSI_ENABLE_BIT MISSING
185 #define MISC_IE_ADDRESS MISSING
186 #define MISC_IS_AXI_ERR_MASK MISSING
187 #define MISC_IS_DST_ADDR_ERR_MASK MISSING
188 #define MISC_IS_SRC_LEN_ERR_MASK MISSING
189 #define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
190 #define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
191 #define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
192 #define SRC_WATERMARK_LOW_LSB MISSING
193 #define SRC_WATERMARK_HIGH_LSB MISSING
194 #define DST_WATERMARK_LOW_LSB MISSING
195 #define DST_WATERMARK_HIGH_LSB MISSING
196 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
197 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
198 #define CE_CTRL1_DMAX_LENGTH_LSB MISSING
199 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
200 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
201 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
202 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
203 #define CE_CTRL1_IDX_UPD_EN_MASK MISSING
204 #define CE_WRAPPER_DEBUG_OFFSET MISSING
205 #define CE_WRAPPER_DEBUG_SEL_MSB MISSING
206 #define CE_WRAPPER_DEBUG_SEL_LSB MISSING
207 #define CE_WRAPPER_DEBUG_SEL_MASK MISSING
208 #define CE_DEBUG_OFFSET MISSING
209 #define CE_DEBUG_SEL_MSB MISSING
210 #define CE_DEBUG_SEL_LSB MISSING
211 #define CE_DEBUG_SEL_MASK MISSING
212 #define CE0_BASE_ADDRESS MISSING
213 #define CE1_BASE_ADDRESS MISSING
214 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
215 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
216 
217 #define QCN9224_BOARD_DATA_SZ MISSING
218 #define QCN9224_BOARD_EXT_DATA_SZ MISSING
219 
220 #define MY_TARGET_DEF QCN9224_TARGETDEF
221 #define MY_HOST_DEF QCN9224_HOSTDEF
222 #define MY_CEREG_DEF QCN9224_CE_TARGETDEF
223 #define MY_TARGET_BOARD_DATA_SZ QCN9224_BOARD_DATA_SZ
224 #define MY_TARGET_BOARD_EXT_DATA_SZ QCN9224_BOARD_EXT_DATA_SZ
225 #include "targetdef.h"
226 #include "hostdef.h"
227 qdf_export_symbol(QCN9224_CE_TARGETDEF);
228 #else
229 #include "common_drv.h"
230 #include "targetdef.h"
231 #include "hostdef.h"
232 struct targetdef_s *QCN9224_TARGETDEF;
233 struct hostdef_s *QCN9224_HOSTDEF;
234 #endif /*QCN9224_HEADERS_DEF */
235 qdf_export_symbol(QCN9224_TARGETDEF);
236 qdf_export_symbol(QCN9224_HOSTDEF);
237