1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _REGTABLE_SDIO_H_ 20*5113495bSYour Name #define _REGTABLE_SDIO_H_ 21*5113495bSYour Name 22*5113495bSYour Name #define MISSING 0 23*5113495bSYour Name extern struct hif_sdio_softc *scn; 24*5113495bSYour Name 25*5113495bSYour Name struct targetdef_s { 26*5113495bSYour Name uint32_t d_RTC_SOC_BASE_ADDRESS; 27*5113495bSYour Name uint32_t d_RTC_WMAC_BASE_ADDRESS; 28*5113495bSYour Name uint32_t d_SYSTEM_SLEEP_OFFSET; 29*5113495bSYour Name uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET; 30*5113495bSYour Name uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; 31*5113495bSYour Name uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; 32*5113495bSYour Name uint32_t d_CLOCK_CONTROL_OFFSET; 33*5113495bSYour Name uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK; 34*5113495bSYour Name uint32_t d_RESET_CONTROL_OFFSET; 35*5113495bSYour Name uint32_t d_RESET_CONTROL_MBOX_RST_MASK; 36*5113495bSYour Name uint32_t d_RESET_CONTROL_SI0_RST_MASK; 37*5113495bSYour Name uint32_t d_WLAN_RESET_CONTROL_OFFSET; 38*5113495bSYour Name uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; 39*5113495bSYour Name uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; 40*5113495bSYour Name uint32_t d_GPIO_BASE_ADDRESS; 41*5113495bSYour Name uint32_t d_GPIO_PIN0_OFFSET; 42*5113495bSYour Name uint32_t d_GPIO_PIN1_OFFSET; 43*5113495bSYour Name uint32_t d_GPIO_PIN0_CONFIG_MASK; 44*5113495bSYour Name uint32_t d_GPIO_PIN1_CONFIG_MASK; 45*5113495bSYour Name uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; 46*5113495bSYour Name uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; 47*5113495bSYour Name uint32_t d_SI_CONFIG_I2C_LSB; 48*5113495bSYour Name uint32_t d_SI_CONFIG_I2C_MASK; 49*5113495bSYour Name uint32_t d_SI_CONFIG_POS_SAMPLE_LSB; 50*5113495bSYour Name uint32_t d_SI_CONFIG_POS_SAMPLE_MASK; 51*5113495bSYour Name uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB; 52*5113495bSYour Name uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK; 53*5113495bSYour Name uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB; 54*5113495bSYour Name uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK; 55*5113495bSYour Name uint32_t d_SI_CONFIG_DIVIDER_LSB; 56*5113495bSYour Name uint32_t d_SI_CONFIG_DIVIDER_MASK; 57*5113495bSYour Name uint32_t d_SI_BASE_ADDRESS; 58*5113495bSYour Name uint32_t d_SI_CONFIG_OFFSET; 59*5113495bSYour Name uint32_t d_SI_TX_DATA0_OFFSET; 60*5113495bSYour Name uint32_t d_SI_TX_DATA1_OFFSET; 61*5113495bSYour Name uint32_t d_SI_RX_DATA0_OFFSET; 62*5113495bSYour Name uint32_t d_SI_RX_DATA1_OFFSET; 63*5113495bSYour Name uint32_t d_SI_CS_OFFSET; 64*5113495bSYour Name uint32_t d_SI_CS_DONE_ERR_MASK; 65*5113495bSYour Name uint32_t d_SI_CS_DONE_INT_MASK; 66*5113495bSYour Name uint32_t d_SI_CS_START_LSB; 67*5113495bSYour Name uint32_t d_SI_CS_START_MASK; 68*5113495bSYour Name uint32_t d_SI_CS_RX_CNT_LSB; 69*5113495bSYour Name uint32_t d_SI_CS_RX_CNT_MASK; 70*5113495bSYour Name uint32_t d_SI_CS_TX_CNT_LSB; 71*5113495bSYour Name uint32_t d_SI_CS_TX_CNT_MASK; 72*5113495bSYour Name uint32_t d_BOARD_DATA_SZ; 73*5113495bSYour Name uint32_t d_BOARD_EXT_DATA_SZ; 74*5113495bSYour Name uint32_t d_MBOX_BASE_ADDRESS; 75*5113495bSYour Name uint32_t d_LOCAL_SCRATCH_OFFSET; 76*5113495bSYour Name uint32_t d_CPU_CLOCK_OFFSET; 77*5113495bSYour Name uint32_t d_LPO_CAL_OFFSET; 78*5113495bSYour Name uint32_t d_GPIO_PIN10_OFFSET; 79*5113495bSYour Name uint32_t d_GPIO_PIN11_OFFSET; 80*5113495bSYour Name uint32_t d_GPIO_PIN12_OFFSET; 81*5113495bSYour Name uint32_t d_GPIO_PIN13_OFFSET; 82*5113495bSYour Name uint32_t d_CLOCK_GPIO_OFFSET; 83*5113495bSYour Name uint32_t d_CPU_CLOCK_STANDARD_LSB; 84*5113495bSYour Name uint32_t d_CPU_CLOCK_STANDARD_MASK; 85*5113495bSYour Name uint32_t d_LPO_CAL_ENABLE_LSB; 86*5113495bSYour Name uint32_t d_LPO_CAL_ENABLE_MASK; 87*5113495bSYour Name uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; 88*5113495bSYour Name uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; 89*5113495bSYour Name uint32_t d_ANALOG_INTF_BASE_ADDRESS; 90*5113495bSYour Name uint32_t d_WLAN_MAC_BASE_ADDRESS; 91*5113495bSYour Name uint32_t d_FW_INDICATOR_ADDRESS; 92*5113495bSYour Name uint32_t d_DRAM_BASE_ADDRESS; 93*5113495bSYour Name uint32_t d_SOC_CORE_BASE_ADDRESS; 94*5113495bSYour Name uint32_t d_CORE_CTRL_ADDRESS; 95*5113495bSYour Name uint32_t d_MSI_NUM_REQUEST; 96*5113495bSYour Name uint32_t d_MSI_ASSIGN_FW; 97*5113495bSYour Name uint32_t d_CORE_CTRL_CPU_INTR_MASK; 98*5113495bSYour Name uint32_t d_SR_WR_INDEX_ADDRESS; 99*5113495bSYour Name uint32_t d_DST_WATERMARK_ADDRESS; 100*5113495bSYour Name 101*5113495bSYour Name /* htt_rx.c */ 102*5113495bSYour Name uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; 103*5113495bSYour Name uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; 104*5113495bSYour Name uint32_t d_RX_MPDU_START_0_RETRY_LSB; 105*5113495bSYour Name uint32_t d_RX_MPDU_START_0_RETRY_MASK; 106*5113495bSYour Name uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; 107*5113495bSYour Name uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; 108*5113495bSYour Name uint32_t d_RX_MPDU_START_2_PN_47_32_LSB; 109*5113495bSYour Name uint32_t d_RX_MPDU_START_2_PN_47_32_MASK; 110*5113495bSYour Name uint32_t d_RX_MPDU_START_2_TID_LSB; 111*5113495bSYour Name uint32_t d_RX_MPDU_START_2_TID_MASK; 112*5113495bSYour Name uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; 113*5113495bSYour Name uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; 114*5113495bSYour Name uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; 115*5113495bSYour Name uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; 116*5113495bSYour Name uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; 117*5113495bSYour Name uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; 118*5113495bSYour Name uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; 119*5113495bSYour Name uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; 120*5113495bSYour Name uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK; 121*5113495bSYour Name uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB; 122*5113495bSYour Name uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; 123*5113495bSYour Name uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; 124*5113495bSYour Name uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; 125*5113495bSYour Name uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; 126*5113495bSYour Name uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; 127*5113495bSYour Name uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; 128*5113495bSYour Name uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; 129*5113495bSYour Name uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; 130*5113495bSYour Name uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; 131*5113495bSYour Name uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; 132*5113495bSYour Name uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK; 133*5113495bSYour Name uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; 134*5113495bSYour Name uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; 135*5113495bSYour Name /* end */ 136*5113495bSYour Name 137*5113495bSYour Name /* PLL start */ 138*5113495bSYour Name uint32_t d_EFUSE_OFFSET; 139*5113495bSYour Name uint32_t d_EFUSE_XTAL_SEL_MSB; 140*5113495bSYour Name uint32_t d_EFUSE_XTAL_SEL_LSB; 141*5113495bSYour Name uint32_t d_EFUSE_XTAL_SEL_MASK; 142*5113495bSYour Name uint32_t d_BB_PLL_CONFIG_OFFSET; 143*5113495bSYour Name uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB; 144*5113495bSYour Name uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB; 145*5113495bSYour Name uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK; 146*5113495bSYour Name uint32_t d_BB_PLL_CONFIG_FRAC_MSB; 147*5113495bSYour Name uint32_t d_BB_PLL_CONFIG_FRAC_LSB; 148*5113495bSYour Name uint32_t d_BB_PLL_CONFIG_FRAC_MASK; 149*5113495bSYour Name uint32_t d_WLAN_PLL_SETTLE_TIME_MSB; 150*5113495bSYour Name uint32_t d_WLAN_PLL_SETTLE_TIME_LSB; 151*5113495bSYour Name uint32_t d_WLAN_PLL_SETTLE_TIME_MASK; 152*5113495bSYour Name uint32_t d_WLAN_PLL_SETTLE_OFFSET; 153*5113495bSYour Name uint32_t d_WLAN_PLL_SETTLE_SW_MASK; 154*5113495bSYour Name uint32_t d_WLAN_PLL_SETTLE_RSTMASK; 155*5113495bSYour Name uint32_t d_WLAN_PLL_SETTLE_RESET; 156*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; 157*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; 158*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; 159*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; 160*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; 161*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; 162*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; 163*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; 164*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; 165*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; 166*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; 167*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; 168*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; 169*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; 170*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; 171*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_DIV_MSB; 172*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_DIV_LSB; 173*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_DIV_MASK; 174*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_DIV_RESET; 175*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_OFFSET; 176*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_SW_MASK; 177*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_RSTMASK; 178*5113495bSYour Name uint32_t d_WLAN_PLL_CONTROL_RESET; 179*5113495bSYour Name uint32_t d_SOC_CORE_CLK_CTRL_OFFSET; 180*5113495bSYour Name uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; 181*5113495bSYour Name uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; 182*5113495bSYour Name uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; 183*5113495bSYour Name uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; 184*5113495bSYour Name uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; 185*5113495bSYour Name uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; 186*5113495bSYour Name uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; 187*5113495bSYour Name uint32_t d_RTC_SYNC_STATUS_OFFSET; 188*5113495bSYour Name uint32_t d_SOC_CPU_CLOCK_OFFSET; 189*5113495bSYour Name uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB; 190*5113495bSYour Name uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB; 191*5113495bSYour Name uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK; 192*5113495bSYour Name /* PLL end */ 193*5113495bSYour Name 194*5113495bSYour Name uint32_t d_SOC_POWER_REG_OFFSET; 195*5113495bSYour Name uint32_t d_SOC_RESET_CONTROL_ADDRESS; 196*5113495bSYour Name uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 197*5113495bSYour Name uint32_t d_CPU_INTR_ADDRESS; 198*5113495bSYour Name uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; 199*5113495bSYour Name uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 200*5113495bSYour Name uint32_t d_SOC_LF_TIMER_STATUS0_ADDRESS; 201*5113495bSYour Name 202*5113495bSYour Name /* chip id start */ 203*5113495bSYour Name uint32_t d_SOC_CHIP_ID_ADDRESS; 204*5113495bSYour Name uint32_t d_SOC_CHIP_ID_VERSION_MASK; 205*5113495bSYour Name uint32_t d_SOC_CHIP_ID_VERSION_LSB; 206*5113495bSYour Name uint32_t d_SOC_CHIP_ID_REVISION_MASK; 207*5113495bSYour Name uint32_t d_SOC_CHIP_ID_REVISION_LSB; 208*5113495bSYour Name /* chip id end */ 209*5113495bSYour Name 210*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS; 211*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS; 212*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS; 213*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS; 214*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS; 215*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS; 216*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS; 217*5113495bSYour Name uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS; 218*5113495bSYour Name uint32_t d_A_SOC_CORE_SPARE_0_REGISTER; 219*5113495bSYour Name uint32_t d_A_SOC_CORE_SPARE_1_REGISTER; 220*5113495bSYour Name 221*5113495bSYour Name uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; 222*5113495bSYour Name uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; 223*5113495bSYour Name uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; 224*5113495bSYour Name uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; 225*5113495bSYour Name uint32_t d_WLAN_DEBUG_CONTROL_OFFSET; 226*5113495bSYour Name uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; 227*5113495bSYour Name uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; 228*5113495bSYour Name uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; 229*5113495bSYour Name uint32_t d_WLAN_DEBUG_OUT_OFFSET; 230*5113495bSYour Name uint32_t d_WLAN_DEBUG_OUT_DATA_MSB; 231*5113495bSYour Name uint32_t d_WLAN_DEBUG_OUT_DATA_LSB; 232*5113495bSYour Name uint32_t d_WLAN_DEBUG_OUT_DATA_MASK; 233*5113495bSYour Name uint32_t d_AMBA_DEBUG_BUS_OFFSET; 234*5113495bSYour Name uint32_t d_AMBA_DEBUG_BUS_SEL_MSB; 235*5113495bSYour Name uint32_t d_AMBA_DEBUG_BUS_SEL_LSB; 236*5113495bSYour Name uint32_t d_AMBA_DEBUG_BUS_SEL_MASK; 237*5113495bSYour Name 238*5113495bSYour Name #ifdef QCA_WIFI_3_0_ADRASTEA 239*5113495bSYour Name uint32_t d_Q6_ENABLE_REGISTER_0; 240*5113495bSYour Name uint32_t d_Q6_ENABLE_REGISTER_1; 241*5113495bSYour Name uint32_t d_Q6_CAUSE_REGISTER_0; 242*5113495bSYour Name uint32_t d_Q6_CAUSE_REGISTER_1; 243*5113495bSYour Name uint32_t d_Q6_CLEAR_REGISTER_0; 244*5113495bSYour Name uint32_t d_Q6_CLEAR_REGISTER_1; 245*5113495bSYour Name #endif 246*5113495bSYour Name }; 247*5113495bSYour Name 248*5113495bSYour Name #define A_SOC_CORE_SPARE_0_REGISTER \ 249*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER) 250*5113495bSYour Name #define A_SOC_CORE_SCRATCH_0_ADDRESS \ 251*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS) 252*5113495bSYour Name #define A_SOC_CORE_SCRATCH_1_ADDRESS \ 253*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS) 254*5113495bSYour Name #define A_SOC_CORE_SCRATCH_2_ADDRESS \ 255*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS) 256*5113495bSYour Name #define A_SOC_CORE_SCRATCH_3_ADDRESS \ 257*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS) 258*5113495bSYour Name #define A_SOC_CORE_SCRATCH_4_ADDRESS \ 259*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS) 260*5113495bSYour Name #define A_SOC_CORE_SCRATCH_5_ADDRESS \ 261*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS) 262*5113495bSYour Name #define A_SOC_CORE_SCRATCH_6_ADDRESS \ 263*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS) 264*5113495bSYour Name #define A_SOC_CORE_SCRATCH_7_ADDRESS \ 265*5113495bSYour Name (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS) 266*5113495bSYour Name #define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 267*5113495bSYour Name #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 268*5113495bSYour Name #define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 269*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_OFFSET \ 270*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 271*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 272*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 273*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 274*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 275*5113495bSYour Name #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 276*5113495bSYour Name #define CLOCK_CONTROL_SI0_CLK_MASK \ 277*5113495bSYour Name (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 278*5113495bSYour Name #define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET) 279*5113495bSYour Name #define RESET_CONTROL_MBOX_RST_MASK \ 280*5113495bSYour Name (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 281*5113495bSYour Name #define RESET_CONTROL_SI0_RST_MASK \ 282*5113495bSYour Name (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 283*5113495bSYour Name #define WLAN_RESET_CONTROL_OFFSET \ 284*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 285*5113495bSYour Name #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 286*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 287*5113495bSYour Name #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 288*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 289*5113495bSYour Name #define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS) 290*5113495bSYour Name #define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET) 291*5113495bSYour Name #define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET) 292*5113495bSYour Name #define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 293*5113495bSYour Name #define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 294*5113495bSYour Name #define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0) 295*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 296*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 297*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 298*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 299*5113495bSYour Name #define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB) 300*5113495bSYour Name #define SI_CONFIG_I2C_MASK \ 301*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_I2C_MASK) 302*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_LSB \ 303*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 304*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_MASK \ 305*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 306*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_LSB \ 307*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 308*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_MASK \ 309*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 310*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_LSB \ 311*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 312*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_MASK \ 313*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 314*5113495bSYour Name #define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 315*5113495bSYour Name #define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 316*5113495bSYour Name #define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS) 317*5113495bSYour Name #define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET) 318*5113495bSYour Name #define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET) 319*5113495bSYour Name #define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET) 320*5113495bSYour Name #define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET) 321*5113495bSYour Name #define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET) 322*5113495bSYour Name #define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET) 323*5113495bSYour Name #define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 324*5113495bSYour Name #define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK) 325*5113495bSYour Name #define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB) 326*5113495bSYour Name #define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK) 327*5113495bSYour Name #define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB) 328*5113495bSYour Name #define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK) 329*5113495bSYour Name #define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB) 330*5113495bSYour Name #define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK) 331*5113495bSYour Name #define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ) 332*5113495bSYour Name #define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ) 333*5113495bSYour Name #define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS) 334*5113495bSYour Name #define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 335*5113495bSYour Name #define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET) 336*5113495bSYour Name #define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET) 337*5113495bSYour Name #define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET) 338*5113495bSYour Name #define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET) 339*5113495bSYour Name #define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET) 340*5113495bSYour Name #define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET) 341*5113495bSYour Name #define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET) 342*5113495bSYour Name #define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 343*5113495bSYour Name #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 344*5113495bSYour Name #define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 345*5113495bSYour Name #define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 346*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 347*5113495bSYour Name (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 348*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 349*5113495bSYour Name (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 350*5113495bSYour Name #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 351*5113495bSYour Name #define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 352*5113495bSYour Name #define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS) 353*5113495bSYour Name #define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS) 354*5113495bSYour Name #define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 355*5113495bSYour Name #define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS) 356*5113495bSYour Name #define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 357*5113495bSYour Name #define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 358*5113495bSYour Name #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ 359*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 360*5113495bSYour Name #define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS) 361*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 362*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 363*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 364*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 365*5113495bSYour Name #define SOC_LF_TIMER_STATUS0_ADDRESS \ 366*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS) 367*5113495bSYour Name 368*5113495bSYour Name 369*5113495bSYour Name #define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 370*5113495bSYour Name #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 371*5113495bSYour Name #define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 372*5113495bSYour Name #define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 373*5113495bSYour Name #define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 374*5113495bSYour Name #define CHIP_ID_REVISION_GET(x) \ 375*5113495bSYour Name (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 376*5113495bSYour Name #define CHIP_ID_VERSION_GET(x) \ 377*5113495bSYour Name (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 378*5113495bSYour Name 379*5113495bSYour Name /* misc */ 380*5113495bSYour Name #define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 381*5113495bSYour Name #define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS) 382*5113495bSYour Name #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET) 383*5113495bSYour Name /* end */ 384*5113495bSYour Name 385*5113495bSYour Name /* copy_engine.c */ 386*5113495bSYour Name /* end */ 387*5113495bSYour Name /* PLL start */ 388*5113495bSYour Name #define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET) 389*5113495bSYour Name #define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 390*5113495bSYour Name #define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 391*5113495bSYour Name #define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 392*5113495bSYour Name #define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 393*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 394*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 395*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 396*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 397*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 398*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 399*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 400*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 401*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 402*5113495bSYour Name #define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 403*5113495bSYour Name #define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 404*5113495bSYour Name #define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 405*5113495bSYour Name #define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 406*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_MSB \ 407*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 408*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_LSB \ 409*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 410*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_MASK \ 411*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 412*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_MSB \ 413*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 414*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_LSB \ 415*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 416*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_MASK \ 417*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 418*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_RESET \ 419*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 420*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 421*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 422*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 423*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 424*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 425*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 426*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 427*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 428*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_MSB \ 429*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 430*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_LSB \ 431*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 432*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_MASK \ 433*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 434*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_RESET \ 435*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 436*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 437*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 438*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 439*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_RESET \ 440*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 441*5113495bSYour Name #define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 442*5113495bSYour Name #define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 443*5113495bSYour Name #define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 444*5113495bSYour Name #define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 445*5113495bSYour Name #define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 446*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 447*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 448*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_MASK \ 449*5113495bSYour Name (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 450*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 451*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 452*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 453*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 454*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 455*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 456*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 457*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 458*5113495bSYour Name #define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 459*5113495bSYour Name #define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 460*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_MSB \ 461*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 462*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_LSB \ 463*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 464*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_MASK \ 465*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 466*5113495bSYour Name /* PLL end */ 467*5113495bSYour Name 468*5113495bSYour Name /* SET macros */ 469*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 470*5113495bSYour Name (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 471*5113495bSYour Name WLAN_SYSTEM_SLEEP_DISABLE_MASK) 472*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 473*5113495bSYour Name (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) 474*5113495bSYour Name #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 475*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_SET(x) \ 476*5113495bSYour Name (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) 477*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 478*5113495bSYour Name (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) 479*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 480*5113495bSYour Name (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) 481*5113495bSYour Name #define SI_CONFIG_DIVIDER_SET(x) \ 482*5113495bSYour Name (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 483*5113495bSYour Name #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 484*5113495bSYour Name #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 485*5113495bSYour Name #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 486*5113495bSYour Name #define LPO_CAL_ENABLE_SET(x) \ 487*5113495bSYour Name (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 488*5113495bSYour Name #define CPU_CLOCK_STANDARD_SET(x) \ 489*5113495bSYour Name (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 490*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 491*5113495bSYour Name (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 492*5113495bSYour Name /* copy_engine.c */ 493*5113495bSYour Name /* end */ 494*5113495bSYour Name /* PLL start */ 495*5113495bSYour Name #define EFUSE_XTAL_SEL_GET(x) \ 496*5113495bSYour Name (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 497*5113495bSYour Name #define EFUSE_XTAL_SEL_SET(x) \ 498*5113495bSYour Name (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 499*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 500*5113495bSYour Name (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 501*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 502*5113495bSYour Name (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 503*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_GET(x) \ 504*5113495bSYour Name (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 505*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_SET(x) \ 506*5113495bSYour Name (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 507*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_GET(x) \ 508*5113495bSYour Name (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 509*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_SET(x) \ 510*5113495bSYour Name (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 511*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 512*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) 513*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 514*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) 515*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 516*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) 517*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 518*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) 519*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 520*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB) 521*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 522*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK) 523*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 524*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) 525*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 526*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) 527*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_GET(x) \ 528*5113495bSYour Name (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) 529*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_SET(x) \ 530*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) 531*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 532*5113495bSYour Name (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB) 533*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 534*5113495bSYour Name (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK) 535*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 536*5113495bSYour Name (((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 537*5113495bSYour Name RTC_SYNC_STATUS_PLL_CHANGING_LSB) 538*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 539*5113495bSYour Name (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 540*5113495bSYour Name RTC_SYNC_STATUS_PLL_CHANGING_MASK) 541*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 542*5113495bSYour Name (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB) 543*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 544*5113495bSYour Name (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) 545*5113495bSYour Name /* PLL end */ 546*5113495bSYour Name 547*5113495bSYour Name #ifdef QCA_WIFI_3_0_ADRASTEA 548*5113495bSYour Name #define Q6_ENABLE_REGISTER_0 \ 549*5113495bSYour Name (scn->targetdef->d_Q6_ENABLE_REGISTER_0) 550*5113495bSYour Name #define Q6_ENABLE_REGISTER_1 \ 551*5113495bSYour Name (scn->targetdef->d_Q6_ENABLE_REGISTER_1) 552*5113495bSYour Name #define Q6_CAUSE_REGISTER_0 \ 553*5113495bSYour Name (scn->targetdef->d_Q6_CAUSE_REGISTER_0) 554*5113495bSYour Name #define Q6_CAUSE_REGISTER_1 \ 555*5113495bSYour Name (scn->targetdef->d_Q6_CAUSE_REGISTER_1) 556*5113495bSYour Name #define Q6_CLEAR_REGISTER_0 \ 557*5113495bSYour Name (scn->targetdef->d_Q6_CLEAR_REGISTER_0) 558*5113495bSYour Name #define Q6_CLEAR_REGISTER_1 \ 559*5113495bSYour Name (scn->targetdef->d_Q6_CLEAR_REGISTER_1) 560*5113495bSYour Name #endif 561*5113495bSYour Name 562*5113495bSYour Name struct hostdef_s { 563*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; 564*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; 565*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_CPU_LSB; 566*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_CPU_MASK; 567*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; 568*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; 569*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; 570*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; 571*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; 572*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; 573*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; 574*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; 575*5113495bSYour Name uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; 576*5113495bSYour Name uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; 577*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_ADDRESS; 578*5113495bSYour Name uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; 579*5113495bSYour Name uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; 580*5113495bSYour Name uint32_t d_HOST_INT_STATUS_ADDRESS; 581*5113495bSYour Name uint32_t d_CPU_INT_STATUS_ADDRESS; 582*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_ADDRESS; 583*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; 584*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; 585*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; 586*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; 587*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; 588*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; 589*5113495bSYour Name uint32_t d_COUNT_DEC_ADDRESS; 590*5113495bSYour Name uint32_t d_HOST_INT_STATUS_CPU_MASK; 591*5113495bSYour Name uint32_t d_HOST_INT_STATUS_CPU_LSB; 592*5113495bSYour Name uint32_t d_HOST_INT_STATUS_ERROR_MASK; 593*5113495bSYour Name uint32_t d_HOST_INT_STATUS_ERROR_LSB; 594*5113495bSYour Name uint32_t d_HOST_INT_STATUS_COUNTER_MASK; 595*5113495bSYour Name uint32_t d_HOST_INT_STATUS_COUNTER_LSB; 596*5113495bSYour Name uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; 597*5113495bSYour Name uint32_t d_WINDOW_DATA_ADDRESS; 598*5113495bSYour Name uint32_t d_WINDOW_READ_ADDR_ADDRESS; 599*5113495bSYour Name uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; 600*5113495bSYour Name uint32_t d_SOC_GLOBAL_RESET_ADDRESS; 601*5113495bSYour Name uint32_t d_RTC_STATE_ADDRESS; 602*5113495bSYour Name uint32_t d_RTC_STATE_COLD_RESET_MASK; 603*5113495bSYour Name uint32_t d_RTC_STATE_V_MASK; 604*5113495bSYour Name uint32_t d_RTC_STATE_V_LSB; 605*5113495bSYour Name uint32_t d_FW_IND_EVENT_PENDING; 606*5113495bSYour Name uint32_t d_FW_IND_INITIALIZED; 607*5113495bSYour Name uint32_t d_FW_IND_HELPER; 608*5113495bSYour Name uint32_t d_RTC_STATE_V_ON; 609*5113495bSYour Name #if defined(SDIO_3_0) 610*5113495bSYour Name uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; 611*5113495bSYour Name uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; 612*5113495bSYour Name #endif 613*5113495bSYour Name uint32_t d_MSI_MAGIC_ADR_ADDRESS; 614*5113495bSYour Name uint32_t d_MSI_MAGIC_ADDRESS; 615*5113495bSYour Name uint32_t d_ENABLE_MSI; 616*5113495bSYour Name uint32_t d_MUX_ID_MASK; 617*5113495bSYour Name uint32_t d_TRANSACTION_ID_MASK; 618*5113495bSYour Name uint32_t d_DESC_DATA_FLAG_MASK; 619*5113495bSYour Name }; 620*5113495bSYour Name #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK) 621*5113495bSYour Name #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK) 622*5113495bSYour Name #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK) 623*5113495bSYour Name #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI) 624*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_LSB \ 625*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 626*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_MASK \ 627*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 628*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 629*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 630*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_LSB \ 631*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 632*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_MASK \ 633*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 634*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 635*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 636*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 637*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 638*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 639*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 640*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 641*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 642*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \ 643*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 644*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 645*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 646*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 647*5113495bSYour Name (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 648*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 649*5113495bSYour Name (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 650*5113495bSYour Name #define INT_STATUS_ENABLE_ADDRESS \ 651*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 652*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 653*5113495bSYour Name (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 654*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 655*5113495bSYour Name (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 656*5113495bSYour Name #define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 657*5113495bSYour Name #define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 658*5113495bSYour Name #define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 659*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_MASK \ 660*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 661*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_LSB \ 662*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 663*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 664*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 665*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 666*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 667*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 668*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 669*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 670*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 671*5113495bSYour Name #define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS) 672*5113495bSYour Name #define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 673*5113495bSYour Name #define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 674*5113495bSYour Name #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 675*5113495bSYour Name #define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 676*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_MASK \ 677*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 678*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_LSB \ 679*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 680*5113495bSYour Name #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 681*5113495bSYour Name #define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS) 682*5113495bSYour Name #define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 683*5113495bSYour Name #define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 684*5113495bSYour Name #define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 685*5113495bSYour Name #define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS) 686*5113495bSYour Name #define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 687*5113495bSYour Name #define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK) 688*5113495bSYour Name #define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB) 689*5113495bSYour Name #define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING) 690*5113495bSYour Name #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED) 691*5113495bSYour Name #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER) 692*5113495bSYour Name #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON) 693*5113495bSYour Name #if defined(SDIO_3_0) 694*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_MASK \ 695*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 696*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_LSB \ 697*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 698*5113495bSYour Name #endif 699*5113495bSYour Name 700*5113495bSYour Name #if !defined(MSI_MAGIC_ADR_ADDRESS) 701*5113495bSYour Name #define MSI_MAGIC_ADR_ADDRESS 0 702*5113495bSYour Name #define MSI_MAGIC_ADDRESS 0 703*5113495bSYour Name #endif 704*5113495bSYour Name 705*5113495bSYour Name /* SET/GET macros */ 706*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_SET(x) \ 707*5113495bSYour Name (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) 708*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_SET(x) \ 709*5113495bSYour Name (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) 710*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 711*5113495bSYour Name (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 712*5113495bSYour Name INT_STATUS_ENABLE_COUNTER_MASK) 713*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 714*5113495bSYour Name (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 715*5113495bSYour Name INT_STATUS_ENABLE_MBOX_DATA_MASK) 716*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 717*5113495bSYour Name (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 718*5113495bSYour Name CPU_INT_STATUS_ENABLE_BIT_MASK) 719*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 720*5113495bSYour Name (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 721*5113495bSYour Name ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 722*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \ 723*5113495bSYour Name (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 724*5113495bSYour Name ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 725*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 726*5113495bSYour Name (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 727*5113495bSYour Name COUNTER_INT_STATUS_ENABLE_BIT_MASK) 728*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 729*5113495bSYour Name (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 730*5113495bSYour Name ERROR_INT_STATUS_WAKEUP_LSB) 731*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 732*5113495bSYour Name (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 733*5113495bSYour Name ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 734*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 735*5113495bSYour Name (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 736*5113495bSYour Name ERROR_INT_STATUS_TX_OVERFLOW_LSB) 737*5113495bSYour Name #define HOST_INT_STATUS_CPU_GET(x) \ 738*5113495bSYour Name (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) 739*5113495bSYour Name #define HOST_INT_STATUS_ERROR_GET(x) \ 740*5113495bSYour Name (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) 741*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_GET(x) \ 742*5113495bSYour Name (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) 743*5113495bSYour Name #define RTC_STATE_V_GET(x) \ 744*5113495bSYour Name (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 745*5113495bSYour Name #if defined(SDIO_3_0) 746*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 747*5113495bSYour Name (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 748*5113495bSYour Name HOST_INT_STATUS_MBOX_DATA_LSB) 749*5113495bSYour Name #endif 750*5113495bSYour Name 751*5113495bSYour Name #define INVALID_REG_LOC_DUMMY_DATA 0xAA 752*5113495bSYour Name 753*5113495bSYour Name #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 754*5113495bSYour Name #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 755*5113495bSYour Name #define AR6320_CPU_SPEED_ADDR 0x403fa4 756*5113495bSYour Name #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 757*5113495bSYour Name #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 758*5113495bSYour Name #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 759*5113495bSYour Name #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 760*5113495bSYour Name #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 761*5113495bSYour Name #define AR6320V3_CPU_SPEED_ADDR 0x404024 762*5113495bSYour Name 763*5113495bSYour Name enum a_refclk_speed_t { 764*5113495bSYour Name SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ 765*5113495bSYour Name SOC_REFCLK_48_MHZ = 0, 766*5113495bSYour Name SOC_REFCLK_19_2_MHZ = 1, 767*5113495bSYour Name SOC_REFCLK_24_MHZ = 2, 768*5113495bSYour Name SOC_REFCLK_26_MHZ = 3, 769*5113495bSYour Name SOC_REFCLK_37_4_MHZ = 4, 770*5113495bSYour Name SOC_REFCLK_38_4_MHZ = 5, 771*5113495bSYour Name SOC_REFCLK_40_MHZ = 6, 772*5113495bSYour Name SOC_REFCLK_52_MHZ = 7, 773*5113495bSYour Name }; 774*5113495bSYour Name 775*5113495bSYour Name #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 776*5113495bSYour Name #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 777*5113495bSYour Name #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 778*5113495bSYour Name #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 779*5113495bSYour Name #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 780*5113495bSYour Name #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 781*5113495bSYour Name #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 782*5113495bSYour Name #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 783*5113495bSYour Name #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 784*5113495bSYour Name 785*5113495bSYour Name #define TARGET_CPU_FREQ 176000000 786*5113495bSYour Name 787*5113495bSYour Name struct wlan_pll_s { 788*5113495bSYour Name uint32_t refdiv; 789*5113495bSYour Name uint32_t div; 790*5113495bSYour Name uint32_t rnfrac; 791*5113495bSYour Name uint32_t outdiv; 792*5113495bSYour Name }; 793*5113495bSYour Name 794*5113495bSYour Name struct cmnos_clock_s { 795*5113495bSYour Name enum a_refclk_speed_t refclk_speed; 796*5113495bSYour Name uint32_t refclk_hz; 797*5113495bSYour Name uint32_t pll_settling_time; /* 50us */ 798*5113495bSYour Name struct wlan_pll_s wlan_pll; 799*5113495bSYour Name }; 800*5113495bSYour Name 801*5113495bSYour Name struct tgt_reg_section { 802*5113495bSYour Name uint32_t start_addr; 803*5113495bSYour Name uint32_t end_addr; 804*5113495bSYour Name }; 805*5113495bSYour Name 806*5113495bSYour Name 807*5113495bSYour Name struct tgt_reg_table { 808*5113495bSYour Name const struct tgt_reg_section *section; 809*5113495bSYour Name uint32_t section_size; 810*5113495bSYour Name }; 811*5113495bSYour Name #endif /* _REGTABLE_SDIO_H_ */ 812