1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2013-2014, 2016-2019 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * 5*5113495bSYour Name * 6*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 7*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 8*5113495bSYour Name * above copyright notice and this permission notice appear in all 9*5113495bSYour Name * copies. 10*5113495bSYour Name * 11*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 12*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 13*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 14*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 15*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 16*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 17*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 18*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 19*5113495bSYour Name */ 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name #ifndef _MAILBOX_H_ 23*5113495bSYour Name #define _MAILBOX_H__ 24*5113495bSYour Name 25*5113495bSYour Name #include "a_debug.h" 26*5113495bSYour Name #include "hif_sdio_dev.h" 27*5113495bSYour Name #include "htc_packet.h" 28*5113495bSYour Name #include "htc_api.h" 29*5113495bSYour Name #include "hif_internal.h" 30*5113495bSYour Name 31*5113495bSYour Name #define INVALID_MAILBOX_NUMBER 0xFF 32*5113495bSYour Name 33*5113495bSYour Name #define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ 34*5113495bSYour Name INT_STATUS_ENABLE_CPU_MASK | \ 35*5113495bSYour Name INT_STATUS_ENABLE_COUNTER_MASK) 36*5113495bSYour Name 37*5113495bSYour Name /* HTC operational parameters */ 38*5113495bSYour Name #define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ 39*5113495bSYour Name #define HTC_TARGET_DEBUG_INTR_MASK 0x01 40*5113495bSYour Name #define HTC_TARGET_CREDIT_INTR_MASK 0xF0 41*5113495bSYour Name 42*5113495bSYour Name #define MAILBOX_COUNT 4 43*5113495bSYour Name #define MAILBOX_FOR_BLOCK_SIZE 1 44*5113495bSYour Name #define MAILBOX_USED_COUNT 2 45*5113495bSYour Name #if defined(SDIO_3_0) 46*5113495bSYour Name #define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 2 47*5113495bSYour Name #else 48*5113495bSYour Name #define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 1 49*5113495bSYour Name #endif 50*5113495bSYour Name #define AR6K_TARGET_DEBUG_INTR_MASK 0x01 51*5113495bSYour Name 52*5113495bSYour Name /* Mailbox address in SDIO address space */ 53*5113495bSYour Name #if defined(SDIO_3_0) 54*5113495bSYour Name #define HIF_MBOX_BASE_ADDR 0x1000 55*5113495bSYour Name #define HIF_MBOX_DUMMY_WIDTH 0x800 56*5113495bSYour Name #else 57*5113495bSYour Name #define HIF_MBOX_BASE_ADDR 0x800 58*5113495bSYour Name #define HIF_MBOX_DUMMY_WIDTH 0 59*5113495bSYour Name #endif 60*5113495bSYour Name 61*5113495bSYour Name #define HIF_MBOX_WIDTH 0x800 62*5113495bSYour Name 63*5113495bSYour Name #define HIF_MBOX_START_ADDR(mbox) \ 64*5113495bSYour Name (HIF_MBOX_BASE_ADDR + mbox * (HIF_MBOX_WIDTH + HIF_MBOX_DUMMY_WIDTH)) 65*5113495bSYour Name 66*5113495bSYour Name #define HIF_MBOX_END_ADDR(mbox) \ 67*5113495bSYour Name (HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1) 68*5113495bSYour Name 69*5113495bSYour Name /* extended MBOX address for larger MBOX writes to MBOX 0*/ 70*5113495bSYour Name #if defined(SDIO_3_0) 71*5113495bSYour Name #define HIF_MBOX0_EXTENDED_BASE_ADDR 0x5000 72*5113495bSYour Name #else 73*5113495bSYour Name #define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800 74*5113495bSYour Name #endif 75*5113495bSYour Name #define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6 * 1024) 76*5113495bSYour Name #define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18 * 1024) 77*5113495bSYour Name 78*5113495bSYour Name /* version 1 of the chip has only a 12K extended mbox range */ 79*5113495bSYour Name #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000 80*5113495bSYour Name #define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12 * 1024) 81*5113495bSYour Name 82*5113495bSYour Name #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6004 0x2800 83*5113495bSYour Name #define HIF_MBOX0_EXTENDED_WIDTH_AR6004 (18 * 1024) 84*5113495bSYour Name 85*5113495bSYour Name #if defined(SDIO_3_0) 86*5113495bSYour Name #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x5000 87*5113495bSYour Name #define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (36 * 1024) 88*5113495bSYour Name #define HIF_MBOX0_EXTENDED_WIDTH_AR6320_ROME_2_0 (56 * 1024) 89*5113495bSYour Name #define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (36 * 1024) 90*5113495bSYour Name #define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 (2 * 1024) 91*5113495bSYour Name #else 92*5113495bSYour Name #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x2800 93*5113495bSYour Name #define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (24 * 1024) 94*5113495bSYour Name #define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (24 * 1024) 95*5113495bSYour Name #define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 0 96*5113495bSYour Name #endif 97*5113495bSYour Name 98*5113495bSYour Name /* GMBOX addresses */ 99*5113495bSYour Name #define HIF_GMBOX_BASE_ADDR 0x7000 100*5113495bSYour Name #define HIF_GMBOX_WIDTH 0x4000 101*5113495bSYour Name 102*5113495bSYour Name /* for SDIO we recommend a 128-byte block size */ 103*5113495bSYour Name #if defined(WITH_BACKPORTS) 104*5113495bSYour Name #define HIF_DEFAULT_IO_BLOCK_SIZE 128 105*5113495bSYour Name #else 106*5113495bSYour Name #define HIF_DEFAULT_IO_BLOCK_SIZE 256 107*5113495bSYour Name #endif 108*5113495bSYour Name 109*5113495bSYour Name #define FIFO_TIMEOUT_AND_CHIP_CONTROL 0x00000868 110*5113495bSYour Name #define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF 111*5113495bSYour Name #define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000 112*5113495bSYour Name /* In SDIO 2.0, asynchronous interrupt is not in SPEC 113*5113495bSYour Name * requirement, but AR6003 support it, so the register 114*5113495bSYour Name * is placed in vendor specific field 0xF0(bit0) 115*5113495bSYour Name * In SDIO 3.0, the register is defined in SPEC, and its 116*5113495bSYour Name * address is 0x16(bit1) 117*5113495bSYour Name */ 118*5113495bSYour Name /* interrupt mode register of AR6003 */ 119*5113495bSYour Name #define CCCR_SDIO_IRQ_MODE_REG_AR6003 0xF0 120*5113495bSYour Name /* mode to enable special 4-bit interrupt assertion without clock */ 121*5113495bSYour Name #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6003 (1 << 0) 122*5113495bSYour Name /* interrupt mode register of AR6320 */ 123*5113495bSYour Name #define CCCR_SDIO_IRQ_MODE_REG_AR6320 0x16 124*5113495bSYour Name /* mode to enable special 4-bit interrupt assertion without clock */ 125*5113495bSYour Name #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6320 (1 << 1) 126*5113495bSYour Name 127*5113495bSYour Name #define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS 0xF0 128*5113495bSYour Name #define CCCR_SDIO_ASYNC_INT_DELAY_LSB 0x06 129*5113495bSYour Name #define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0 130*5113495bSYour Name 131*5113495bSYour Name /* Vendor Specific Driver Strength Settings */ 132*5113495bSYour Name #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xf2 133*5113495bSYour Name #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_MASK 0x0e 134*5113495bSYour Name #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02 135*5113495bSYour Name #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04 136*5113495bSYour Name #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08 137*5113495bSYour Name 138*5113495bSYour Name #define HIF_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE 139*5113495bSYour Name #define HIF_MBOX0_BLOCK_SIZE 1 140*5113495bSYour Name #define HIF_MBOX1_BLOCK_SIZE HIF_BLOCK_SIZE 141*5113495bSYour Name #define HIF_MBOX2_BLOCK_SIZE HIF_BLOCK_SIZE 142*5113495bSYour Name #define HIF_MBOX3_BLOCK_SIZE HIF_BLOCK_SIZE 143*5113495bSYour Name 144*5113495bSYour Name /* 145*5113495bSYour Name * data written into the dummy space will not put into the final mbox FIFO 146*5113495bSYour Name */ 147*5113495bSYour Name #define HIF_DUMMY_SPACE_MASK 0xFFFF0000 148*5113495bSYour Name 149*5113495bSYour Name PREPACK struct MBOX_IRQ_PROC_REGISTERS { 150*5113495bSYour Name uint8_t host_int_status; 151*5113495bSYour Name uint8_t cpu_int_status; 152*5113495bSYour Name uint8_t error_int_status; 153*5113495bSYour Name uint8_t counter_int_status; 154*5113495bSYour Name uint8_t mbox_frame; 155*5113495bSYour Name uint8_t rx_lookahead_valid; 156*5113495bSYour Name uint8_t host_int_status2; 157*5113495bSYour Name uint8_t gmbox_rx_avail; 158*5113495bSYour Name uint32_t rx_lookahead[MAILBOX_LOOKAHEAD_SIZE_IN_WORD * MAILBOX_COUNT]; 159*5113495bSYour Name uint32_t int_status_enable; 160*5113495bSYour Name } POSTPACK; 161*5113495bSYour Name 162*5113495bSYour Name PREPACK struct MBOX_IRQ_ENABLE_REGISTERS { 163*5113495bSYour Name uint8_t int_status_enable; 164*5113495bSYour Name uint8_t cpu_int_status_enable; 165*5113495bSYour Name uint8_t error_status_enable; 166*5113495bSYour Name uint8_t counter_int_status_enable; 167*5113495bSYour Name } POSTPACK; 168*5113495bSYour Name 169*5113495bSYour Name #define TOTAL_CREDIT_COUNTER_CNT 4 170*5113495bSYour Name 171*5113495bSYour Name PREPACK struct MBOX_COUNTER_REGISTERS { 172*5113495bSYour Name uint32_t counter[TOTAL_CREDIT_COUNTER_CNT]; 173*5113495bSYour Name } POSTPACK; 174*5113495bSYour Name 175*5113495bSYour Name struct devRegisters { 176*5113495bSYour Name struct MBOX_IRQ_PROC_REGISTERS IrqProcRegisters; 177*5113495bSYour Name struct MBOX_IRQ_ENABLE_REGISTERS IrqEnableRegisters; 178*5113495bSYour Name struct MBOX_COUNTER_REGISTERS MailBoxCounterRegisters; 179*5113495bSYour Name }; 180*5113495bSYour Name 181*5113495bSYour Name #define mboxProcRegs(hdev) hdev->devRegisters.IrqProcRegisters 182*5113495bSYour Name #define mboxEnaRegs(hdev) hdev->devRegisters.IrqEnableRegisters 183*5113495bSYour Name #define mboxCountRegs(hdev) hdev->devRegisters.MailBoxCounterRegisters 184*5113495bSYour Name 185*5113495bSYour Name #define DEV_REGISTERS_SIZE (sizeof(struct MBOX_IRQ_PROC_REGISTERS) + \ 186*5113495bSYour Name sizeof(struct MBOX_IRQ_ENABLE_REGISTERS) + \ 187*5113495bSYour Name sizeof(struct MBOX_COUNTER_REGISTERS)) 188*5113495bSYour Name 189*5113495bSYour Name void hif_dev_dump_registers(struct hif_sdio_device *pdev, 190*5113495bSYour Name struct MBOX_IRQ_PROC_REGISTERS *irq_proc, 191*5113495bSYour Name struct MBOX_IRQ_ENABLE_REGISTERS *irq_en, 192*5113495bSYour Name struct MBOX_COUNTER_REGISTERS *mbox_regs); 193*5113495bSYour Name #endif /* _MAILBOX_H_ */ 194