1 /* 2 * Copyright (c) 2013-2014, 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * 5 * 6 * Permission to use, copy, modify, and/or distribute this software for 7 * any purpose with or without fee is hereby granted, provided that the 8 * above copyright notice and this permission notice appear in all 9 * copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 12 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 13 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 14 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 15 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 16 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 17 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 18 * PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 22 #ifndef _MAILBOX_H_ 23 #define _MAILBOX_H__ 24 25 #include "a_debug.h" 26 #include "hif_sdio_dev.h" 27 #include "htc_packet.h" 28 #include "htc_api.h" 29 #include "hif_internal.h" 30 31 #define INVALID_MAILBOX_NUMBER 0xFF 32 33 #define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ 34 INT_STATUS_ENABLE_CPU_MASK | \ 35 INT_STATUS_ENABLE_COUNTER_MASK) 36 37 /* HTC operational parameters */ 38 #define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ 39 #define HTC_TARGET_DEBUG_INTR_MASK 0x01 40 #define HTC_TARGET_CREDIT_INTR_MASK 0xF0 41 42 #define MAILBOX_COUNT 4 43 #define MAILBOX_FOR_BLOCK_SIZE 1 44 #define MAILBOX_USED_COUNT 2 45 #if defined(SDIO_3_0) 46 #define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 2 47 #else 48 #define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 1 49 #endif 50 #define AR6K_TARGET_DEBUG_INTR_MASK 0x01 51 52 /* Mailbox address in SDIO address space */ 53 #if defined(SDIO_3_0) 54 #define HIF_MBOX_BASE_ADDR 0x1000 55 #define HIF_MBOX_DUMMY_WIDTH 0x800 56 #else 57 #define HIF_MBOX_BASE_ADDR 0x800 58 #define HIF_MBOX_DUMMY_WIDTH 0 59 #endif 60 61 #define HIF_MBOX_WIDTH 0x800 62 63 #define HIF_MBOX_START_ADDR(mbox) \ 64 (HIF_MBOX_BASE_ADDR + mbox * (HIF_MBOX_WIDTH + HIF_MBOX_DUMMY_WIDTH)) 65 66 #define HIF_MBOX_END_ADDR(mbox) \ 67 (HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1) 68 69 /* extended MBOX address for larger MBOX writes to MBOX 0*/ 70 #if defined(SDIO_3_0) 71 #define HIF_MBOX0_EXTENDED_BASE_ADDR 0x5000 72 #else 73 #define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800 74 #endif 75 #define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6 * 1024) 76 #define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18 * 1024) 77 78 /* version 1 of the chip has only a 12K extended mbox range */ 79 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000 80 #define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12 * 1024) 81 82 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6004 0x2800 83 #define HIF_MBOX0_EXTENDED_WIDTH_AR6004 (18 * 1024) 84 85 #if defined(SDIO_3_0) 86 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x5000 87 #define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (36 * 1024) 88 #define HIF_MBOX0_EXTENDED_WIDTH_AR6320_ROME_2_0 (56 * 1024) 89 #define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (36 * 1024) 90 #define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 (2 * 1024) 91 #else 92 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x2800 93 #define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (24 * 1024) 94 #define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (24 * 1024) 95 #define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 0 96 #endif 97 98 /* GMBOX addresses */ 99 #define HIF_GMBOX_BASE_ADDR 0x7000 100 #define HIF_GMBOX_WIDTH 0x4000 101 102 /* for SDIO we recommend a 128-byte block size */ 103 #if defined(WITH_BACKPORTS) 104 #define HIF_DEFAULT_IO_BLOCK_SIZE 128 105 #else 106 #define HIF_DEFAULT_IO_BLOCK_SIZE 256 107 #endif 108 109 #define FIFO_TIMEOUT_AND_CHIP_CONTROL 0x00000868 110 #define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF 111 #define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000 112 /* In SDIO 2.0, asynchronous interrupt is not in SPEC 113 * requirement, but AR6003 support it, so the register 114 * is placed in vendor specific field 0xF0(bit0) 115 * In SDIO 3.0, the register is defined in SPEC, and its 116 * address is 0x16(bit1) 117 */ 118 /* interrupt mode register of AR6003 */ 119 #define CCCR_SDIO_IRQ_MODE_REG_AR6003 0xF0 120 /* mode to enable special 4-bit interrupt assertion without clock */ 121 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6003 (1 << 0) 122 /* interrupt mode register of AR6320 */ 123 #define CCCR_SDIO_IRQ_MODE_REG_AR6320 0x16 124 /* mode to enable special 4-bit interrupt assertion without clock */ 125 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6320 (1 << 1) 126 127 #define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS 0xF0 128 #define CCCR_SDIO_ASYNC_INT_DELAY_LSB 0x06 129 #define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0 130 131 /* Vendor Specific Driver Strength Settings */ 132 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xf2 133 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_MASK 0x0e 134 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02 135 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04 136 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08 137 138 #define HIF_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE 139 #define HIF_MBOX0_BLOCK_SIZE 1 140 #define HIF_MBOX1_BLOCK_SIZE HIF_BLOCK_SIZE 141 #define HIF_MBOX2_BLOCK_SIZE HIF_BLOCK_SIZE 142 #define HIF_MBOX3_BLOCK_SIZE HIF_BLOCK_SIZE 143 144 /* 145 * data written into the dummy space will not put into the final mbox FIFO 146 */ 147 #define HIF_DUMMY_SPACE_MASK 0xFFFF0000 148 149 PREPACK struct MBOX_IRQ_PROC_REGISTERS { 150 uint8_t host_int_status; 151 uint8_t cpu_int_status; 152 uint8_t error_int_status; 153 uint8_t counter_int_status; 154 uint8_t mbox_frame; 155 uint8_t rx_lookahead_valid; 156 uint8_t host_int_status2; 157 uint8_t gmbox_rx_avail; 158 uint32_t rx_lookahead[MAILBOX_LOOKAHEAD_SIZE_IN_WORD * MAILBOX_COUNT]; 159 uint32_t int_status_enable; 160 } POSTPACK; 161 162 PREPACK struct MBOX_IRQ_ENABLE_REGISTERS { 163 uint8_t int_status_enable; 164 uint8_t cpu_int_status_enable; 165 uint8_t error_status_enable; 166 uint8_t counter_int_status_enable; 167 } POSTPACK; 168 169 #define TOTAL_CREDIT_COUNTER_CNT 4 170 171 PREPACK struct MBOX_COUNTER_REGISTERS { 172 uint32_t counter[TOTAL_CREDIT_COUNTER_CNT]; 173 } POSTPACK; 174 175 struct devRegisters { 176 struct MBOX_IRQ_PROC_REGISTERS IrqProcRegisters; 177 struct MBOX_IRQ_ENABLE_REGISTERS IrqEnableRegisters; 178 struct MBOX_COUNTER_REGISTERS MailBoxCounterRegisters; 179 }; 180 181 #define mboxProcRegs(hdev) hdev->devRegisters.IrqProcRegisters 182 #define mboxEnaRegs(hdev) hdev->devRegisters.IrqEnableRegisters 183 #define mboxCountRegs(hdev) hdev->devRegisters.MailBoxCounterRegisters 184 185 #define DEV_REGISTERS_SIZE (sizeof(struct MBOX_IRQ_PROC_REGISTERS) + \ 186 sizeof(struct MBOX_IRQ_ENABLE_REGISTERS) + \ 187 sizeof(struct MBOX_COUNTER_REGISTERS)) 188 189 void hif_dev_dump_registers(struct hif_sdio_device *pdev, 190 struct MBOX_IRQ_PROC_REGISTERS *irq_proc, 191 struct MBOX_IRQ_ENABLE_REGISTERS *irq_en, 192 struct MBOX_COUNTER_REGISTERS *mbox_regs); 193 #endif /* _MAILBOX_H_ */ 194