1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _REGTABLE_USB_H_ 20*5113495bSYour Name #define _REGTABLE_USB_H_ 21*5113495bSYour Name #include "if_usb.h" 22*5113495bSYour Name 23*5113495bSYour Name #define MISSING 0 24*5113495bSYour Name 25*5113495bSYour Name struct targetdef_s { 26*5113495bSYour Name u_int32_t d_RTC_SOC_BASE_ADDRESS; 27*5113495bSYour Name u_int32_t d_RTC_WMAC_BASE_ADDRESS; 28*5113495bSYour Name u_int32_t d_SYSTEM_SLEEP_OFFSET; 29*5113495bSYour Name u_int32_t d_WLAN_SYSTEM_SLEEP_OFFSET; 30*5113495bSYour Name u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; 31*5113495bSYour Name u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; 32*5113495bSYour Name u_int32_t d_CLOCK_CONTROL_OFFSET; 33*5113495bSYour Name u_int32_t d_CLOCK_CONTROL_SI0_CLK_MASK; 34*5113495bSYour Name u_int32_t d_RESET_CONTROL_OFFSET; 35*5113495bSYour Name u_int32_t d_RESET_CONTROL_MBOX_RST_MASK; 36*5113495bSYour Name u_int32_t d_RESET_CONTROL_SI0_RST_MASK; 37*5113495bSYour Name u_int32_t d_WLAN_RESET_CONTROL_OFFSET; 38*5113495bSYour Name u_int32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; 39*5113495bSYour Name u_int32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; 40*5113495bSYour Name u_int32_t d_GPIO_BASE_ADDRESS; 41*5113495bSYour Name u_int32_t d_GPIO_PIN0_OFFSET; 42*5113495bSYour Name u_int32_t d_GPIO_PIN1_OFFSET; 43*5113495bSYour Name u_int32_t d_GPIO_PIN0_CONFIG_MASK; 44*5113495bSYour Name u_int32_t d_GPIO_PIN1_CONFIG_MASK; 45*5113495bSYour Name u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; 46*5113495bSYour Name u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; 47*5113495bSYour Name u_int32_t d_SI_CONFIG_I2C_LSB; 48*5113495bSYour Name u_int32_t d_SI_CONFIG_I2C_MASK; 49*5113495bSYour Name u_int32_t d_SI_CONFIG_POS_SAMPLE_LSB; 50*5113495bSYour Name u_int32_t d_SI_CONFIG_POS_SAMPLE_MASK; 51*5113495bSYour Name u_int32_t d_SI_CONFIG_INACTIVE_CLK_LSB; 52*5113495bSYour Name u_int32_t d_SI_CONFIG_INACTIVE_CLK_MASK; 53*5113495bSYour Name u_int32_t d_SI_CONFIG_INACTIVE_DATA_LSB; 54*5113495bSYour Name u_int32_t d_SI_CONFIG_INACTIVE_DATA_MASK; 55*5113495bSYour Name u_int32_t d_SI_CONFIG_DIVIDER_LSB; 56*5113495bSYour Name u_int32_t d_SI_CONFIG_DIVIDER_MASK; 57*5113495bSYour Name u_int32_t d_SI_BASE_ADDRESS; 58*5113495bSYour Name u_int32_t d_SI_CONFIG_OFFSET; 59*5113495bSYour Name u_int32_t d_SI_TX_DATA0_OFFSET; 60*5113495bSYour Name u_int32_t d_SI_TX_DATA1_OFFSET; 61*5113495bSYour Name u_int32_t d_SI_RX_DATA0_OFFSET; 62*5113495bSYour Name u_int32_t d_SI_RX_DATA1_OFFSET; 63*5113495bSYour Name u_int32_t d_SI_CS_OFFSET; 64*5113495bSYour Name u_int32_t d_SI_CS_DONE_ERR_MASK; 65*5113495bSYour Name u_int32_t d_SI_CS_DONE_INT_MASK; 66*5113495bSYour Name u_int32_t d_SI_CS_START_LSB; 67*5113495bSYour Name u_int32_t d_SI_CS_START_MASK; 68*5113495bSYour Name u_int32_t d_SI_CS_RX_CNT_LSB; 69*5113495bSYour Name u_int32_t d_SI_CS_RX_CNT_MASK; 70*5113495bSYour Name u_int32_t d_SI_CS_TX_CNT_LSB; 71*5113495bSYour Name u_int32_t d_SI_CS_TX_CNT_MASK; 72*5113495bSYour Name u_int32_t d_BOARD_DATA_SZ; 73*5113495bSYour Name u_int32_t d_BOARD_EXT_DATA_SZ; 74*5113495bSYour Name u_int32_t d_MBOX_BASE_ADDRESS; 75*5113495bSYour Name u_int32_t d_LOCAL_SCRATCH_OFFSET; 76*5113495bSYour Name u_int32_t d_CPU_CLOCK_OFFSET; 77*5113495bSYour Name u_int32_t d_LPO_CAL_OFFSET; 78*5113495bSYour Name u_int32_t d_GPIO_PIN10_OFFSET; 79*5113495bSYour Name u_int32_t d_GPIO_PIN11_OFFSET; 80*5113495bSYour Name u_int32_t d_GPIO_PIN12_OFFSET; 81*5113495bSYour Name u_int32_t d_GPIO_PIN13_OFFSET; 82*5113495bSYour Name u_int32_t d_CLOCK_GPIO_OFFSET; 83*5113495bSYour Name u_int32_t d_CPU_CLOCK_STANDARD_LSB; 84*5113495bSYour Name u_int32_t d_CPU_CLOCK_STANDARD_MASK; 85*5113495bSYour Name u_int32_t d_LPO_CAL_ENABLE_LSB; 86*5113495bSYour Name u_int32_t d_LPO_CAL_ENABLE_MASK; 87*5113495bSYour Name u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; 88*5113495bSYour Name u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; 89*5113495bSYour Name u_int32_t d_ANALOG_INTF_BASE_ADDRESS; 90*5113495bSYour Name u_int32_t d_WLAN_MAC_BASE_ADDRESS; 91*5113495bSYour Name u_int32_t d_CE0_BASE_ADDRESS; 92*5113495bSYour Name u_int32_t d_CE1_BASE_ADDRESS; 93*5113495bSYour Name u_int32_t d_FW_INDICATOR_ADDRESS; 94*5113495bSYour Name u_int32_t d_DRAM_BASE_ADDRESS; 95*5113495bSYour Name u_int32_t d_SOC_CORE_BASE_ADDRESS; 96*5113495bSYour Name u_int32_t d_CORE_CTRL_ADDRESS; 97*5113495bSYour Name u_int32_t d_CE_COUNT; 98*5113495bSYour Name u_int32_t d_MSI_NUM_REQUEST; 99*5113495bSYour Name u_int32_t d_MSI_ASSIGN_FW; 100*5113495bSYour Name u_int32_t d_MSI_ASSIGN_CE_INITIAL; 101*5113495bSYour Name u_int32_t d_PCIE_INTR_ENABLE_ADDRESS; 102*5113495bSYour Name u_int32_t d_PCIE_INTR_CLR_ADDRESS; 103*5113495bSYour Name u_int32_t d_PCIE_INTR_FIRMWARE_MASK; 104*5113495bSYour Name u_int32_t d_PCIE_INTR_CE_MASK_ALL; 105*5113495bSYour Name u_int32_t d_CORE_CTRL_CPU_INTR_MASK; 106*5113495bSYour Name u_int32_t d_SR_WR_INDEX_ADDRESS; 107*5113495bSYour Name u_int32_t d_DST_WATERMARK_ADDRESS; 108*5113495bSYour Name 109*5113495bSYour Name /* htt_rx.c */ 110*5113495bSYour Name u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; 111*5113495bSYour Name u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; 112*5113495bSYour Name uint32_t d_RX_MPDU_START_0_RETRY_LSB; 113*5113495bSYour Name uint32_t d_RX_MPDU_START_0_RETRY_MASK; 114*5113495bSYour Name u_int32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; 115*5113495bSYour Name u_int32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; 116*5113495bSYour Name u_int32_t d_RX_MPDU_START_2_PN_47_32_LSB; 117*5113495bSYour Name u_int32_t d_RX_MPDU_START_2_PN_47_32_MASK; 118*5113495bSYour Name uint32_t d_RX_MPDU_START_2_TID_LSB; 119*5113495bSYour Name uint32_t d_RX_MPDU_START_2_TID_MASK; 120*5113495bSYour Name u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; 121*5113495bSYour Name u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; 122*5113495bSYour Name u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; 123*5113495bSYour Name u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; 124*5113495bSYour Name u_int32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; 125*5113495bSYour Name u_int32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; 126*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; 127*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; 128*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_FRAGMENT_MASK; 129*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_FRAGMENT_LSB; 130*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; 131*5113495bSYour Name u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; 132*5113495bSYour Name u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; 133*5113495bSYour Name u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; 134*5113495bSYour Name u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; 135*5113495bSYour Name u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; 136*5113495bSYour Name u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; 137*5113495bSYour Name u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; 138*5113495bSYour Name u_int32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; 139*5113495bSYour Name u_int32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; 140*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_MORE_DATA_MASK; 141*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; 142*5113495bSYour Name u_int32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; 143*5113495bSYour Name /* end */ 144*5113495bSYour Name /* copy_engine.c */ 145*5113495bSYour Name u_int32_t d_DST_WR_INDEX_ADDRESS; 146*5113495bSYour Name u_int32_t d_SRC_WATERMARK_ADDRESS; 147*5113495bSYour Name u_int32_t d_SRC_WATERMARK_LOW_MASK; 148*5113495bSYour Name u_int32_t d_SRC_WATERMARK_HIGH_MASK; 149*5113495bSYour Name u_int32_t d_DST_WATERMARK_LOW_MASK; 150*5113495bSYour Name u_int32_t d_DST_WATERMARK_HIGH_MASK; 151*5113495bSYour Name u_int32_t d_CURRENT_SRRI_ADDRESS; 152*5113495bSYour Name u_int32_t d_CURRENT_DRRI_ADDRESS; 153*5113495bSYour Name u_int32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; 154*5113495bSYour Name u_int32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; 155*5113495bSYour Name u_int32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; 156*5113495bSYour Name u_int32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; 157*5113495bSYour Name u_int32_t d_HOST_IS_ADDRESS; 158*5113495bSYour Name u_int32_t d_HOST_IS_COPY_COMPLETE_MASK; 159*5113495bSYour Name u_int32_t d_CE_WRAPPER_BASE_ADDRESS; 160*5113495bSYour Name u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; 161*5113495bSYour Name u_int32_t d_HOST_IE_ADDRESS; 162*5113495bSYour Name u_int32_t d_HOST_IE_COPY_COMPLETE_MASK; 163*5113495bSYour Name u_int32_t d_SR_BA_ADDRESS; 164*5113495bSYour Name u_int32_t d_SR_SIZE_ADDRESS; 165*5113495bSYour Name u_int32_t d_CE_CTRL1_ADDRESS; 166*5113495bSYour Name u_int32_t d_CE_CTRL1_DMAX_LENGTH_MASK; 167*5113495bSYour Name u_int32_t d_DR_BA_ADDRESS; 168*5113495bSYour Name u_int32_t d_DR_SIZE_ADDRESS; 169*5113495bSYour Name u_int32_t d_MISC_IE_ADDRESS; 170*5113495bSYour Name u_int32_t d_MISC_IS_AXI_ERR_MASK; 171*5113495bSYour Name u_int32_t d_MISC_IS_DST_ADDR_ERR_MASK; 172*5113495bSYour Name u_int32_t d_MISC_IS_SRC_LEN_ERR_MASK; 173*5113495bSYour Name u_int32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; 174*5113495bSYour Name u_int32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; 175*5113495bSYour Name u_int32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; 176*5113495bSYour Name u_int32_t d_SRC_WATERMARK_LOW_LSB; 177*5113495bSYour Name u_int32_t d_SRC_WATERMARK_HIGH_LSB; 178*5113495bSYour Name u_int32_t d_DST_WATERMARK_LOW_LSB; 179*5113495bSYour Name u_int32_t d_DST_WATERMARK_HIGH_LSB; 180*5113495bSYour Name u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; 181*5113495bSYour Name u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; 182*5113495bSYour Name u_int32_t d_CE_CTRL1_DMAX_LENGTH_LSB; 183*5113495bSYour Name u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; 184*5113495bSYour Name u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; 185*5113495bSYour Name u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; 186*5113495bSYour Name u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; 187*5113495bSYour Name u_int32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; 188*5113495bSYour Name u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; 189*5113495bSYour Name u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; 190*5113495bSYour Name u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; 191*5113495bSYour Name u_int32_t d_WLAN_DEBUG_CONTROL_OFFSET; 192*5113495bSYour Name u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; 193*5113495bSYour Name u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; 194*5113495bSYour Name u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; 195*5113495bSYour Name u_int32_t d_WLAN_DEBUG_OUT_OFFSET; 196*5113495bSYour Name u_int32_t d_WLAN_DEBUG_OUT_DATA_MSB; 197*5113495bSYour Name u_int32_t d_WLAN_DEBUG_OUT_DATA_LSB; 198*5113495bSYour Name u_int32_t d_WLAN_DEBUG_OUT_DATA_MASK; 199*5113495bSYour Name u_int32_t d_AMBA_DEBUG_BUS_OFFSET; 200*5113495bSYour Name u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB; 201*5113495bSYour Name u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB; 202*5113495bSYour Name u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK; 203*5113495bSYour Name u_int32_t d_AMBA_DEBUG_BUS_SEL_MSB; 204*5113495bSYour Name u_int32_t d_AMBA_DEBUG_BUS_SEL_LSB; 205*5113495bSYour Name u_int32_t d_AMBA_DEBUG_BUS_SEL_MASK; 206*5113495bSYour Name u_int32_t d_CE_WRAPPER_DEBUG_OFFSET; 207*5113495bSYour Name u_int32_t d_CE_WRAPPER_DEBUG_SEL_MSB; 208*5113495bSYour Name u_int32_t d_CE_WRAPPER_DEBUG_SEL_LSB; 209*5113495bSYour Name u_int32_t d_CE_WRAPPER_DEBUG_SEL_MASK; 210*5113495bSYour Name u_int32_t d_CE_DEBUG_OFFSET; 211*5113495bSYour Name u_int32_t d_CE_DEBUG_SEL_MSB; 212*5113495bSYour Name u_int32_t d_CE_DEBUG_SEL_LSB; 213*5113495bSYour Name u_int32_t d_CE_DEBUG_SEL_MASK; 214*5113495bSYour Name /* end */ 215*5113495bSYour Name /* PLL start */ 216*5113495bSYour Name u_int32_t d_EFUSE_OFFSET; 217*5113495bSYour Name u_int32_t d_EFUSE_XTAL_SEL_MSB; 218*5113495bSYour Name u_int32_t d_EFUSE_XTAL_SEL_LSB; 219*5113495bSYour Name u_int32_t d_EFUSE_XTAL_SEL_MASK; 220*5113495bSYour Name u_int32_t d_BB_PLL_CONFIG_OFFSET; 221*5113495bSYour Name u_int32_t d_BB_PLL_CONFIG_OUTDIV_MSB; 222*5113495bSYour Name u_int32_t d_BB_PLL_CONFIG_OUTDIV_LSB; 223*5113495bSYour Name u_int32_t d_BB_PLL_CONFIG_OUTDIV_MASK; 224*5113495bSYour Name u_int32_t d_BB_PLL_CONFIG_FRAC_MSB; 225*5113495bSYour Name u_int32_t d_BB_PLL_CONFIG_FRAC_LSB; 226*5113495bSYour Name u_int32_t d_BB_PLL_CONFIG_FRAC_MASK; 227*5113495bSYour Name u_int32_t d_WLAN_PLL_SETTLE_TIME_MSB; 228*5113495bSYour Name u_int32_t d_WLAN_PLL_SETTLE_TIME_LSB; 229*5113495bSYour Name u_int32_t d_WLAN_PLL_SETTLE_TIME_MASK; 230*5113495bSYour Name u_int32_t d_WLAN_PLL_SETTLE_OFFSET; 231*5113495bSYour Name u_int32_t d_WLAN_PLL_SETTLE_SW_MASK; 232*5113495bSYour Name u_int32_t d_WLAN_PLL_SETTLE_RSTMASK; 233*5113495bSYour Name u_int32_t d_WLAN_PLL_SETTLE_RESET; 234*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; 235*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; 236*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; 237*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; 238*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; 239*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; 240*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; 241*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; 242*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; 243*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; 244*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; 245*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; 246*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; 247*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; 248*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; 249*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_DIV_MSB; 250*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_DIV_LSB; 251*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_DIV_MASK; 252*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_DIV_RESET; 253*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_OFFSET; 254*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_SW_MASK; 255*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_RSTMASK; 256*5113495bSYour Name u_int32_t d_WLAN_PLL_CONTROL_RESET; 257*5113495bSYour Name u_int32_t d_SOC_CORE_CLK_CTRL_OFFSET; 258*5113495bSYour Name u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; 259*5113495bSYour Name u_int32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; 260*5113495bSYour Name u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; 261*5113495bSYour Name u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; 262*5113495bSYour Name u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; 263*5113495bSYour Name u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; 264*5113495bSYour Name u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; 265*5113495bSYour Name u_int32_t d_RTC_SYNC_STATUS_OFFSET; 266*5113495bSYour Name u_int32_t d_SOC_CPU_CLOCK_OFFSET; 267*5113495bSYour Name u_int32_t d_SOC_CPU_CLOCK_STANDARD_MSB; 268*5113495bSYour Name u_int32_t d_SOC_CPU_CLOCK_STANDARD_LSB; 269*5113495bSYour Name u_int32_t d_SOC_CPU_CLOCK_STANDARD_MASK; 270*5113495bSYour Name /* PLL end */ 271*5113495bSYour Name u_int32_t d_SOC_POWER_REG_OFFSET; 272*5113495bSYour Name u_int32_t d_PCIE_INTR_CAUSE_ADDRESS; 273*5113495bSYour Name u_int32_t d_SOC_RESET_CONTROL_ADDRESS; 274*5113495bSYour Name u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK; 275*5113495bSYour Name u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB; 276*5113495bSYour Name u_int32_t d_SOC_RESET_CONTROL_CE_RST_MASK; 277*5113495bSYour Name u_int32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 278*5113495bSYour Name u_int32_t d_CPU_INTR_ADDRESS; 279*5113495bSYour Name u_int32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; 280*5113495bSYour Name u_int32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 281*5113495bSYour Name u_int32_t d_SOC_LF_TIMER_STATUS0_ADDRESS; 282*5113495bSYour Name /* chip id start */ 283*5113495bSYour Name u_int32_t d_SOC_CHIP_ID_ADDRESS; 284*5113495bSYour Name u_int32_t d_SOC_CHIP_ID_VERSION_MASK; 285*5113495bSYour Name u_int32_t d_SOC_CHIP_ID_VERSION_LSB; 286*5113495bSYour Name u_int32_t d_SOC_CHIP_ID_REVISION_MASK; 287*5113495bSYour Name u_int32_t d_SOC_CHIP_ID_REVISION_LSB; 288*5113495bSYour Name /* chip id end */ 289*5113495bSYour Name }; 290*5113495bSYour Name 291*5113495bSYour Name #define RTC_SOC_BASE_ADDRESS \ 292*5113495bSYour Name (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 293*5113495bSYour Name #define RTC_WMAC_BASE_ADDRESS \ 294*5113495bSYour Name (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 295*5113495bSYour Name #define SYSTEM_SLEEP_OFFSET \ 296*5113495bSYour Name (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 297*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_OFFSET \ 298*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 299*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 300*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 301*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 302*5113495bSYour Name (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 303*5113495bSYour Name #define CLOCK_CONTROL_OFFSET \ 304*5113495bSYour Name (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 305*5113495bSYour Name #define CLOCK_CONTROL_SI0_CLK_MASK \ 306*5113495bSYour Name (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 307*5113495bSYour Name #define RESET_CONTROL_OFFSET \ 308*5113495bSYour Name (scn->targetdef->d_RESET_CONTROL_OFFSET) 309*5113495bSYour Name #define RESET_CONTROL_MBOX_RST_MASK \ 310*5113495bSYour Name (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 311*5113495bSYour Name #define RESET_CONTROL_SI0_RST_MASK \ 312*5113495bSYour Name (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 313*5113495bSYour Name #define WLAN_RESET_CONTROL_OFFSET \ 314*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 315*5113495bSYour Name #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 316*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 317*5113495bSYour Name #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 318*5113495bSYour Name (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 319*5113495bSYour Name #define GPIO_BASE_ADDRESS \ 320*5113495bSYour Name (scn->targetdef->d_GPIO_BASE_ADDRESS) 321*5113495bSYour Name #define GPIO_PIN0_OFFSET \ 322*5113495bSYour Name (scn->targetdef->d_GPIO_PIN0_OFFSET) 323*5113495bSYour Name #define GPIO_PIN1_OFFSET \ 324*5113495bSYour Name (scn->targetdef->d_GPIO_PIN1_OFFSET) 325*5113495bSYour Name #define GPIO_PIN0_CONFIG_MASK \ 326*5113495bSYour Name (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 327*5113495bSYour Name #define GPIO_PIN1_CONFIG_MASK \ 328*5113495bSYour Name (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 329*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 330*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 331*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 332*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 333*5113495bSYour Name #define SI_CONFIG_I2C_LSB \ 334*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_I2C_LSB) 335*5113495bSYour Name #define SI_CONFIG_I2C_MASK \ 336*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_I2C_MASK) 337*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_LSB \ 338*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 339*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_MASK \ 340*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 341*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_LSB \ 342*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 343*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_MASK \ 344*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 345*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_LSB \ 346*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 347*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_MASK \ 348*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 349*5113495bSYour Name #define SI_CONFIG_DIVIDER_LSB \ 350*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 351*5113495bSYour Name #define SI_CONFIG_DIVIDER_MASK \ 352*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 353*5113495bSYour Name #define SI_BASE_ADDRESS \ 354*5113495bSYour Name (scn->targetdef->d_SI_BASE_ADDRESS) 355*5113495bSYour Name #define SI_CONFIG_OFFSET \ 356*5113495bSYour Name (scn->targetdef->d_SI_CONFIG_OFFSET) 357*5113495bSYour Name #define SI_TX_DATA0_OFFSET \ 358*5113495bSYour Name (scn->targetdef->d_SI_TX_DATA0_OFFSET) 359*5113495bSYour Name #define SI_TX_DATA1_OFFSET \ 360*5113495bSYour Name (scn->targetdef->d_SI_TX_DATA1_OFFSET) 361*5113495bSYour Name #define SI_RX_DATA0_OFFSET \ 362*5113495bSYour Name (scn->targetdef->d_SI_RX_DATA0_OFFSET) 363*5113495bSYour Name #define SI_RX_DATA1_OFFSET \ 364*5113495bSYour Name (scn->targetdef->d_SI_RX_DATA1_OFFSET) 365*5113495bSYour Name #define SI_CS_OFFSET \ 366*5113495bSYour Name (scn->targetdef->d_SI_CS_OFFSET) 367*5113495bSYour Name #define SI_CS_DONE_ERR_MASK \ 368*5113495bSYour Name (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 369*5113495bSYour Name #define SI_CS_DONE_INT_MASK \ 370*5113495bSYour Name (scn->targetdef->d_SI_CS_DONE_INT_MASK) 371*5113495bSYour Name #define SI_CS_START_LSB \ 372*5113495bSYour Name (scn->targetdef->d_SI_CS_START_LSB) 373*5113495bSYour Name #define SI_CS_START_MASK \ 374*5113495bSYour Name (scn->targetdef->d_SI_CS_START_MASK) 375*5113495bSYour Name #define SI_CS_RX_CNT_LSB \ 376*5113495bSYour Name (scn->targetdef->d_SI_CS_RX_CNT_LSB) 377*5113495bSYour Name #define SI_CS_RX_CNT_MASK \ 378*5113495bSYour Name (scn->targetdef->d_SI_CS_RX_CNT_MASK) 379*5113495bSYour Name #define SI_CS_TX_CNT_LSB \ 380*5113495bSYour Name (scn->targetdef->d_SI_CS_TX_CNT_LSB) 381*5113495bSYour Name #define SI_CS_TX_CNT_MASK \ 382*5113495bSYour Name (scn->targetdef->d_SI_CS_TX_CNT_MASK) 383*5113495bSYour Name #define EEPROM_SZ \ 384*5113495bSYour Name (scn->targetdef->d_BOARD_DATA_SZ) 385*5113495bSYour Name #define EEPROM_EXT_SZ \ 386*5113495bSYour Name (scn->targetdef->d_BOARD_EXT_DATA_SZ) 387*5113495bSYour Name #define MBOX_BASE_ADDRESS \ 388*5113495bSYour Name (scn->targetdef->d_MBOX_BASE_ADDRESS) 389*5113495bSYour Name #define LOCAL_SCRATCH_OFFSET \ 390*5113495bSYour Name (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 391*5113495bSYour Name #define CPU_CLOCK_OFFSET \ 392*5113495bSYour Name (scn->targetdef->d_CPU_CLOCK_OFFSET) 393*5113495bSYour Name #define LPO_CAL_OFFSET \ 394*5113495bSYour Name (scn->targetdef->d_LPO_CAL_OFFSET) 395*5113495bSYour Name #define GPIO_PIN10_OFFSET \ 396*5113495bSYour Name (scn->targetdef->d_GPIO_PIN10_OFFSET) 397*5113495bSYour Name #define GPIO_PIN11_OFFSET \ 398*5113495bSYour Name (scn->targetdef->d_GPIO_PIN11_OFFSET) 399*5113495bSYour Name #define GPIO_PIN12_OFFSET \ 400*5113495bSYour Name (scn->targetdef->d_GPIO_PIN12_OFFSET) 401*5113495bSYour Name #define GPIO_PIN13_OFFSET \ 402*5113495bSYour Name (scn->targetdef->d_GPIO_PIN13_OFFSET) 403*5113495bSYour Name #define CLOCK_GPIO_OFFSET \ 404*5113495bSYour Name (scn->targetdef->d_CLOCK_GPIO_OFFSET) 405*5113495bSYour Name #define CPU_CLOCK_STANDARD_LSB \ 406*5113495bSYour Name (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 407*5113495bSYour Name #define CPU_CLOCK_STANDARD_MASK \ 408*5113495bSYour Name (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 409*5113495bSYour Name #define LPO_CAL_ENABLE_LSB \ 410*5113495bSYour Name (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 411*5113495bSYour Name #define LPO_CAL_ENABLE_MASK \ 412*5113495bSYour Name (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 413*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 414*5113495bSYour Name (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 415*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 416*5113495bSYour Name (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 417*5113495bSYour Name #define ANALOG_INTF_BASE_ADDRESS \ 418*5113495bSYour Name (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 419*5113495bSYour Name #define WLAN_MAC_BASE_ADDRESS \ 420*5113495bSYour Name (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 421*5113495bSYour Name #define CE0_BASE_ADDRESS \ 422*5113495bSYour Name (scn->targetdef->d_CE0_BASE_ADDRESS) 423*5113495bSYour Name #define CE1_BASE_ADDRESS \ 424*5113495bSYour Name (scn->targetdef->d_CE1_BASE_ADDRESS) 425*5113495bSYour Name #define FW_INDICATOR_ADDRESS \ 426*5113495bSYour Name (scn->targetdef->d_FW_INDICATOR_ADDRESS) 427*5113495bSYour Name #define DRAM_BASE_ADDRESS \ 428*5113495bSYour Name (scn->targetdef->d_DRAM_BASE_ADDRESS) 429*5113495bSYour Name #define SOC_CORE_BASE_ADDRESS \ 430*5113495bSYour Name (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 431*5113495bSYour Name #define CORE_CTRL_ADDRESS \ 432*5113495bSYour Name (scn->targetdef->d_CORE_CTRL_ADDRESS) 433*5113495bSYour Name #define CE_COUNT \ 434*5113495bSYour Name (scn->targetdef->d_CE_COUNT) 435*5113495bSYour Name #define PCIE_INTR_ENABLE_ADDRESS \ 436*5113495bSYour Name (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS) 437*5113495bSYour Name #define PCIE_INTR_CLR_ADDRESS \ 438*5113495bSYour Name (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS) 439*5113495bSYour Name #define PCIE_INTR_FIRMWARE_MASK \ 440*5113495bSYour Name (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK) 441*5113495bSYour Name #define PCIE_INTR_CE_MASK_ALL \ 442*5113495bSYour Name (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL) 443*5113495bSYour Name #define CORE_CTRL_CPU_INTR_MASK \ 444*5113495bSYour Name (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 445*5113495bSYour Name #define PCIE_INTR_CAUSE_ADDRESS \ 446*5113495bSYour Name (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS) 447*5113495bSYour Name #define SOC_RESET_CONTROL_ADDRESS \ 448*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 449*5113495bSYour Name #define SOC_RESET_CONTROL_CE_RST_MASK \ 450*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK) 451*5113495bSYour Name #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK\ 452*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 453*5113495bSYour Name #define CPU_INTR_ADDRESS \ 454*5113495bSYour Name (scn->targetdef->d_CPU_INTR_ADDRESS) 455*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 456*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 457*5113495bSYour Name #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 458*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 459*5113495bSYour Name #define SOC_LF_TIMER_STATUS0_ADDRESS \ 460*5113495bSYour Name (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS) 461*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \ 462*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 463*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \ 464*5113495bSYour Name (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 465*5113495bSYour Name 466*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \ 467*5113495bSYour Name (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \ 468*5113495bSYour Name SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 469*5113495bSYour Name #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \ 470*5113495bSYour Name (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \ 471*5113495bSYour Name SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 472*5113495bSYour Name 473*5113495bSYour Name /* hif_pci.c */ 474*5113495bSYour Name #define CHIP_ID_ADDRESS \ 475*5113495bSYour Name (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 476*5113495bSYour Name #define SOC_CHIP_ID_REVISION_MASK \ 477*5113495bSYour Name (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 478*5113495bSYour Name #define SOC_CHIP_ID_REVISION_LSB \ 479*5113495bSYour Name (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 480*5113495bSYour Name #define SOC_CHIP_ID_VERSION_MASK \ 481*5113495bSYour Name (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 482*5113495bSYour Name #define SOC_CHIP_ID_VERSION_LSB \ 483*5113495bSYour Name (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 484*5113495bSYour Name #define CHIP_ID_REVISION_GET(x) \ 485*5113495bSYour Name (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 486*5113495bSYour Name #define CHIP_ID_VERSION_GET(x) \ 487*5113495bSYour Name (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 488*5113495bSYour Name /* hif_pci.c end */ 489*5113495bSYour Name 490*5113495bSYour Name /* misc */ 491*5113495bSYour Name #define SR_WR_INDEX_ADDRESS \ 492*5113495bSYour Name (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 493*5113495bSYour Name #define DST_WATERMARK_ADDRESS \ 494*5113495bSYour Name (scn->targetdef->d_DST_WATERMARK_ADDRESS) 495*5113495bSYour Name #define SOC_POWER_REG_OFFSET \ 496*5113495bSYour Name (scn->targetdef->d_SOC_POWER_REG_OFFSET) 497*5113495bSYour Name /* end */ 498*5113495bSYour Name 499*5113495bSYour Name /* copy_engine.c */ 500*5113495bSYour Name #define DST_WR_INDEX_ADDRESS \ 501*5113495bSYour Name (scn->targetdef->d_DST_WR_INDEX_ADDRESS) 502*5113495bSYour Name #define SRC_WATERMARK_ADDRESS \ 503*5113495bSYour Name (scn->targetdef->d_SRC_WATERMARK_ADDRESS) 504*5113495bSYour Name #define SRC_WATERMARK_LOW_MASK \ 505*5113495bSYour Name (scn->targetdef->d_SRC_WATERMARK_LOW_MASK) 506*5113495bSYour Name #define SRC_WATERMARK_HIGH_MASK \ 507*5113495bSYour Name (scn->targetdef->d_SRC_WATERMARK_HIGH_MASK) 508*5113495bSYour Name #define DST_WATERMARK_LOW_MASK \ 509*5113495bSYour Name (scn->targetdef->d_DST_WATERMARK_LOW_MASK) 510*5113495bSYour Name #define DST_WATERMARK_HIGH_MASK \ 511*5113495bSYour Name (scn->targetdef->d_DST_WATERMARK_HIGH_MASK) 512*5113495bSYour Name #define CURRENT_SRRI_ADDRESS \ 513*5113495bSYour Name (scn->targetdef->d_CURRENT_SRRI_ADDRESS) 514*5113495bSYour Name #define CURRENT_DRRI_ADDRESS \ 515*5113495bSYour Name (scn->targetdef->d_CURRENT_DRRI_ADDRESS) 516*5113495bSYour Name #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ 517*5113495bSYour Name (scn->targetdef->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK) 518*5113495bSYour Name #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK\ 519*5113495bSYour Name (scn->targetdef->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK) 520*5113495bSYour Name #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ 521*5113495bSYour Name (scn->targetdef->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 522*5113495bSYour Name #define HOST_IS_DST_RING_LOW_WATERMARK_MASK\ 523*5113495bSYour Name (scn->targetdef->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK) 524*5113495bSYour Name #define HOST_IS_ADDRESS \ 525*5113495bSYour Name (scn->targetdef->d_HOST_IS_ADDRESS) 526*5113495bSYour Name #define HOST_IS_COPY_COMPLETE_MASK \ 527*5113495bSYour Name (scn->targetdef->d_HOST_IS_COPY_COMPLETE_MASK) 528*5113495bSYour Name #define CE_WRAPPER_BASE_ADDRESS \ 529*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_BASE_ADDRESS) 530*5113495bSYour Name #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \ 531*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS) 532*5113495bSYour Name #define HOST_IE_ADDRESS \ 533*5113495bSYour Name (scn->targetdef->d_HOST_IE_ADDRESS) 534*5113495bSYour Name #define HOST_IE_COPY_COMPLETE_MASK \ 535*5113495bSYour Name (scn->targetdef->d_HOST_IE_COPY_COMPLETE_MASK) 536*5113495bSYour Name #define SR_BA_ADDRESS \ 537*5113495bSYour Name (scn->targetdef->d_SR_BA_ADDRESS) 538*5113495bSYour Name #define SR_SIZE_ADDRESS \ 539*5113495bSYour Name (scn->targetdef->d_SR_SIZE_ADDRESS) 540*5113495bSYour Name #define CE_CTRL1_ADDRESS \ 541*5113495bSYour Name (scn->targetdef->d_CE_CTRL1_ADDRESS) 542*5113495bSYour Name #define CE_CTRL1_DMAX_LENGTH_MASK \ 543*5113495bSYour Name (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_MASK) 544*5113495bSYour Name #define DR_BA_ADDRESS \ 545*5113495bSYour Name (scn->targetdef->d_DR_BA_ADDRESS) 546*5113495bSYour Name #define DR_SIZE_ADDRESS \ 547*5113495bSYour Name (scn->targetdef->d_DR_SIZE_ADDRESS) 548*5113495bSYour Name #define MISC_IE_ADDRESS \ 549*5113495bSYour Name (scn->targetdef->d_MISC_IE_ADDRESS) 550*5113495bSYour Name #define MISC_IS_AXI_ERR_MASK \ 551*5113495bSYour Name (scn->targetdef->d_MISC_IS_AXI_ERR_MASK) 552*5113495bSYour Name #define MISC_IS_DST_ADDR_ERR_MASK \ 553*5113495bSYour Name (scn->targetdef->d_MISC_IS_DST_ADDR_ERR_MASK) 554*5113495bSYour Name #define MISC_IS_SRC_LEN_ERR_MASK \ 555*5113495bSYour Name (scn->targetdef->d_MISC_IS_SRC_LEN_ERR_MASK) 556*5113495bSYour Name #define MISC_IS_DST_MAX_LEN_VIO_MASK \ 557*5113495bSYour Name (scn->targetdef->d_MISC_IS_DST_MAX_LEN_VIO_MASK) 558*5113495bSYour Name #define MISC_IS_DST_RING_OVERFLOW_MASK \ 559*5113495bSYour Name (scn->targetdef->d_MISC_IS_DST_RING_OVERFLOW_MASK) 560*5113495bSYour Name #define MISC_IS_SRC_RING_OVERFLOW_MASK \ 561*5113495bSYour Name (scn->targetdef->d_MISC_IS_SRC_RING_OVERFLOW_MASK) 562*5113495bSYour Name #define SRC_WATERMARK_LOW_LSB \ 563*5113495bSYour Name (scn->targetdef->d_SRC_WATERMARK_LOW_LSB) 564*5113495bSYour Name #define SRC_WATERMARK_HIGH_LSB \ 565*5113495bSYour Name (scn->targetdef->d_SRC_WATERMARK_HIGH_LSB) 566*5113495bSYour Name #define DST_WATERMARK_LOW_LSB \ 567*5113495bSYour Name (scn->targetdef->d_DST_WATERMARK_LOW_LSB) 568*5113495bSYour Name #define DST_WATERMARK_HIGH_LSB \ 569*5113495bSYour Name (scn->targetdef->d_DST_WATERMARK_HIGH_LSB) 570*5113495bSYour Name #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 571*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) 572*5113495bSYour Name #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 573*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 574*5113495bSYour Name #define CE_CTRL1_DMAX_LENGTH_LSB \ 575*5113495bSYour Name (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_LSB) 576*5113495bSYour Name #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK\ 577*5113495bSYour Name (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 578*5113495bSYour Name #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK\ 579*5113495bSYour Name (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 580*5113495bSYour Name #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ 581*5113495bSYour Name (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 582*5113495bSYour Name #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ 583*5113495bSYour Name (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) 584*5113495bSYour Name #define WLAN_DEBUG_INPUT_SEL_OFFSET \ 585*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET) 586*5113495bSYour Name #define WLAN_DEBUG_INPUT_SEL_SRC_MSB \ 587*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB) 588*5113495bSYour Name #define WLAN_DEBUG_INPUT_SEL_SRC_LSB \ 589*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB) 590*5113495bSYour Name #define WLAN_DEBUG_INPUT_SEL_SRC_MASK \ 591*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK) 592*5113495bSYour Name #define WLAN_DEBUG_CONTROL_OFFSET \ 593*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET) 594*5113495bSYour Name #define WLAN_DEBUG_CONTROL_ENABLE_MSB \ 595*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB) 596*5113495bSYour Name #define WLAN_DEBUG_CONTROL_ENABLE_LSB \ 597*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB) 598*5113495bSYour Name #define WLAN_DEBUG_CONTROL_ENABLE_MASK \ 599*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK) 600*5113495bSYour Name #define WLAN_DEBUG_OUT_OFFSET \ 601*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET) 602*5113495bSYour Name #define WLAN_DEBUG_OUT_DATA_MSB \ 603*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB) 604*5113495bSYour Name #define WLAN_DEBUG_OUT_DATA_LSB \ 605*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB) 606*5113495bSYour Name #define WLAN_DEBUG_OUT_DATA_MASK \ 607*5113495bSYour Name (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK) 608*5113495bSYour Name #define AMBA_DEBUG_BUS_OFFSET \ 609*5113495bSYour Name (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET) 610*5113495bSYour Name #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \ 611*5113495bSYour Name (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB) 612*5113495bSYour Name #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \ 613*5113495bSYour Name (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 614*5113495bSYour Name #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \ 615*5113495bSYour Name (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 616*5113495bSYour Name #define AMBA_DEBUG_BUS_SEL_MSB \ 617*5113495bSYour Name (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB) 618*5113495bSYour Name #define AMBA_DEBUG_BUS_SEL_LSB \ 619*5113495bSYour Name (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB) 620*5113495bSYour Name #define AMBA_DEBUG_BUS_SEL_MASK \ 621*5113495bSYour Name (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK) 622*5113495bSYour Name #define CE_WRAPPER_DEBUG_OFFSET \ 623*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_DEBUG_OFFSET) 624*5113495bSYour Name #define CE_WRAPPER_DEBUG_SEL_MSB \ 625*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MSB) 626*5113495bSYour Name #define CE_WRAPPER_DEBUG_SEL_LSB \ 627*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_LSB) 628*5113495bSYour Name #define CE_WRAPPER_DEBUG_SEL_MASK \ 629*5113495bSYour Name (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MASK) 630*5113495bSYour Name #define CE_DEBUG_OFFSET \ 631*5113495bSYour Name (scn->targetdef->d_CE_DEBUG_OFFSET) 632*5113495bSYour Name #define CE_DEBUG_SEL_MSB \ 633*5113495bSYour Name (scn->targetdef->d_CE_DEBUG_SEL_MSB) 634*5113495bSYour Name #define CE_DEBUG_SEL_LSB \ 635*5113495bSYour Name (scn->targetdef->d_CE_DEBUG_SEL_LSB) 636*5113495bSYour Name #define CE_DEBUG_SEL_MASK \ 637*5113495bSYour Name (scn->targetdef->d_CE_DEBUG_SEL_MASK) 638*5113495bSYour Name /* end */ 639*5113495bSYour Name /* PLL start */ 640*5113495bSYour Name #define EFUSE_OFFSET \ 641*5113495bSYour Name (scn->targetdef->d_EFUSE_OFFSET) 642*5113495bSYour Name #define EFUSE_XTAL_SEL_MSB \ 643*5113495bSYour Name (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 644*5113495bSYour Name #define EFUSE_XTAL_SEL_LSB \ 645*5113495bSYour Name (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 646*5113495bSYour Name #define EFUSE_XTAL_SEL_MASK \ 647*5113495bSYour Name (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 648*5113495bSYour Name #define BB_PLL_CONFIG_OFFSET \ 649*5113495bSYour Name (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 650*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_MSB \ 651*5113495bSYour Name (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 652*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_LSB \ 653*5113495bSYour Name (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 654*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_MASK \ 655*5113495bSYour Name (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 656*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_MSB \ 657*5113495bSYour Name (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 658*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_LSB \ 659*5113495bSYour Name (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 660*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_MASK \ 661*5113495bSYour Name (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 662*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_MSB \ 663*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 664*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_LSB \ 665*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 666*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_MASK \ 667*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 668*5113495bSYour Name #define WLAN_PLL_SETTLE_OFFSET \ 669*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 670*5113495bSYour Name #define WLAN_PLL_SETTLE_SW_MASK \ 671*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 672*5113495bSYour Name #define WLAN_PLL_SETTLE_RSTMASK \ 673*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 674*5113495bSYour Name #define WLAN_PLL_SETTLE_RESET \ 675*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 676*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_MSB \ 677*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 678*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_LSB \ 679*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 680*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_MASK \ 681*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 682*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_MSB \ 683*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 684*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_LSB \ 685*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 686*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_MASK \ 687*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 688*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_RESET \ 689*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 690*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 691*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 692*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 693*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 694*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 695*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 696*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 697*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 698*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_MSB \ 699*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 700*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_LSB \ 701*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 702*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_MASK \ 703*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 704*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_RESET \ 705*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 706*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_MSB \ 707*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 708*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_LSB \ 709*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 710*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_MASK \ 711*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 712*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_RESET \ 713*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 714*5113495bSYour Name #define WLAN_PLL_CONTROL_OFFSET \ 715*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 716*5113495bSYour Name #define WLAN_PLL_CONTROL_SW_MASK \ 717*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 718*5113495bSYour Name #define WLAN_PLL_CONTROL_RSTMASK \ 719*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 720*5113495bSYour Name #define WLAN_PLL_CONTROL_RESET \ 721*5113495bSYour Name (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 722*5113495bSYour Name #define SOC_CORE_CLK_CTRL_OFFSET \ 723*5113495bSYour Name (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 724*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_MSB \ 725*5113495bSYour Name (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 726*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_LSB \ 727*5113495bSYour Name (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 728*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_MASK \ 729*5113495bSYour Name (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 730*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 731*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 732*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 733*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 734*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 735*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 736*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 737*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 738*5113495bSYour Name #define RTC_SYNC_STATUS_OFFSET \ 739*5113495bSYour Name (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 740*5113495bSYour Name #define SOC_CPU_CLOCK_OFFSET \ 741*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 742*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_MSB \ 743*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 744*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_LSB \ 745*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 746*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_MASK \ 747*5113495bSYour Name (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 748*5113495bSYour Name /* PLL end */ 749*5113495bSYour Name 750*5113495bSYour Name /* SET macros */ 751*5113495bSYour Name #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 752*5113495bSYour Name (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 753*5113495bSYour Name WLAN_SYSTEM_SLEEP_DISABLE_MASK) 754*5113495bSYour Name #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 755*5113495bSYour Name (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & \ 756*5113495bSYour Name SI_CONFIG_BIDIR_OD_DATA_MASK) 757*5113495bSYour Name #define SI_CONFIG_I2C_SET(x) \ 758*5113495bSYour Name (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 759*5113495bSYour Name #define SI_CONFIG_POS_SAMPLE_SET(x) \ 760*5113495bSYour Name (((x) << SI_CONFIG_POS_SAMPLE_LSB) & \ 761*5113495bSYour Name SI_CONFIG_POS_SAMPLE_MASK) 762*5113495bSYour Name #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 763*5113495bSYour Name (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & \ 764*5113495bSYour Name SI_CONFIG_INACTIVE_CLK_MASK) 765*5113495bSYour Name #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 766*5113495bSYour Name (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & \ 767*5113495bSYour Name SI_CONFIG_INACTIVE_DATA_MASK) 768*5113495bSYour Name #define SI_CONFIG_DIVIDER_SET(x) \ 769*5113495bSYour Name (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 770*5113495bSYour Name #define SI_CS_START_SET(x) \ 771*5113495bSYour Name (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 772*5113495bSYour Name #define SI_CS_RX_CNT_SET(x) \ 773*5113495bSYour Name (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 774*5113495bSYour Name #define SI_CS_TX_CNT_SET(x) \ 775*5113495bSYour Name (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 776*5113495bSYour Name #define LPO_CAL_ENABLE_SET(x) \ 777*5113495bSYour Name (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 778*5113495bSYour Name #define CPU_CLOCK_STANDARD_SET(x) \ 779*5113495bSYour Name (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 780*5113495bSYour Name #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 781*5113495bSYour Name (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & \ 782*5113495bSYour Name CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 783*5113495bSYour Name /* copy_engine.c */ 784*5113495bSYour Name #define SRC_WATERMARK_LOW_SET(x) \ 785*5113495bSYour Name (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 786*5113495bSYour Name #define SRC_WATERMARK_HIGH_SET(x) \ 787*5113495bSYour Name (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 788*5113495bSYour Name #define DST_WATERMARK_LOW_SET(x) \ 789*5113495bSYour Name (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 790*5113495bSYour Name #define DST_WATERMARK_HIGH_SET(x) \ 791*5113495bSYour Name (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 792*5113495bSYour Name #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) (((x) & \ 793*5113495bSYour Name CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 794*5113495bSYour Name CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 795*5113495bSYour Name #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 796*5113495bSYour Name (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 797*5113495bSYour Name #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 798*5113495bSYour Name (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 799*5113495bSYour Name CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 800*5113495bSYour Name #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 801*5113495bSYour Name (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 802*5113495bSYour Name CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 803*5113495bSYour Name #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \ 804*5113495bSYour Name (((x) & \ 805*5113495bSYour Name WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \ 806*5113495bSYour Name WLAN_DEBUG_INPUT_SEL_SRC_LSB) 807*5113495bSYour Name #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \ 808*5113495bSYour Name (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \ 809*5113495bSYour Name WLAN_DEBUG_INPUT_SEL_SRC_MASK) 810*5113495bSYour Name #define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \ 811*5113495bSYour Name (((x) & \ 812*5113495bSYour Name WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \ 813*5113495bSYour Name WLAN_DEBUG_CONTROL_ENABLE_LSB) 814*5113495bSYour Name #define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \ 815*5113495bSYour Name (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \ 816*5113495bSYour Name WLAN_DEBUG_CONTROL_ENABLE_MASK) 817*5113495bSYour Name #define WLAN_DEBUG_OUT_DATA_GET(x) \ 818*5113495bSYour Name (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) 819*5113495bSYour Name #define WLAN_DEBUG_OUT_DATA_SET(x) \ 820*5113495bSYour Name (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) 821*5113495bSYour Name #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \ 822*5113495bSYour Name (((x) & \ 823*5113495bSYour Name AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \ 824*5113495bSYour Name AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 825*5113495bSYour Name #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \ 826*5113495bSYour Name (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \ 827*5113495bSYour Name AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 828*5113495bSYour Name #define AMBA_DEBUG_BUS_SEL_GET(x) \ 829*5113495bSYour Name (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB) 830*5113495bSYour Name #define AMBA_DEBUG_BUS_SEL_SET(x) \ 831*5113495bSYour Name (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK) 832*5113495bSYour Name #define CE_WRAPPER_DEBUG_SEL_GET(x) \ 833*5113495bSYour Name (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB) 834*5113495bSYour Name #define CE_WRAPPER_DEBUG_SEL_SET(x) \ 835*5113495bSYour Name (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK) 836*5113495bSYour Name #define CE_DEBUG_SEL_GET(x) \ 837*5113495bSYour Name (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB) 838*5113495bSYour Name #define CE_DEBUG_SEL_SET(x) \ 839*5113495bSYour Name (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK) 840*5113495bSYour Name /* end */ 841*5113495bSYour Name /* PLL start */ 842*5113495bSYour Name #define EFUSE_XTAL_SEL_GET(x) \ 843*5113495bSYour Name (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 844*5113495bSYour Name #define EFUSE_XTAL_SEL_SET(x) \ 845*5113495bSYour Name (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 846*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 847*5113495bSYour Name (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 848*5113495bSYour Name #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 849*5113495bSYour Name (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 850*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_GET(x) \ 851*5113495bSYour Name (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 852*5113495bSYour Name #define BB_PLL_CONFIG_FRAC_SET(x) \ 853*5113495bSYour Name (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 854*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_GET(x) \ 855*5113495bSYour Name (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 856*5113495bSYour Name #define WLAN_PLL_SETTLE_TIME_SET(x) \ 857*5113495bSYour Name (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 858*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 859*5113495bSYour Name (((x) & \ 860*5113495bSYour Name WLAN_PLL_CONTROL_NOPWD_MASK) >> \ 861*5113495bSYour Name WLAN_PLL_CONTROL_NOPWD_LSB) 862*5113495bSYour Name #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 863*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & \ 864*5113495bSYour Name WLAN_PLL_CONTROL_NOPWD_MASK) 865*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 866*5113495bSYour Name (((x) & \ 867*5113495bSYour Name WLAN_PLL_CONTROL_BYPASS_MASK) >> \ 868*5113495bSYour Name WLAN_PLL_CONTROL_BYPASS_LSB) 869*5113495bSYour Name #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 870*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & \ 871*5113495bSYour Name WLAN_PLL_CONTROL_BYPASS_MASK) 872*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 873*5113495bSYour Name (((x) & \ 874*5113495bSYour Name WLAN_PLL_CONTROL_CLK_SEL_MASK) >> \ 875*5113495bSYour Name WLAN_PLL_CONTROL_CLK_SEL_LSB) 876*5113495bSYour Name #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 877*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & \ 878*5113495bSYour Name WLAN_PLL_CONTROL_CLK_SEL_MASK) 879*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 880*5113495bSYour Name (((x) & \ 881*5113495bSYour Name WLAN_PLL_CONTROL_REFDIV_MASK) >> \ 882*5113495bSYour Name WLAN_PLL_CONTROL_REFDIV_LSB) 883*5113495bSYour Name #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 884*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & \ 885*5113495bSYour Name WLAN_PLL_CONTROL_REFDIV_MASK) 886*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_GET(x) \ 887*5113495bSYour Name (((x) & \ 888*5113495bSYour Name WLAN_PLL_CONTROL_DIV_MASK) >> \ 889*5113495bSYour Name WLAN_PLL_CONTROL_DIV_LSB) 890*5113495bSYour Name #define WLAN_PLL_CONTROL_DIV_SET(x) \ 891*5113495bSYour Name (((x) << WLAN_PLL_CONTROL_DIV_LSB) & \ 892*5113495bSYour Name WLAN_PLL_CONTROL_DIV_MASK) 893*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 894*5113495bSYour Name (((x) & \ 895*5113495bSYour Name SOC_CORE_CLK_CTRL_DIV_MASK) >> \ 896*5113495bSYour Name SOC_CORE_CLK_CTRL_DIV_LSB) 897*5113495bSYour Name #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 898*5113495bSYour Name (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & \ 899*5113495bSYour Name SOC_CORE_CLK_CTRL_DIV_MASK) 900*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 901*5113495bSYour Name (((x) & \ 902*5113495bSYour Name RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 903*5113495bSYour Name RTC_SYNC_STATUS_PLL_CHANGING_LSB) 904*5113495bSYour Name #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 905*5113495bSYour Name (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 906*5113495bSYour Name RTC_SYNC_STATUS_PLL_CHANGING_MASK) 907*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 908*5113495bSYour Name (((x) & \ 909*5113495bSYour Name SOC_CPU_CLOCK_STANDARD_MASK) >> \ 910*5113495bSYour Name SOC_CPU_CLOCK_STANDARD_LSB) 911*5113495bSYour Name #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 912*5113495bSYour Name (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & \ 913*5113495bSYour Name SOC_CPU_CLOCK_STANDARD_MASK) 914*5113495bSYour Name /* PLL end */ 915*5113495bSYour Name 916*5113495bSYour Name struct hostdef_s { 917*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; 918*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; 919*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_CPU_LSB; 920*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_CPU_MASK; 921*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; 922*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; 923*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; 924*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; 925*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; 926*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; 927*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; 928*5113495bSYour Name uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; 929*5113495bSYour Name uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; 930*5113495bSYour Name uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; 931*5113495bSYour Name uint32_t d_INT_STATUS_ENABLE_ADDRESS; 932*5113495bSYour Name uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; 933*5113495bSYour Name uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; 934*5113495bSYour Name uint32_t d_HOST_INT_STATUS_ADDRESS; 935*5113495bSYour Name uint32_t d_CPU_INT_STATUS_ADDRESS; 936*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_ADDRESS; 937*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; 938*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; 939*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; 940*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; 941*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; 942*5113495bSYour Name uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; 943*5113495bSYour Name uint32_t d_COUNT_DEC_ADDRESS; 944*5113495bSYour Name uint32_t d_HOST_INT_STATUS_CPU_MASK; 945*5113495bSYour Name uint32_t d_HOST_INT_STATUS_CPU_LSB; 946*5113495bSYour Name uint32_t d_HOST_INT_STATUS_ERROR_MASK; 947*5113495bSYour Name uint32_t d_HOST_INT_STATUS_ERROR_LSB; 948*5113495bSYour Name uint32_t d_HOST_INT_STATUS_COUNTER_MASK; 949*5113495bSYour Name uint32_t d_HOST_INT_STATUS_COUNTER_LSB; 950*5113495bSYour Name uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; 951*5113495bSYour Name uint32_t d_WINDOW_DATA_ADDRESS; 952*5113495bSYour Name uint32_t d_WINDOW_READ_ADDR_ADDRESS; 953*5113495bSYour Name uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; 954*5113495bSYour Name uint32_t d_SOC_GLOBAL_RESET_ADDRESS; 955*5113495bSYour Name uint32_t d_RTC_STATE_ADDRESS; 956*5113495bSYour Name uint32_t d_RTC_STATE_COLD_RESET_MASK; 957*5113495bSYour Name uint32_t d_PCIE_LOCAL_BASE_ADDRESS; 958*5113495bSYour Name uint32_t d_PCIE_SOC_WAKE_RESET; 959*5113495bSYour Name uint32_t d_PCIE_SOC_WAKE_ADDRESS; 960*5113495bSYour Name uint32_t d_PCIE_SOC_WAKE_V_MASK; 961*5113495bSYour Name uint32_t d_RTC_STATE_V_MASK; 962*5113495bSYour Name uint32_t d_RTC_STATE_V_LSB; 963*5113495bSYour Name uint32_t d_FW_IND_EVENT_PENDING; 964*5113495bSYour Name uint32_t d_FW_IND_INITIALIZED; 965*5113495bSYour Name uint32_t d_RTC_STATE_V_ON; 966*5113495bSYour Name #if defined(SDIO_3_0) 967*5113495bSYour Name uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; 968*5113495bSYour Name uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; 969*5113495bSYour Name #endif 970*5113495bSYour Name uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS; 971*5113495bSYour Name uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK; 972*5113495bSYour Name uint32_t d_SOC_PCIE_BASE_ADDRESS; 973*5113495bSYour Name uint32_t d_MSI_MAGIC_ADR_ADDRESS; 974*5113495bSYour Name uint32_t d_MSI_MAGIC_ADDRESS; 975*5113495bSYour Name }; 976*5113495bSYour Name 977*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_LSB \ 978*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 979*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_MASK \ 980*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 981*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_LSB \ 982*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 983*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_MASK \ 984*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 985*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_LSB \ 986*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 987*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_MASK \ 988*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 989*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 990*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 991*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 992*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 993*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 994*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 995*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 996*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 997*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB\ 998*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 999*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 1000*5113495bSYour Name (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 1001*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 1002*5113495bSYour Name (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 1003*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 1004*5113495bSYour Name (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 1005*5113495bSYour Name #define INT_STATUS_ENABLE_ADDRESS \ 1006*5113495bSYour Name (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 1007*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 1008*5113495bSYour Name (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 1009*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 1010*5113495bSYour Name (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 1011*5113495bSYour Name #define HOST_INT_STATUS_ADDRESS \ 1012*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 1013*5113495bSYour Name #define CPU_INT_STATUS_ADDRESS \ 1014*5113495bSYour Name (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 1015*5113495bSYour Name #define ERROR_INT_STATUS_ADDRESS \ 1016*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 1017*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_MASK \ 1018*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 1019*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_LSB \ 1020*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 1021*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 1022*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 1023*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 1024*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 1025*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 1026*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 1027*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 1028*5113495bSYour Name (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 1029*5113495bSYour Name #define COUNT_DEC_ADDRESS \ 1030*5113495bSYour Name (scn->hostdef->d_COUNT_DEC_ADDRESS) 1031*5113495bSYour Name #define HOST_INT_STATUS_CPU_MASK \ 1032*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 1033*5113495bSYour Name #define HOST_INT_STATUS_CPU_LSB \ 1034*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 1035*5113495bSYour Name #define HOST_INT_STATUS_ERROR_MASK \ 1036*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 1037*5113495bSYour Name #define HOST_INT_STATUS_ERROR_LSB \ 1038*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 1039*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_MASK \ 1040*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 1041*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_LSB \ 1042*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 1043*5113495bSYour Name #define RX_LOOKAHEAD_VALID_ADDRESS \ 1044*5113495bSYour Name (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 1045*5113495bSYour Name #define WINDOW_DATA_ADDRESS \ 1046*5113495bSYour Name (scn->hostdef->d_WINDOW_DATA_ADDRESS) 1047*5113495bSYour Name #define WINDOW_READ_ADDR_ADDRESS \ 1048*5113495bSYour Name (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 1049*5113495bSYour Name #define WINDOW_WRITE_ADDR_ADDRESS \ 1050*5113495bSYour Name (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 1051*5113495bSYour Name #define SOC_GLOBAL_RESET_ADDRESS \ 1052*5113495bSYour Name (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 1053*5113495bSYour Name #define RTC_STATE_ADDRESS \ 1054*5113495bSYour Name (scn->hostdef->d_RTC_STATE_ADDRESS) 1055*5113495bSYour Name #define RTC_STATE_COLD_RESET_MASK \ 1056*5113495bSYour Name (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 1057*5113495bSYour Name #define PCIE_LOCAL_BASE_ADDRESS \ 1058*5113495bSYour Name (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS) 1059*5113495bSYour Name #define PCIE_SOC_WAKE_RESET \ 1060*5113495bSYour Name (scn->hostdef->d_PCIE_SOC_WAKE_RESET) 1061*5113495bSYour Name #define PCIE_SOC_WAKE_ADDRESS \ 1062*5113495bSYour Name (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS) 1063*5113495bSYour Name #define PCIE_SOC_WAKE_V_MASK \ 1064*5113495bSYour Name (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK) 1065*5113495bSYour Name #define RTC_STATE_V_MASK \ 1066*5113495bSYour Name (scn->hostdef->d_RTC_STATE_V_MASK) 1067*5113495bSYour Name #define RTC_STATE_V_LSB \ 1068*5113495bSYour Name (scn->hostdef->d_RTC_STATE_V_LSB) 1069*5113495bSYour Name #define FW_IND_EVENT_PENDING \ 1070*5113495bSYour Name (scn->hostdef->d_FW_IND_EVENT_PENDING) 1071*5113495bSYour Name #define FW_IND_INITIALIZED \ 1072*5113495bSYour Name (scn->hostdef->d_FW_IND_INITIALIZED) 1073*5113495bSYour Name #define RTC_STATE_V_ON \ 1074*5113495bSYour Name (scn->hostdef->d_RTC_STATE_V_ON) 1075*5113495bSYour Name #if defined(SDIO_3_0) 1076*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_MASK \ 1077*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 1078*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_LSB \ 1079*5113495bSYour Name (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 1080*5113495bSYour Name #endif 1081*5113495bSYour Name 1082*5113495bSYour Name #if !defined(SOC_PCIE_BASE_ADDRESS) 1083*5113495bSYour Name #define SOC_PCIE_BASE_ADDRESS 0 1084*5113495bSYour Name #endif 1085*5113495bSYour Name 1086*5113495bSYour Name #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS) 1087*5113495bSYour Name #define PCIE_SOC_RDY_STATUS_ADDRESS 0 1088*5113495bSYour Name #define PCIE_SOC_RDY_STATUS_BAR_MASK 0 1089*5113495bSYour Name #endif 1090*5113495bSYour Name 1091*5113495bSYour Name #if !defined(MSI_MAGIC_ADR_ADDRESS) 1092*5113495bSYour Name #define MSI_MAGIC_ADR_ADDRESS 0 1093*5113495bSYour Name #define MSI_MAGIC_ADDRESS 0 1094*5113495bSYour Name #endif 1095*5113495bSYour Name 1096*5113495bSYour Name /* SET/GET macros */ 1097*5113495bSYour Name #define INT_STATUS_ENABLE_ERROR_SET(x) \ 1098*5113495bSYour Name (((x) << INT_STATUS_ENABLE_ERROR_LSB) & \ 1099*5113495bSYour Name INT_STATUS_ENABLE_ERROR_MASK) 1100*5113495bSYour Name #define INT_STATUS_ENABLE_CPU_SET(x) \ 1101*5113495bSYour Name (((x) << INT_STATUS_ENABLE_CPU_LSB) & \ 1102*5113495bSYour Name INT_STATUS_ENABLE_CPU_MASK) 1103*5113495bSYour Name #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 1104*5113495bSYour Name (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 1105*5113495bSYour Name INT_STATUS_ENABLE_COUNTER_MASK) 1106*5113495bSYour Name #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 1107*5113495bSYour Name (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 1108*5113495bSYour Name INT_STATUS_ENABLE_MBOX_DATA_MASK) 1109*5113495bSYour Name #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 1110*5113495bSYour Name (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 1111*5113495bSYour Name CPU_INT_STATUS_ENABLE_BIT_MASK) 1112*5113495bSYour Name #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 1113*5113495bSYour Name (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 1114*5113495bSYour Name ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 1115*5113495bSYour Name #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)\ 1116*5113495bSYour Name (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 1117*5113495bSYour Name ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 1118*5113495bSYour Name #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 1119*5113495bSYour Name (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 1120*5113495bSYour Name COUNTER_INT_STATUS_ENABLE_BIT_MASK) 1121*5113495bSYour Name #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 1122*5113495bSYour Name (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 1123*5113495bSYour Name ERROR_INT_STATUS_WAKEUP_LSB) 1124*5113495bSYour Name #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 1125*5113495bSYour Name (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 1126*5113495bSYour Name ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 1127*5113495bSYour Name #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 1128*5113495bSYour Name (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 1129*5113495bSYour Name ERROR_INT_STATUS_TX_OVERFLOW_LSB) 1130*5113495bSYour Name #define HOST_INT_STATUS_CPU_GET(x) \ 1131*5113495bSYour Name (((x) & HOST_INT_STATUS_CPU_MASK) >> \ 1132*5113495bSYour Name HOST_INT_STATUS_CPU_LSB) 1133*5113495bSYour Name #define HOST_INT_STATUS_ERROR_GET(x) \ 1134*5113495bSYour Name (((x) & HOST_INT_STATUS_ERROR_MASK) >> \ 1135*5113495bSYour Name HOST_INT_STATUS_ERROR_LSB) 1136*5113495bSYour Name #define HOST_INT_STATUS_COUNTER_GET(x) \ 1137*5113495bSYour Name (((x) & HOST_INT_STATUS_COUNTER_MASK) >> \ 1138*5113495bSYour Name HOST_INT_STATUS_COUNTER_LSB) 1139*5113495bSYour Name #define RTC_STATE_V_GET(x) \ 1140*5113495bSYour Name (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1141*5113495bSYour Name #if defined(SDIO_3_0) 1142*5113495bSYour Name #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 1143*5113495bSYour Name (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 1144*5113495bSYour Name HOST_INT_STATUS_MBOX_DATA_LSB) 1145*5113495bSYour Name #endif 1146*5113495bSYour Name 1147*5113495bSYour Name #define INVALID_REG_LOC_DUMMY_DATA 0xAA 1148*5113495bSYour Name 1149*5113495bSYour Name 1150*5113495bSYour Name 1151*5113495bSYour Name #define ROME_USB_RTC_SOC_BASE_ADDRESS 0x00000800 1152*5113495bSYour Name #define ROME_USB_SOC_RESET_CONTROL_COLD_RST_LSB 0x0 1153*5113495bSYour Name #define SOC_RESET_CONTROL_COLD_RST_LSB 8 1154*5113495bSYour Name #define SOC_RESET_CONTROL_COLD_RST_MASK 0x00000100 1155*5113495bSYour Name #define SOC_RESET_CONTROL_COLD_RST_SET(x) \ 1156*5113495bSYour Name (((x) << SOC_RESET_CONTROL_COLD_RST_LSB) & \ 1157*5113495bSYour Name SOC_RESET_CONTROL_COLD_RST_MASK) 1158*5113495bSYour Name 1159*5113495bSYour Name #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 1160*5113495bSYour Name #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 1161*5113495bSYour Name #define AR6320_CPU_SPEED_ADDR 0x403fa4 1162*5113495bSYour Name #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 1163*5113495bSYour Name #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 1164*5113495bSYour Name #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 1165*5113495bSYour Name #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 1166*5113495bSYour Name #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 1167*5113495bSYour Name #define AR6320V3_CPU_SPEED_ADDR 0x404024 1168*5113495bSYour Name 1169*5113495bSYour Name enum a_refclk_speed_t { 1170*5113495bSYour Name /* Unsupported ref clock -- use PLL Bypass */ 1171*5113495bSYour Name SOC_REFCLK_UNKNOWN = -1, 1172*5113495bSYour Name SOC_REFCLK_48_MHZ = 0, 1173*5113495bSYour Name SOC_REFCLK_19_2_MHZ = 1, 1174*5113495bSYour Name SOC_REFCLK_24_MHZ = 2, 1175*5113495bSYour Name SOC_REFCLK_26_MHZ = 3, 1176*5113495bSYour Name SOC_REFCLK_37_4_MHZ = 4, 1177*5113495bSYour Name SOC_REFCLK_38_4_MHZ = 5, 1178*5113495bSYour Name SOC_REFCLK_40_MHZ = 6, 1179*5113495bSYour Name SOC_REFCLK_52_MHZ = 7, 1180*5113495bSYour Name }; 1181*5113495bSYour Name 1182*5113495bSYour Name #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 1183*5113495bSYour Name #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 1184*5113495bSYour Name #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 1185*5113495bSYour Name #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 1186*5113495bSYour Name #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 1187*5113495bSYour Name #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 1188*5113495bSYour Name #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 1189*5113495bSYour Name #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 1190*5113495bSYour Name #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 1191*5113495bSYour Name 1192*5113495bSYour Name #define TARGET_CPU_FREQ 176000000 1193*5113495bSYour Name 1194*5113495bSYour Name struct wlan_pll_s { 1195*5113495bSYour Name u_int32_t refdiv; 1196*5113495bSYour Name u_int32_t div; 1197*5113495bSYour Name u_int32_t rnfrac; 1198*5113495bSYour Name u_int32_t outdiv; 1199*5113495bSYour Name }; 1200*5113495bSYour Name 1201*5113495bSYour Name struct cmnos_clock_s { 1202*5113495bSYour Name enum a_refclk_speed_t refclk_speed; 1203*5113495bSYour Name u_int32_t refclk_hz; 1204*5113495bSYour Name u_int32_t pll_settling_time; /* 50us */ 1205*5113495bSYour Name struct wlan_pll_s wlan_pll; 1206*5113495bSYour Name }; 1207*5113495bSYour Name 1208*5113495bSYour Name struct tgt_reg_section { 1209*5113495bSYour Name u_int32_t start_addr; 1210*5113495bSYour Name u_int32_t end_addr; 1211*5113495bSYour Name }; 1212*5113495bSYour Name 1213*5113495bSYour Name struct tgt_reg_table { 1214*5113495bSYour Name const struct tgt_reg_section *section; 1215*5113495bSYour Name u_int32_t section_size; 1216*5113495bSYour Name }; 1217*5113495bSYour Name 1218*5113495bSYour Name void target_register_tbl_attach(struct hif_softc *scn, 1219*5113495bSYour Name uint32_t target_type); 1220*5113495bSYour Name void hif_register_tbl_attach(struct hif_softc *scn, 1221*5113495bSYour Name uint32_t target_type); 1222*5113495bSYour Name #endif 1223