xref: /wlan-driver/qca-wifi-host-cmn/hif/src/usb/regtable_usb.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef _REGTABLE_USB_H_
20 #define _REGTABLE_USB_H_
21 #include "if_usb.h"
22 
23 #define MISSING  0
24 
25 struct targetdef_s {
26 	u_int32_t d_RTC_SOC_BASE_ADDRESS;
27 	u_int32_t d_RTC_WMAC_BASE_ADDRESS;
28 	u_int32_t d_SYSTEM_SLEEP_OFFSET;
29 	u_int32_t d_WLAN_SYSTEM_SLEEP_OFFSET;
30 	u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
31 	u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
32 	u_int32_t d_CLOCK_CONTROL_OFFSET;
33 	u_int32_t d_CLOCK_CONTROL_SI0_CLK_MASK;
34 	u_int32_t d_RESET_CONTROL_OFFSET;
35 	u_int32_t d_RESET_CONTROL_MBOX_RST_MASK;
36 	u_int32_t d_RESET_CONTROL_SI0_RST_MASK;
37 	u_int32_t d_WLAN_RESET_CONTROL_OFFSET;
38 	u_int32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK;
39 	u_int32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK;
40 	u_int32_t d_GPIO_BASE_ADDRESS;
41 	u_int32_t d_GPIO_PIN0_OFFSET;
42 	u_int32_t d_GPIO_PIN1_OFFSET;
43 	u_int32_t d_GPIO_PIN0_CONFIG_MASK;
44 	u_int32_t d_GPIO_PIN1_CONFIG_MASK;
45 	u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB;
46 	u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK;
47 	u_int32_t d_SI_CONFIG_I2C_LSB;
48 	u_int32_t d_SI_CONFIG_I2C_MASK;
49 	u_int32_t d_SI_CONFIG_POS_SAMPLE_LSB;
50 	u_int32_t d_SI_CONFIG_POS_SAMPLE_MASK;
51 	u_int32_t d_SI_CONFIG_INACTIVE_CLK_LSB;
52 	u_int32_t d_SI_CONFIG_INACTIVE_CLK_MASK;
53 	u_int32_t d_SI_CONFIG_INACTIVE_DATA_LSB;
54 	u_int32_t d_SI_CONFIG_INACTIVE_DATA_MASK;
55 	u_int32_t d_SI_CONFIG_DIVIDER_LSB;
56 	u_int32_t d_SI_CONFIG_DIVIDER_MASK;
57 	u_int32_t d_SI_BASE_ADDRESS;
58 	u_int32_t d_SI_CONFIG_OFFSET;
59 	u_int32_t d_SI_TX_DATA0_OFFSET;
60 	u_int32_t d_SI_TX_DATA1_OFFSET;
61 	u_int32_t d_SI_RX_DATA0_OFFSET;
62 	u_int32_t d_SI_RX_DATA1_OFFSET;
63 	u_int32_t d_SI_CS_OFFSET;
64 	u_int32_t d_SI_CS_DONE_ERR_MASK;
65 	u_int32_t d_SI_CS_DONE_INT_MASK;
66 	u_int32_t d_SI_CS_START_LSB;
67 	u_int32_t d_SI_CS_START_MASK;
68 	u_int32_t d_SI_CS_RX_CNT_LSB;
69 	u_int32_t d_SI_CS_RX_CNT_MASK;
70 	u_int32_t d_SI_CS_TX_CNT_LSB;
71 	u_int32_t d_SI_CS_TX_CNT_MASK;
72 	u_int32_t d_BOARD_DATA_SZ;
73 	u_int32_t d_BOARD_EXT_DATA_SZ;
74 	u_int32_t d_MBOX_BASE_ADDRESS;
75 	u_int32_t d_LOCAL_SCRATCH_OFFSET;
76 	u_int32_t d_CPU_CLOCK_OFFSET;
77 	u_int32_t d_LPO_CAL_OFFSET;
78 	u_int32_t d_GPIO_PIN10_OFFSET;
79 	u_int32_t d_GPIO_PIN11_OFFSET;
80 	u_int32_t d_GPIO_PIN12_OFFSET;
81 	u_int32_t d_GPIO_PIN13_OFFSET;
82 	u_int32_t d_CLOCK_GPIO_OFFSET;
83 	u_int32_t d_CPU_CLOCK_STANDARD_LSB;
84 	u_int32_t d_CPU_CLOCK_STANDARD_MASK;
85 	u_int32_t d_LPO_CAL_ENABLE_LSB;
86 	u_int32_t d_LPO_CAL_ENABLE_MASK;
87 	u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
88 	u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
89 	u_int32_t d_ANALOG_INTF_BASE_ADDRESS;
90 	u_int32_t d_WLAN_MAC_BASE_ADDRESS;
91 	u_int32_t d_CE0_BASE_ADDRESS;
92 	u_int32_t d_CE1_BASE_ADDRESS;
93 	u_int32_t d_FW_INDICATOR_ADDRESS;
94 	u_int32_t d_DRAM_BASE_ADDRESS;
95 	u_int32_t d_SOC_CORE_BASE_ADDRESS;
96 	u_int32_t d_CORE_CTRL_ADDRESS;
97 	u_int32_t d_CE_COUNT;
98 	u_int32_t d_MSI_NUM_REQUEST;
99 	u_int32_t d_MSI_ASSIGN_FW;
100 	u_int32_t d_MSI_ASSIGN_CE_INITIAL;
101 	u_int32_t d_PCIE_INTR_ENABLE_ADDRESS;
102 	u_int32_t d_PCIE_INTR_CLR_ADDRESS;
103 	u_int32_t d_PCIE_INTR_FIRMWARE_MASK;
104 	u_int32_t d_PCIE_INTR_CE_MASK_ALL;
105 	u_int32_t d_CORE_CTRL_CPU_INTR_MASK;
106 	u_int32_t d_SR_WR_INDEX_ADDRESS;
107 	u_int32_t d_DST_WATERMARK_ADDRESS;
108 
109 	/* htt_rx.c */
110 	u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
111 	u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
112 	uint32_t d_RX_MPDU_START_0_RETRY_LSB;
113 	uint32_t d_RX_MPDU_START_0_RETRY_MASK;
114 	u_int32_t d_RX_MPDU_START_0_SEQ_NUM_MASK;
115 	u_int32_t d_RX_MPDU_START_0_SEQ_NUM_LSB;
116 	u_int32_t d_RX_MPDU_START_2_PN_47_32_LSB;
117 	u_int32_t d_RX_MPDU_START_2_PN_47_32_MASK;
118 	uint32_t d_RX_MPDU_START_2_TID_LSB;
119 	uint32_t d_RX_MPDU_START_2_TID_MASK;
120 	u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK;
121 	u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB;
122 	u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK;
123 	u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB;
124 	u_int32_t d_RX_MSDU_END_4_LAST_MSDU_MASK;
125 	u_int32_t d_RX_MSDU_END_4_LAST_MSDU_LSB;
126 	u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK;
127 	u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB;
128 	u_int32_t d_RX_ATTENTION_0_FRAGMENT_MASK;
129 	u_int32_t d_RX_ATTENTION_0_FRAGMENT_LSB;
130 	u_int32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK;
131 	u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK;
132 	u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB;
133 	u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK;
134 	u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB;
135 	u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET;
136 	u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK;
137 	u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB;
138 	u_int32_t d_RX_MPDU_START_0_ENCRYPTED_MASK;
139 	u_int32_t d_RX_MPDU_START_0_ENCRYPTED_LSB;
140 	u_int32_t d_RX_ATTENTION_0_MORE_DATA_MASK;
141 	u_int32_t d_RX_ATTENTION_0_MSDU_DONE_MASK;
142 	u_int32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK;
143 	/* end */
144 	/* copy_engine.c */
145 	u_int32_t d_DST_WR_INDEX_ADDRESS;
146 	u_int32_t d_SRC_WATERMARK_ADDRESS;
147 	u_int32_t d_SRC_WATERMARK_LOW_MASK;
148 	u_int32_t d_SRC_WATERMARK_HIGH_MASK;
149 	u_int32_t d_DST_WATERMARK_LOW_MASK;
150 	u_int32_t d_DST_WATERMARK_HIGH_MASK;
151 	u_int32_t d_CURRENT_SRRI_ADDRESS;
152 	u_int32_t d_CURRENT_DRRI_ADDRESS;
153 	u_int32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK;
154 	u_int32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK;
155 	u_int32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK;
156 	u_int32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK;
157 	u_int32_t d_HOST_IS_ADDRESS;
158 	u_int32_t d_HOST_IS_COPY_COMPLETE_MASK;
159 	u_int32_t d_CE_WRAPPER_BASE_ADDRESS;
160 	u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
161 	u_int32_t d_HOST_IE_ADDRESS;
162 	u_int32_t d_HOST_IE_COPY_COMPLETE_MASK;
163 	u_int32_t d_SR_BA_ADDRESS;
164 	u_int32_t d_SR_SIZE_ADDRESS;
165 	u_int32_t d_CE_CTRL1_ADDRESS;
166 	u_int32_t d_CE_CTRL1_DMAX_LENGTH_MASK;
167 	u_int32_t d_DR_BA_ADDRESS;
168 	u_int32_t d_DR_SIZE_ADDRESS;
169 	u_int32_t d_MISC_IE_ADDRESS;
170 	u_int32_t d_MISC_IS_AXI_ERR_MASK;
171 	u_int32_t d_MISC_IS_DST_ADDR_ERR_MASK;
172 	u_int32_t d_MISC_IS_SRC_LEN_ERR_MASK;
173 	u_int32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK;
174 	u_int32_t d_MISC_IS_DST_RING_OVERFLOW_MASK;
175 	u_int32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK;
176 	u_int32_t d_SRC_WATERMARK_LOW_LSB;
177 	u_int32_t d_SRC_WATERMARK_HIGH_LSB;
178 	u_int32_t d_DST_WATERMARK_LOW_LSB;
179 	u_int32_t d_DST_WATERMARK_HIGH_LSB;
180 	u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK;
181 	u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB;
182 	u_int32_t d_CE_CTRL1_DMAX_LENGTH_LSB;
183 	u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK;
184 	u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
185 	u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
186 	u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
187 	u_int32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
188 	u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
189 	u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
190 	u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
191 	u_int32_t d_WLAN_DEBUG_CONTROL_OFFSET;
192 	u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
193 	u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
194 	u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
195 	u_int32_t d_WLAN_DEBUG_OUT_OFFSET;
196 	u_int32_t d_WLAN_DEBUG_OUT_DATA_MSB;
197 	u_int32_t d_WLAN_DEBUG_OUT_DATA_LSB;
198 	u_int32_t d_WLAN_DEBUG_OUT_DATA_MASK;
199 	u_int32_t d_AMBA_DEBUG_BUS_OFFSET;
200 	u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB;
201 	u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB;
202 	u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
203 	u_int32_t d_AMBA_DEBUG_BUS_SEL_MSB;
204 	u_int32_t d_AMBA_DEBUG_BUS_SEL_LSB;
205 	u_int32_t d_AMBA_DEBUG_BUS_SEL_MASK;
206 	u_int32_t d_CE_WRAPPER_DEBUG_OFFSET;
207 	u_int32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
208 	u_int32_t d_CE_WRAPPER_DEBUG_SEL_LSB;
209 	u_int32_t d_CE_WRAPPER_DEBUG_SEL_MASK;
210 	u_int32_t d_CE_DEBUG_OFFSET;
211 	u_int32_t d_CE_DEBUG_SEL_MSB;
212 	u_int32_t d_CE_DEBUG_SEL_LSB;
213 	u_int32_t d_CE_DEBUG_SEL_MASK;
214 	/* end */
215 	/* PLL start */
216 	u_int32_t d_EFUSE_OFFSET;
217 	u_int32_t d_EFUSE_XTAL_SEL_MSB;
218 	u_int32_t d_EFUSE_XTAL_SEL_LSB;
219 	u_int32_t d_EFUSE_XTAL_SEL_MASK;
220 	u_int32_t d_BB_PLL_CONFIG_OFFSET;
221 	u_int32_t d_BB_PLL_CONFIG_OUTDIV_MSB;
222 	u_int32_t d_BB_PLL_CONFIG_OUTDIV_LSB;
223 	u_int32_t d_BB_PLL_CONFIG_OUTDIV_MASK;
224 	u_int32_t d_BB_PLL_CONFIG_FRAC_MSB;
225 	u_int32_t d_BB_PLL_CONFIG_FRAC_LSB;
226 	u_int32_t d_BB_PLL_CONFIG_FRAC_MASK;
227 	u_int32_t d_WLAN_PLL_SETTLE_TIME_MSB;
228 	u_int32_t d_WLAN_PLL_SETTLE_TIME_LSB;
229 	u_int32_t d_WLAN_PLL_SETTLE_TIME_MASK;
230 	u_int32_t d_WLAN_PLL_SETTLE_OFFSET;
231 	u_int32_t d_WLAN_PLL_SETTLE_SW_MASK;
232 	u_int32_t d_WLAN_PLL_SETTLE_RSTMASK;
233 	u_int32_t d_WLAN_PLL_SETTLE_RESET;
234 	u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MSB;
235 	u_int32_t d_WLAN_PLL_CONTROL_NOPWD_LSB;
236 	u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MASK;
237 	u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MSB;
238 	u_int32_t d_WLAN_PLL_CONTROL_BYPASS_LSB;
239 	u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MASK;
240 	u_int32_t d_WLAN_PLL_CONTROL_BYPASS_RESET;
241 	u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB;
242 	u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB;
243 	u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK;
244 	u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET;
245 	u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MSB;
246 	u_int32_t d_WLAN_PLL_CONTROL_REFDIV_LSB;
247 	u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MASK;
248 	u_int32_t d_WLAN_PLL_CONTROL_REFDIV_RESET;
249 	u_int32_t d_WLAN_PLL_CONTROL_DIV_MSB;
250 	u_int32_t d_WLAN_PLL_CONTROL_DIV_LSB;
251 	u_int32_t d_WLAN_PLL_CONTROL_DIV_MASK;
252 	u_int32_t d_WLAN_PLL_CONTROL_DIV_RESET;
253 	u_int32_t d_WLAN_PLL_CONTROL_OFFSET;
254 	u_int32_t d_WLAN_PLL_CONTROL_SW_MASK;
255 	u_int32_t d_WLAN_PLL_CONTROL_RSTMASK;
256 	u_int32_t d_WLAN_PLL_CONTROL_RESET;
257 	u_int32_t d_SOC_CORE_CLK_CTRL_OFFSET;
258 	u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MSB;
259 	u_int32_t d_SOC_CORE_CLK_CTRL_DIV_LSB;
260 	u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MASK;
261 	u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB;
262 	u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB;
263 	u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK;
264 	u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET;
265 	u_int32_t d_RTC_SYNC_STATUS_OFFSET;
266 	u_int32_t d_SOC_CPU_CLOCK_OFFSET;
267 	u_int32_t d_SOC_CPU_CLOCK_STANDARD_MSB;
268 	u_int32_t d_SOC_CPU_CLOCK_STANDARD_LSB;
269 	u_int32_t d_SOC_CPU_CLOCK_STANDARD_MASK;
270 	/* PLL end */
271 	u_int32_t d_SOC_POWER_REG_OFFSET;
272 	u_int32_t d_PCIE_INTR_CAUSE_ADDRESS;
273 	u_int32_t d_SOC_RESET_CONTROL_ADDRESS;
274 	u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK;
275 	u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB;
276 	u_int32_t d_SOC_RESET_CONTROL_CE_RST_MASK;
277 	u_int32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
278 	u_int32_t d_CPU_INTR_ADDRESS;
279 	u_int32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
280 	u_int32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
281 	u_int32_t d_SOC_LF_TIMER_STATUS0_ADDRESS;
282 	/* chip id start */
283 	u_int32_t d_SOC_CHIP_ID_ADDRESS;
284 	u_int32_t d_SOC_CHIP_ID_VERSION_MASK;
285 	u_int32_t d_SOC_CHIP_ID_VERSION_LSB;
286 	u_int32_t d_SOC_CHIP_ID_REVISION_MASK;
287 	u_int32_t d_SOC_CHIP_ID_REVISION_LSB;
288 	/* chip id end */
289 };
290 
291 #define RTC_SOC_BASE_ADDRESS               \
292 		(scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
293 #define RTC_WMAC_BASE_ADDRESS              \
294 		(scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
295 #define SYSTEM_SLEEP_OFFSET                \
296 		(scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
297 #define WLAN_SYSTEM_SLEEP_OFFSET           \
298 		(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
299 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB      \
300 		(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
301 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK     \
302 		(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
303 #define CLOCK_CONTROL_OFFSET               \
304 		(scn->targetdef->d_CLOCK_CONTROL_OFFSET)
305 #define CLOCK_CONTROL_SI0_CLK_MASK         \
306 		(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
307 #define RESET_CONTROL_OFFSET               \
308 		(scn->targetdef->d_RESET_CONTROL_OFFSET)
309 #define RESET_CONTROL_MBOX_RST_MASK        \
310 		(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
311 #define RESET_CONTROL_SI0_RST_MASK         \
312 		(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
313 #define WLAN_RESET_CONTROL_OFFSET          \
314 		(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
315 #define WLAN_RESET_CONTROL_COLD_RST_MASK   \
316 		(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
317 #define WLAN_RESET_CONTROL_WARM_RST_MASK   \
318 		(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
319 #define GPIO_BASE_ADDRESS                  \
320 		(scn->targetdef->d_GPIO_BASE_ADDRESS)
321 #define GPIO_PIN0_OFFSET                   \
322 		(scn->targetdef->d_GPIO_PIN0_OFFSET)
323 #define GPIO_PIN1_OFFSET                   \
324 		(scn->targetdef->d_GPIO_PIN1_OFFSET)
325 #define GPIO_PIN0_CONFIG_MASK              \
326 		(scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
327 #define GPIO_PIN1_CONFIG_MASK              \
328 		(scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
329 #define SI_CONFIG_BIDIR_OD_DATA_LSB        \
330 		(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
331 #define SI_CONFIG_BIDIR_OD_DATA_MASK       \
332 		(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
333 #define SI_CONFIG_I2C_LSB                  \
334 		(scn->targetdef->d_SI_CONFIG_I2C_LSB)
335 #define SI_CONFIG_I2C_MASK                 \
336 		(scn->targetdef->d_SI_CONFIG_I2C_MASK)
337 #define SI_CONFIG_POS_SAMPLE_LSB           \
338 		(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
339 #define SI_CONFIG_POS_SAMPLE_MASK          \
340 		(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
341 #define SI_CONFIG_INACTIVE_CLK_LSB         \
342 		(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
343 #define SI_CONFIG_INACTIVE_CLK_MASK        \
344 		(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
345 #define SI_CONFIG_INACTIVE_DATA_LSB        \
346 		(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
347 #define SI_CONFIG_INACTIVE_DATA_MASK       \
348 		(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
349 #define SI_CONFIG_DIVIDER_LSB              \
350 		(scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
351 #define SI_CONFIG_DIVIDER_MASK             \
352 		(scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
353 #define SI_BASE_ADDRESS                    \
354 		(scn->targetdef->d_SI_BASE_ADDRESS)
355 #define SI_CONFIG_OFFSET                   \
356 		(scn->targetdef->d_SI_CONFIG_OFFSET)
357 #define SI_TX_DATA0_OFFSET                 \
358 		(scn->targetdef->d_SI_TX_DATA0_OFFSET)
359 #define SI_TX_DATA1_OFFSET                 \
360 		(scn->targetdef->d_SI_TX_DATA1_OFFSET)
361 #define SI_RX_DATA0_OFFSET                 \
362 		(scn->targetdef->d_SI_RX_DATA0_OFFSET)
363 #define SI_RX_DATA1_OFFSET                 \
364 		(scn->targetdef->d_SI_RX_DATA1_OFFSET)
365 #define SI_CS_OFFSET                       \
366 		(scn->targetdef->d_SI_CS_OFFSET)
367 #define SI_CS_DONE_ERR_MASK                \
368 		(scn->targetdef->d_SI_CS_DONE_ERR_MASK)
369 #define SI_CS_DONE_INT_MASK                \
370 		(scn->targetdef->d_SI_CS_DONE_INT_MASK)
371 #define SI_CS_START_LSB                    \
372 		(scn->targetdef->d_SI_CS_START_LSB)
373 #define SI_CS_START_MASK                   \
374 		(scn->targetdef->d_SI_CS_START_MASK)
375 #define SI_CS_RX_CNT_LSB                   \
376 		(scn->targetdef->d_SI_CS_RX_CNT_LSB)
377 #define SI_CS_RX_CNT_MASK                  \
378 		(scn->targetdef->d_SI_CS_RX_CNT_MASK)
379 #define SI_CS_TX_CNT_LSB                   \
380 		(scn->targetdef->d_SI_CS_TX_CNT_LSB)
381 #define SI_CS_TX_CNT_MASK                  \
382 		(scn->targetdef->d_SI_CS_TX_CNT_MASK)
383 #define EEPROM_SZ                          \
384 		(scn->targetdef->d_BOARD_DATA_SZ)
385 #define EEPROM_EXT_SZ                      \
386 		(scn->targetdef->d_BOARD_EXT_DATA_SZ)
387 #define MBOX_BASE_ADDRESS                  \
388 		(scn->targetdef->d_MBOX_BASE_ADDRESS)
389 #define LOCAL_SCRATCH_OFFSET               \
390 		(scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
391 #define CPU_CLOCK_OFFSET                   \
392 		(scn->targetdef->d_CPU_CLOCK_OFFSET)
393 #define LPO_CAL_OFFSET                     \
394 		(scn->targetdef->d_LPO_CAL_OFFSET)
395 #define GPIO_PIN10_OFFSET                  \
396 		(scn->targetdef->d_GPIO_PIN10_OFFSET)
397 #define GPIO_PIN11_OFFSET                  \
398 		(scn->targetdef->d_GPIO_PIN11_OFFSET)
399 #define GPIO_PIN12_OFFSET                  \
400 		(scn->targetdef->d_GPIO_PIN12_OFFSET)
401 #define GPIO_PIN13_OFFSET                  \
402 		(scn->targetdef->d_GPIO_PIN13_OFFSET)
403 #define CLOCK_GPIO_OFFSET                  \
404 		(scn->targetdef->d_CLOCK_GPIO_OFFSET)
405 #define CPU_CLOCK_STANDARD_LSB             \
406 		(scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
407 #define CPU_CLOCK_STANDARD_MASK            \
408 		(scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
409 #define LPO_CAL_ENABLE_LSB                 \
410 		(scn->targetdef->d_LPO_CAL_ENABLE_LSB)
411 #define LPO_CAL_ENABLE_MASK                \
412 		(scn->targetdef->d_LPO_CAL_ENABLE_MASK)
413 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB       \
414 		(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
415 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK      \
416 		(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
417 #define ANALOG_INTF_BASE_ADDRESS           \
418 		(scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
419 #define WLAN_MAC_BASE_ADDRESS              \
420 		(scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
421 #define CE0_BASE_ADDRESS                   \
422 		(scn->targetdef->d_CE0_BASE_ADDRESS)
423 #define CE1_BASE_ADDRESS                   \
424 		(scn->targetdef->d_CE1_BASE_ADDRESS)
425 #define FW_INDICATOR_ADDRESS               \
426 		(scn->targetdef->d_FW_INDICATOR_ADDRESS)
427 #define DRAM_BASE_ADDRESS                  \
428 		(scn->targetdef->d_DRAM_BASE_ADDRESS)
429 #define SOC_CORE_BASE_ADDRESS              \
430 		(scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
431 #define CORE_CTRL_ADDRESS                  \
432 		(scn->targetdef->d_CORE_CTRL_ADDRESS)
433 #define CE_COUNT                           \
434 		(scn->targetdef->d_CE_COUNT)
435 #define PCIE_INTR_ENABLE_ADDRESS           \
436 		(scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
437 #define PCIE_INTR_CLR_ADDRESS              \
438 		(scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
439 #define PCIE_INTR_FIRMWARE_MASK            \
440 		(scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
441 #define PCIE_INTR_CE_MASK_ALL              \
442 		(scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
443 #define CORE_CTRL_CPU_INTR_MASK            \
444 		(scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
445 #define PCIE_INTR_CAUSE_ADDRESS            \
446 		(scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
447 #define SOC_RESET_CONTROL_ADDRESS          \
448 		(scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
449 #define SOC_RESET_CONTROL_CE_RST_MASK      \
450 		(scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
451 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK\
452 		(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
453 #define CPU_INTR_ADDRESS                   \
454 		(scn->targetdef->d_CPU_INTR_ADDRESS)
455 #define SOC_LF_TIMER_CONTROL0_ADDRESS      \
456 		(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
457 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK  \
458 		(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
459 #define SOC_LF_TIMER_STATUS0_ADDRESS      \
460 		(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
461 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
462 		(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
463 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \
464 		(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
465 
466 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \
467 	(((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \
468 		SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
469 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \
470 	(((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \
471 			SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
472 
473 /* hif_pci.c */
474 #define CHIP_ID_ADDRESS                    \
475 		(scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
476 #define SOC_CHIP_ID_REVISION_MASK          \
477 		(scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
478 #define SOC_CHIP_ID_REVISION_LSB           \
479 		(scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
480 #define SOC_CHIP_ID_VERSION_MASK           \
481 		(scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
482 #define SOC_CHIP_ID_VERSION_LSB            \
483 		(scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
484 #define CHIP_ID_REVISION_GET(x) \
485 		(((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB)
486 #define CHIP_ID_VERSION_GET(x) \
487 	(((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB)
488 /* hif_pci.c end */
489 
490 /* misc */
491 #define SR_WR_INDEX_ADDRESS                \
492 		(scn->targetdef->d_SR_WR_INDEX_ADDRESS)
493 #define DST_WATERMARK_ADDRESS              \
494 		(scn->targetdef->d_DST_WATERMARK_ADDRESS)
495 #define SOC_POWER_REG_OFFSET               \
496 		(scn->targetdef->d_SOC_POWER_REG_OFFSET)
497 /* end */
498 
499 /* copy_engine.c */
500 #define DST_WR_INDEX_ADDRESS               \
501 		(scn->targetdef->d_DST_WR_INDEX_ADDRESS)
502 #define SRC_WATERMARK_ADDRESS              \
503 		(scn->targetdef->d_SRC_WATERMARK_ADDRESS)
504 #define SRC_WATERMARK_LOW_MASK             \
505 		(scn->targetdef->d_SRC_WATERMARK_LOW_MASK)
506 #define SRC_WATERMARK_HIGH_MASK            \
507 		(scn->targetdef->d_SRC_WATERMARK_HIGH_MASK)
508 #define DST_WATERMARK_LOW_MASK             \
509 		(scn->targetdef->d_DST_WATERMARK_LOW_MASK)
510 #define DST_WATERMARK_HIGH_MASK            \
511 		(scn->targetdef->d_DST_WATERMARK_HIGH_MASK)
512 #define CURRENT_SRRI_ADDRESS               \
513 		(scn->targetdef->d_CURRENT_SRRI_ADDRESS)
514 #define CURRENT_DRRI_ADDRESS               \
515 		(scn->targetdef->d_CURRENT_DRRI_ADDRESS)
516 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
517 		(scn->targetdef->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
518 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK\
519 		(scn->targetdef->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
520 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
521 		(scn->targetdef->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
522 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK\
523 		(scn->targetdef->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
524 #define HOST_IS_ADDRESS                    \
525 		(scn->targetdef->d_HOST_IS_ADDRESS)
526 #define HOST_IS_COPY_COMPLETE_MASK         \
527 		(scn->targetdef->d_HOST_IS_COPY_COMPLETE_MASK)
528 #define CE_WRAPPER_BASE_ADDRESS            \
529 		(scn->targetdef->d_CE_WRAPPER_BASE_ADDRESS)
530 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \
531 		(scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
532 #define HOST_IE_ADDRESS                    \
533 		(scn->targetdef->d_HOST_IE_ADDRESS)
534 #define HOST_IE_COPY_COMPLETE_MASK         \
535 		(scn->targetdef->d_HOST_IE_COPY_COMPLETE_MASK)
536 #define SR_BA_ADDRESS                      \
537 		(scn->targetdef->d_SR_BA_ADDRESS)
538 #define SR_SIZE_ADDRESS                    \
539 		(scn->targetdef->d_SR_SIZE_ADDRESS)
540 #define CE_CTRL1_ADDRESS                   \
541 		(scn->targetdef->d_CE_CTRL1_ADDRESS)
542 #define CE_CTRL1_DMAX_LENGTH_MASK          \
543 		(scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_MASK)
544 #define DR_BA_ADDRESS                      \
545 		(scn->targetdef->d_DR_BA_ADDRESS)
546 #define DR_SIZE_ADDRESS                    \
547 		(scn->targetdef->d_DR_SIZE_ADDRESS)
548 #define MISC_IE_ADDRESS                    \
549 		(scn->targetdef->d_MISC_IE_ADDRESS)
550 #define MISC_IS_AXI_ERR_MASK               \
551 		(scn->targetdef->d_MISC_IS_AXI_ERR_MASK)
552 #define MISC_IS_DST_ADDR_ERR_MASK          \
553 		(scn->targetdef->d_MISC_IS_DST_ADDR_ERR_MASK)
554 #define MISC_IS_SRC_LEN_ERR_MASK           \
555 		(scn->targetdef->d_MISC_IS_SRC_LEN_ERR_MASK)
556 #define MISC_IS_DST_MAX_LEN_VIO_MASK       \
557 		(scn->targetdef->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
558 #define MISC_IS_DST_RING_OVERFLOW_MASK     \
559 		(scn->targetdef->d_MISC_IS_DST_RING_OVERFLOW_MASK)
560 #define MISC_IS_SRC_RING_OVERFLOW_MASK     \
561 		(scn->targetdef->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
562 #define SRC_WATERMARK_LOW_LSB              \
563 		(scn->targetdef->d_SRC_WATERMARK_LOW_LSB)
564 #define SRC_WATERMARK_HIGH_LSB             \
565 		(scn->targetdef->d_SRC_WATERMARK_HIGH_LSB)
566 #define DST_WATERMARK_LOW_LSB              \
567 		(scn->targetdef->d_DST_WATERMARK_LOW_LSB)
568 #define DST_WATERMARK_HIGH_LSB             \
569 		(scn->targetdef->d_DST_WATERMARK_HIGH_LSB)
570 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
571 		(scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
572 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  \
573 		(scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
574 #define CE_CTRL1_DMAX_LENGTH_LSB           \
575 		(scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_LSB)
576 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK\
577 		(scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
578 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK\
579 		(scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
580 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
581 		(scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
582 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
583 		(scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
584 #define WLAN_DEBUG_INPUT_SEL_OFFSET        \
585 		(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
586 #define WLAN_DEBUG_INPUT_SEL_SRC_MSB       \
587 		(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
588 #define WLAN_DEBUG_INPUT_SEL_SRC_LSB       \
589 		(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
590 #define WLAN_DEBUG_INPUT_SEL_SRC_MASK      \
591 		(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
592 #define WLAN_DEBUG_CONTROL_OFFSET          \
593 		(scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
594 #define WLAN_DEBUG_CONTROL_ENABLE_MSB      \
595 		(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
596 #define WLAN_DEBUG_CONTROL_ENABLE_LSB      \
597 		(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
598 #define WLAN_DEBUG_CONTROL_ENABLE_MASK     \
599 		(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
600 #define WLAN_DEBUG_OUT_OFFSET              \
601 		(scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
602 #define WLAN_DEBUG_OUT_DATA_MSB            \
603 		(scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
604 #define WLAN_DEBUG_OUT_DATA_LSB            \
605 		(scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
606 #define WLAN_DEBUG_OUT_DATA_MASK           \
607 		(scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
608 #define AMBA_DEBUG_BUS_OFFSET              \
609 		(scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
610 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB  \
611 		(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
612 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB  \
613 		(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
614 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \
615 		(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
616 #define AMBA_DEBUG_BUS_SEL_MSB             \
617 		(scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
618 #define AMBA_DEBUG_BUS_SEL_LSB             \
619 		(scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
620 #define AMBA_DEBUG_BUS_SEL_MASK            \
621 		(scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
622 #define CE_WRAPPER_DEBUG_OFFSET            \
623 		(scn->targetdef->d_CE_WRAPPER_DEBUG_OFFSET)
624 #define CE_WRAPPER_DEBUG_SEL_MSB           \
625 		(scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MSB)
626 #define CE_WRAPPER_DEBUG_SEL_LSB           \
627 		(scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_LSB)
628 #define CE_WRAPPER_DEBUG_SEL_MASK          \
629 		(scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MASK)
630 #define CE_DEBUG_OFFSET                    \
631 		(scn->targetdef->d_CE_DEBUG_OFFSET)
632 #define CE_DEBUG_SEL_MSB                   \
633 		(scn->targetdef->d_CE_DEBUG_SEL_MSB)
634 #define CE_DEBUG_SEL_LSB                   \
635 		(scn->targetdef->d_CE_DEBUG_SEL_LSB)
636 #define CE_DEBUG_SEL_MASK                  \
637 		(scn->targetdef->d_CE_DEBUG_SEL_MASK)
638 /* end */
639 /* PLL start */
640 #define EFUSE_OFFSET                       \
641 		(scn->targetdef->d_EFUSE_OFFSET)
642 #define EFUSE_XTAL_SEL_MSB                 \
643 		(scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
644 #define EFUSE_XTAL_SEL_LSB                 \
645 		(scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
646 #define EFUSE_XTAL_SEL_MASK                \
647 		(scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
648 #define BB_PLL_CONFIG_OFFSET               \
649 		(scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
650 #define BB_PLL_CONFIG_OUTDIV_MSB           \
651 		(scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
652 #define BB_PLL_CONFIG_OUTDIV_LSB           \
653 		(scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
654 #define BB_PLL_CONFIG_OUTDIV_MASK          \
655 		(scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
656 #define BB_PLL_CONFIG_FRAC_MSB             \
657 		(scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
658 #define BB_PLL_CONFIG_FRAC_LSB             \
659 		(scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
660 #define BB_PLL_CONFIG_FRAC_MASK            \
661 		(scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
662 #define WLAN_PLL_SETTLE_TIME_MSB           \
663 		(scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
664 #define WLAN_PLL_SETTLE_TIME_LSB           \
665 		(scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
666 #define WLAN_PLL_SETTLE_TIME_MASK          \
667 		(scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
668 #define WLAN_PLL_SETTLE_OFFSET             \
669 		(scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
670 #define WLAN_PLL_SETTLE_SW_MASK            \
671 		(scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
672 #define WLAN_PLL_SETTLE_RSTMASK            \
673 		(scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
674 #define WLAN_PLL_SETTLE_RESET              \
675 		(scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
676 #define WLAN_PLL_CONTROL_NOPWD_MSB         \
677 		(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
678 #define WLAN_PLL_CONTROL_NOPWD_LSB         \
679 		(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
680 #define WLAN_PLL_CONTROL_NOPWD_MASK        \
681 		(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
682 #define WLAN_PLL_CONTROL_BYPASS_MSB        \
683 		(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
684 #define WLAN_PLL_CONTROL_BYPASS_LSB        \
685 		(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
686 #define WLAN_PLL_CONTROL_BYPASS_MASK       \
687 		(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
688 #define WLAN_PLL_CONTROL_BYPASS_RESET      \
689 		(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
690 #define WLAN_PLL_CONTROL_CLK_SEL_MSB       \
691 		(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
692 #define WLAN_PLL_CONTROL_CLK_SEL_LSB       \
693 		(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
694 #define WLAN_PLL_CONTROL_CLK_SEL_MASK      \
695 		(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
696 #define WLAN_PLL_CONTROL_CLK_SEL_RESET     \
697 		(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
698 #define WLAN_PLL_CONTROL_REFDIV_MSB        \
699 		(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
700 #define WLAN_PLL_CONTROL_REFDIV_LSB        \
701 		(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
702 #define WLAN_PLL_CONTROL_REFDIV_MASK       \
703 		(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
704 #define WLAN_PLL_CONTROL_REFDIV_RESET      \
705 		(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
706 #define WLAN_PLL_CONTROL_DIV_MSB           \
707 		(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
708 #define WLAN_PLL_CONTROL_DIV_LSB           \
709 		(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
710 #define WLAN_PLL_CONTROL_DIV_MASK          \
711 		(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
712 #define WLAN_PLL_CONTROL_DIV_RESET         \
713 		(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
714 #define WLAN_PLL_CONTROL_OFFSET            \
715 		(scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
716 #define WLAN_PLL_CONTROL_SW_MASK           \
717 		(scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
718 #define WLAN_PLL_CONTROL_RSTMASK           \
719 		(scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
720 #define WLAN_PLL_CONTROL_RESET             \
721 		(scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
722 #define SOC_CORE_CLK_CTRL_OFFSET           \
723 		(scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
724 #define SOC_CORE_CLK_CTRL_DIV_MSB          \
725 		(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
726 #define SOC_CORE_CLK_CTRL_DIV_LSB          \
727 		(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
728 #define SOC_CORE_CLK_CTRL_DIV_MASK         \
729 		(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
730 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB   \
731 		(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
732 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB   \
733 		(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
734 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK  \
735 		(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
736 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \
737 		(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
738 #define RTC_SYNC_STATUS_OFFSET             \
739 		(scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
740 #define SOC_CPU_CLOCK_OFFSET               \
741 		(scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
742 #define SOC_CPU_CLOCK_STANDARD_MSB         \
743 		(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
744 #define SOC_CPU_CLOCK_STANDARD_LSB         \
745 		(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
746 #define SOC_CPU_CLOCK_STANDARD_MASK        \
747 		(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
748 /* PLL end */
749 
750 /* SET macros */
751 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x)       \
752 		(((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
753 				 WLAN_SYSTEM_SLEEP_DISABLE_MASK)
754 #define SI_CONFIG_BIDIR_OD_DATA_SET(x)         \
755 		(((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & \
756 				 SI_CONFIG_BIDIR_OD_DATA_MASK)
757 #define SI_CONFIG_I2C_SET(x)                   \
758 		(((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
759 #define SI_CONFIG_POS_SAMPLE_SET(x)            \
760 		(((x) << SI_CONFIG_POS_SAMPLE_LSB) & \
761 				 SI_CONFIG_POS_SAMPLE_MASK)
762 #define SI_CONFIG_INACTIVE_CLK_SET(x)          \
763 		(((x) << SI_CONFIG_INACTIVE_CLK_LSB) & \
764 				 SI_CONFIG_INACTIVE_CLK_MASK)
765 #define SI_CONFIG_INACTIVE_DATA_SET(x)         \
766 		(((x) << SI_CONFIG_INACTIVE_DATA_LSB) & \
767 				 SI_CONFIG_INACTIVE_DATA_MASK)
768 #define SI_CONFIG_DIVIDER_SET(x)               \
769 		(((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
770 #define SI_CS_START_SET(x)                     \
771 		(((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
772 #define SI_CS_RX_CNT_SET(x)                    \
773 		(((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
774 #define SI_CS_TX_CNT_SET(x)                    \
775 		(((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
776 #define LPO_CAL_ENABLE_SET(x)                  \
777 		(((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
778 #define CPU_CLOCK_STANDARD_SET(x)              \
779 		(((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
780 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x)        \
781 		(((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & \
782 				 CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
783 /* copy_engine.c */
784 #define SRC_WATERMARK_LOW_SET(x)               \
785 		(((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
786 #define SRC_WATERMARK_HIGH_SET(x)              \
787 		(((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
788 #define DST_WATERMARK_LOW_SET(x)               \
789 		(((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
790 #define DST_WATERMARK_HIGH_SET(x)              \
791 		(((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
792 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) (((x) & \
793 			CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
794 				CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
795 #define CE_CTRL1_DMAX_LENGTH_SET(x)            \
796 		(((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
797 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x)  \
798 		(((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
799 				 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
800 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x)  \
801 		(((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
802 				 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
803 #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x)        \
804 		(((x) & \
805 			 WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \
806 					WLAN_DEBUG_INPUT_SEL_SRC_LSB)
807 #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x)        \
808 		(((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \
809 				 WLAN_DEBUG_INPUT_SEL_SRC_MASK)
810 #define WLAN_DEBUG_CONTROL_ENABLE_GET(x)       \
811 		(((x) & \
812 			WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \
813 					WLAN_DEBUG_CONTROL_ENABLE_LSB)
814 #define WLAN_DEBUG_CONTROL_ENABLE_SET(x)       \
815 		(((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \
816 				 WLAN_DEBUG_CONTROL_ENABLE_MASK)
817 #define WLAN_DEBUG_OUT_DATA_GET(x)             \
818 		(((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
819 #define WLAN_DEBUG_OUT_DATA_SET(x)             \
820 		(((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
821 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x)   \
822 		(((x) & \
823 			AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \
824 					AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
825 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x)   \
826 		(((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \
827 				 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
828 #define AMBA_DEBUG_BUS_SEL_GET(x)              \
829 		(((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB)
830 #define AMBA_DEBUG_BUS_SEL_SET(x)              \
831 		(((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK)
832 #define CE_WRAPPER_DEBUG_SEL_GET(x)            \
833 		(((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB)
834 #define CE_WRAPPER_DEBUG_SEL_SET(x)            \
835 		(((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK)
836 #define CE_DEBUG_SEL_GET(x)                    \
837 		(((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
838 #define CE_DEBUG_SEL_SET(x)                    \
839 		(((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
840 /* end */
841 /* PLL start */
842 #define EFUSE_XTAL_SEL_GET(x)                  \
843 		(((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB)
844 #define EFUSE_XTAL_SEL_SET(x)                  \
845 		(((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK)
846 #define BB_PLL_CONFIG_OUTDIV_GET(x)            \
847 		(((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB)
848 #define BB_PLL_CONFIG_OUTDIV_SET(x)            \
849 		(((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK)
850 #define BB_PLL_CONFIG_FRAC_GET(x)              \
851 		(((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
852 #define BB_PLL_CONFIG_FRAC_SET(x)              \
853 		(((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
854 #define WLAN_PLL_SETTLE_TIME_GET(x)            \
855 		(((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
856 #define WLAN_PLL_SETTLE_TIME_SET(x)            \
857 		(((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
858 #define WLAN_PLL_CONTROL_NOPWD_GET(x)          \
859 		(((x) & \
860 				 WLAN_PLL_CONTROL_NOPWD_MASK) >> \
861 						WLAN_PLL_CONTROL_NOPWD_LSB)
862 #define WLAN_PLL_CONTROL_NOPWD_SET(x)          \
863 		(((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & \
864 				 WLAN_PLL_CONTROL_NOPWD_MASK)
865 #define WLAN_PLL_CONTROL_BYPASS_GET(x)         \
866 		(((x) & \
867 				 WLAN_PLL_CONTROL_BYPASS_MASK) >> \
868 						WLAN_PLL_CONTROL_BYPASS_LSB)
869 #define WLAN_PLL_CONTROL_BYPASS_SET(x)         \
870 		(((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & \
871 				 WLAN_PLL_CONTROL_BYPASS_MASK)
872 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x)        \
873 		(((x) & \
874 				 WLAN_PLL_CONTROL_CLK_SEL_MASK) >> \
875 						WLAN_PLL_CONTROL_CLK_SEL_LSB)
876 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x)        \
877 		(((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & \
878 				 WLAN_PLL_CONTROL_CLK_SEL_MASK)
879 #define WLAN_PLL_CONTROL_REFDIV_GET(x)         \
880 		(((x) & \
881 				 WLAN_PLL_CONTROL_REFDIV_MASK) >> \
882 						WLAN_PLL_CONTROL_REFDIV_LSB)
883 #define WLAN_PLL_CONTROL_REFDIV_SET(x)         \
884 		(((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & \
885 				 WLAN_PLL_CONTROL_REFDIV_MASK)
886 #define WLAN_PLL_CONTROL_DIV_GET(x)            \
887 		(((x) & \
888 			 WLAN_PLL_CONTROL_DIV_MASK) >> \
889 					WLAN_PLL_CONTROL_DIV_LSB)
890 #define WLAN_PLL_CONTROL_DIV_SET(x)            \
891 		(((x) << WLAN_PLL_CONTROL_DIV_LSB) & \
892 			 WLAN_PLL_CONTROL_DIV_MASK)
893 #define SOC_CORE_CLK_CTRL_DIV_GET(x)           \
894 		(((x) & \
895 			 SOC_CORE_CLK_CTRL_DIV_MASK) >> \
896 					SOC_CORE_CLK_CTRL_DIV_LSB)
897 #define SOC_CORE_CLK_CTRL_DIV_SET(x)           \
898 		(((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & \
899 			 SOC_CORE_CLK_CTRL_DIV_MASK)
900 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x)    \
901 		(((x) & \
902 			 RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \
903 					RTC_SYNC_STATUS_PLL_CHANGING_LSB)
904 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x)    \
905 		(((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \
906 			 RTC_SYNC_STATUS_PLL_CHANGING_MASK)
907 #define SOC_CPU_CLOCK_STANDARD_GET(x)          \
908 		(((x) & \
909 			 SOC_CPU_CLOCK_STANDARD_MASK) >> \
910 				 SOC_CPU_CLOCK_STANDARD_LSB)
911 #define SOC_CPU_CLOCK_STANDARD_SET(x)          \
912 		(((x) << SOC_CPU_CLOCK_STANDARD_LSB) & \
913 			 SOC_CPU_CLOCK_STANDARD_MASK)
914 /* PLL end */
915 
916 struct hostdef_s {
917 	uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
918 	uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
919 	uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
920 	uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
921 	uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
922 	uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
923 	uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
924 	uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
925 	uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
926 	uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
927 	uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
928 	uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
929 	uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
930 	uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
931 	uint32_t d_INT_STATUS_ENABLE_ADDRESS;
932 	uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
933 	uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
934 	uint32_t d_HOST_INT_STATUS_ADDRESS;
935 	uint32_t d_CPU_INT_STATUS_ADDRESS;
936 	uint32_t d_ERROR_INT_STATUS_ADDRESS;
937 	uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
938 	uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
939 	uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
940 	uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
941 	uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
942 	uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
943 	uint32_t d_COUNT_DEC_ADDRESS;
944 	uint32_t d_HOST_INT_STATUS_CPU_MASK;
945 	uint32_t d_HOST_INT_STATUS_CPU_LSB;
946 	uint32_t d_HOST_INT_STATUS_ERROR_MASK;
947 	uint32_t d_HOST_INT_STATUS_ERROR_LSB;
948 	uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
949 	uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
950 	uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
951 	uint32_t d_WINDOW_DATA_ADDRESS;
952 	uint32_t d_WINDOW_READ_ADDR_ADDRESS;
953 	uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
954 	uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
955 	uint32_t d_RTC_STATE_ADDRESS;
956 	uint32_t d_RTC_STATE_COLD_RESET_MASK;
957 	uint32_t d_PCIE_LOCAL_BASE_ADDRESS;
958 	uint32_t d_PCIE_SOC_WAKE_RESET;
959 	uint32_t d_PCIE_SOC_WAKE_ADDRESS;
960 	uint32_t d_PCIE_SOC_WAKE_V_MASK;
961 	uint32_t d_RTC_STATE_V_MASK;
962 	uint32_t d_RTC_STATE_V_LSB;
963 	uint32_t d_FW_IND_EVENT_PENDING;
964 	uint32_t d_FW_IND_INITIALIZED;
965 	uint32_t d_RTC_STATE_V_ON;
966 #if defined(SDIO_3_0)
967 	uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
968 	uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
969 #endif
970 	uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS;
971 	uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK;
972 	uint32_t d_SOC_PCIE_BASE_ADDRESS;
973 	uint32_t d_MSI_MAGIC_ADR_ADDRESS;
974 	uint32_t d_MSI_MAGIC_ADDRESS;
975 };
976 
977 #define INT_STATUS_ENABLE_ERROR_LSB        \
978 		(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
979 #define INT_STATUS_ENABLE_ERROR_MASK       \
980 		(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
981 #define INT_STATUS_ENABLE_CPU_LSB          \
982 		(scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
983 #define INT_STATUS_ENABLE_CPU_MASK         \
984 		(scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
985 #define INT_STATUS_ENABLE_COUNTER_LSB      \
986 		(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
987 #define INT_STATUS_ENABLE_COUNTER_MASK     \
988 		(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
989 #define INT_STATUS_ENABLE_MBOX_DATA_LSB    \
990 		(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
991 #define INT_STATUS_ENABLE_MBOX_DATA_MASK   \
992 		(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
993 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     \
994 		(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
995 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    \
996 		(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
997 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB\
998 		(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
999 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     \
1000 		(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
1001 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB  \
1002 		(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
1003 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \
1004 		(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
1005 #define INT_STATUS_ENABLE_ADDRESS          \
1006 		(scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
1007 #define CPU_INT_STATUS_ENABLE_BIT_LSB      \
1008 		(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
1009 #define CPU_INT_STATUS_ENABLE_BIT_MASK     \
1010 		(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
1011 #define HOST_INT_STATUS_ADDRESS            \
1012 		(scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
1013 #define CPU_INT_STATUS_ADDRESS             \
1014 		(scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
1015 #define ERROR_INT_STATUS_ADDRESS           \
1016 		(scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
1017 #define ERROR_INT_STATUS_WAKEUP_MASK       \
1018 		(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
1019 #define ERROR_INT_STATUS_WAKEUP_LSB        \
1020 		(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
1021 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \
1022 		(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
1023 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB  \
1024 		(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
1025 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK  \
1026 		(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
1027 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB   \
1028 		(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
1029 #define COUNT_DEC_ADDRESS                  \
1030 		(scn->hostdef->d_COUNT_DEC_ADDRESS)
1031 #define HOST_INT_STATUS_CPU_MASK           \
1032 		(scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
1033 #define HOST_INT_STATUS_CPU_LSB            \
1034 		(scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
1035 #define HOST_INT_STATUS_ERROR_MASK         \
1036 		(scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
1037 #define HOST_INT_STATUS_ERROR_LSB          \
1038 		(scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
1039 #define HOST_INT_STATUS_COUNTER_MASK       \
1040 		(scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
1041 #define HOST_INT_STATUS_COUNTER_LSB        \
1042 		(scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
1043 #define RX_LOOKAHEAD_VALID_ADDRESS         \
1044 		(scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
1045 #define WINDOW_DATA_ADDRESS                \
1046 		(scn->hostdef->d_WINDOW_DATA_ADDRESS)
1047 #define WINDOW_READ_ADDR_ADDRESS           \
1048 		(scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
1049 #define WINDOW_WRITE_ADDR_ADDRESS          \
1050 		(scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
1051 #define SOC_GLOBAL_RESET_ADDRESS           \
1052 		(scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
1053 #define RTC_STATE_ADDRESS                  \
1054 		(scn->hostdef->d_RTC_STATE_ADDRESS)
1055 #define RTC_STATE_COLD_RESET_MASK          \
1056 		(scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
1057 #define PCIE_LOCAL_BASE_ADDRESS            \
1058 		(scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
1059 #define PCIE_SOC_WAKE_RESET                \
1060 		(scn->hostdef->d_PCIE_SOC_WAKE_RESET)
1061 #define PCIE_SOC_WAKE_ADDRESS              \
1062 		(scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
1063 #define PCIE_SOC_WAKE_V_MASK               \
1064 		(scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
1065 #define RTC_STATE_V_MASK                   \
1066 		(scn->hostdef->d_RTC_STATE_V_MASK)
1067 #define RTC_STATE_V_LSB                    \
1068 		(scn->hostdef->d_RTC_STATE_V_LSB)
1069 #define FW_IND_EVENT_PENDING               \
1070 		(scn->hostdef->d_FW_IND_EVENT_PENDING)
1071 #define FW_IND_INITIALIZED                 \
1072 		(scn->hostdef->d_FW_IND_INITIALIZED)
1073 #define RTC_STATE_V_ON                     \
1074 		(scn->hostdef->d_RTC_STATE_V_ON)
1075 #if defined(SDIO_3_0)
1076 #define HOST_INT_STATUS_MBOX_DATA_MASK     \
1077 		(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
1078 #define HOST_INT_STATUS_MBOX_DATA_LSB      \
1079 		(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
1080 #endif
1081 
1082 #if !defined(SOC_PCIE_BASE_ADDRESS)
1083 #define SOC_PCIE_BASE_ADDRESS 0
1084 #endif
1085 
1086 #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS)
1087 #define PCIE_SOC_RDY_STATUS_ADDRESS 0
1088 #define PCIE_SOC_RDY_STATUS_BAR_MASK 0
1089 #endif
1090 
1091 #if !defined(MSI_MAGIC_ADR_ADDRESS)
1092 #define MSI_MAGIC_ADR_ADDRESS 0
1093 #define MSI_MAGIC_ADDRESS 0
1094 #endif
1095 
1096 /* SET/GET macros */
1097 #define INT_STATUS_ENABLE_ERROR_SET(x)        \
1098 		(((x) << INT_STATUS_ENABLE_ERROR_LSB) & \
1099 					INT_STATUS_ENABLE_ERROR_MASK)
1100 #define INT_STATUS_ENABLE_CPU_SET(x)          \
1101 		(((x) << INT_STATUS_ENABLE_CPU_LSB) & \
1102 				INT_STATUS_ENABLE_CPU_MASK)
1103 #define INT_STATUS_ENABLE_COUNTER_SET(x)      \
1104 		(((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \
1105 				INT_STATUS_ENABLE_COUNTER_MASK)
1106 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x)    \
1107 		(((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \
1108 				INT_STATUS_ENABLE_MBOX_DATA_MASK)
1109 #define CPU_INT_STATUS_ENABLE_BIT_SET(x)      \
1110 		(((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \
1111 				CPU_INT_STATUS_ENABLE_BIT_MASK)
1112 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \
1113 		(((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \
1114 				ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
1115 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)\
1116 		(((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \
1117 				ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
1118 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)  \
1119 		(((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \
1120 					COUNTER_INT_STATUS_ENABLE_BIT_MASK)
1121 #define ERROR_INT_STATUS_WAKEUP_GET(x)        \
1122 		(((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \
1123 				ERROR_INT_STATUS_WAKEUP_LSB)
1124 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)  \
1125 		(((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \
1126 					ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
1127 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)   \
1128 		(((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \
1129 					ERROR_INT_STATUS_TX_OVERFLOW_LSB)
1130 #define HOST_INT_STATUS_CPU_GET(x)            \
1131 		(((x) & HOST_INT_STATUS_CPU_MASK) >> \
1132 					HOST_INT_STATUS_CPU_LSB)
1133 #define HOST_INT_STATUS_ERROR_GET(x)          \
1134 		(((x) & HOST_INT_STATUS_ERROR_MASK) >> \
1135 					HOST_INT_STATUS_ERROR_LSB)
1136 #define HOST_INT_STATUS_COUNTER_GET(x)        \
1137 		(((x) & HOST_INT_STATUS_COUNTER_MASK) >> \
1138 					HOST_INT_STATUS_COUNTER_LSB)
1139 #define RTC_STATE_V_GET(x)                    \
1140 		(((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
1141 #if defined(SDIO_3_0)
1142 #define HOST_INT_STATUS_MBOX_DATA_GET(x)      \
1143 		(((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \
1144 					HOST_INT_STATUS_MBOX_DATA_LSB)
1145 #endif
1146 
1147 #define INVALID_REG_LOC_DUMMY_DATA 0xAA
1148 
1149 
1150 
1151 #define ROME_USB_RTC_SOC_BASE_ADDRESS		0x00000800
1152 #define ROME_USB_SOC_RESET_CONTROL_COLD_RST_LSB	0x0
1153 #define SOC_RESET_CONTROL_COLD_RST_LSB		8
1154 #define SOC_RESET_CONTROL_COLD_RST_MASK		0x00000100
1155 #define SOC_RESET_CONTROL_COLD_RST_SET(x)	\
1156 	(((x) << SOC_RESET_CONTROL_COLD_RST_LSB) & \
1157 	 SOC_RESET_CONTROL_COLD_RST_MASK)
1158 
1159 #define AR6320_CORE_CLK_DIV_ADDR	0x403fa8
1160 #define AR6320_CPU_PLL_INIT_DONE_ADDR	0x403fd0
1161 #define AR6320_CPU_SPEED_ADDR		0x403fa4
1162 #define AR6320V2_CORE_CLK_DIV_ADDR	0x403fd8
1163 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR	0x403fd0
1164 #define AR6320V2_CPU_SPEED_ADDR		0x403fd4
1165 #define AR6320V3_CORE_CLK_DIV_ADDR	0x404028
1166 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR	0x404020
1167 #define AR6320V3_CPU_SPEED_ADDR		0x404024
1168 
1169 enum a_refclk_speed_t {
1170 	/* Unsupported ref clock -- use PLL Bypass */
1171 	SOC_REFCLK_UNKNOWN   = -1,
1172 	SOC_REFCLK_48_MHZ    = 0,
1173 	SOC_REFCLK_19_2_MHZ  = 1,
1174 	SOC_REFCLK_24_MHZ    = 2,
1175 	SOC_REFCLK_26_MHZ    = 3,
1176 	SOC_REFCLK_37_4_MHZ  = 4,
1177 	SOC_REFCLK_38_4_MHZ  = 5,
1178 	SOC_REFCLK_40_MHZ    = 6,
1179 	SOC_REFCLK_52_MHZ    = 7,
1180 };
1181 
1182 #define A_REFCLK_UNKNOWN    SOC_REFCLK_UNKNOWN
1183 #define A_REFCLK_48_MHZ     SOC_REFCLK_48_MHZ
1184 #define A_REFCLK_19_2_MHZ   SOC_REFCLK_19_2_MHZ
1185 #define A_REFCLK_24_MHZ     SOC_REFCLK_24_MHZ
1186 #define A_REFCLK_26_MHZ     SOC_REFCLK_26_MHZ
1187 #define A_REFCLK_37_4_MHZ   SOC_REFCLK_37_4_MHZ
1188 #define A_REFCLK_38_4_MHZ   SOC_REFCLK_38_4_MHZ
1189 #define A_REFCLK_40_MHZ     SOC_REFCLK_40_MHZ
1190 #define A_REFCLK_52_MHZ     SOC_REFCLK_52_MHZ
1191 
1192 #define TARGET_CPU_FREQ 176000000
1193 
1194 struct wlan_pll_s {
1195 	u_int32_t refdiv;
1196 	u_int32_t div;
1197 	u_int32_t rnfrac;
1198 	u_int32_t outdiv;
1199 };
1200 
1201 struct cmnos_clock_s {
1202 	enum a_refclk_speed_t refclk_speed;
1203 	u_int32_t         refclk_hz;
1204 	u_int32_t         pll_settling_time; /* 50us */
1205 	struct wlan_pll_s   wlan_pll;
1206 };
1207 
1208 struct tgt_reg_section {
1209 	u_int32_t start_addr;
1210 	u_int32_t end_addr;
1211 };
1212 
1213 struct tgt_reg_table {
1214 	const struct tgt_reg_section *section;
1215 	u_int32_t section_size;
1216 };
1217 
1218 void target_register_tbl_attach(struct hif_softc *scn,
1219 					uint32_t target_type);
1220 void hif_register_tbl_attach(struct hif_softc *scn,
1221 					uint32_t target_type);
1222 #endif
1223